-
68 m 53 s
ftnTest
-
41 ms
frame formats
-
41 ms
passedshould show
-
show formats
data flow: portSize=132, period=72, size=9504, raw=8448
c0 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c1 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c2 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c3 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c4 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c5 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c6 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c7 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c8 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c9 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c10 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c11 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c12 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c13 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c14 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c15 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c16 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c17 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c18 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c19 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c20 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c21 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c22 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c23 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c24 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c25 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c26 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c27 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c28 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c29 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c30 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c31 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c32 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c33 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c34 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c35 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c36 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c37 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c38 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c39 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c40 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c41 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c42 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c43 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c44 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c45 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c46 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c47 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c48 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c49 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c50 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c51 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c52 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c53 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c54 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c55 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c56 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c57 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c58 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c59 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c60 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c61 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c62 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c63 ■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■■
c64
c65
c66
c67
c68
c69
c70
c71
-
1 m 12 s
convFtn
-
1 m 12 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on convFtn----
-
[INFO ]
-
: testing vector length: 820928, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 19:59:15
[Progress] at 0.000 : Elaborate components
[Progress] at 0.496 : Checks and transforms
[Progress] at 0.780 : Generate Verilog
[Warning] 1 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 0.972
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testConvFtn
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 2376.354 ms
[Progress] Start convFtn_dut test simulation with seed 1627601962
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 2153.402 ms
-
[INFO ]
-
: frames starts at 2, that is,simTime 56,
-
[INFO ]
-
: test for generator convFtn passed
101-th frame:
input :
0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 63 more elements...
1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 63 more elements...
0 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 63 more elements...
0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1 63 more elements...
56 more cycles...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
yours :
0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 190 more elements...
1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 190 more elements...
1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 190 more elements...
1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 190 more elements...
56 more cycles...
0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 190 more elements...
1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 190 more elements...
1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 190 more elements...
1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 190 more elements...
golden:
0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 190 more elements...
1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 190 more elements...
1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 190 more elements...
1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 190 more elements...
56 more cycles...
0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 190 more elements...
1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 190 more elements...
1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 190 more elements...
1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 190 more elements...
-
1 m 0 s
intrlvFtn
-
1 m 0 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on intrlvFtn----
-
[INFO ]
-
: testing vector length: 1641856, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:00:27
[Progress] at 71.870 : Elaborate components
[Progress] at 71.921 : Checks and transforms
[Progress] at 71.975 : Generate Verilog
[Warning] 1 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 72.022
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testIntrlvFtn
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 2202.058 ms
[Progress] Start intrlvFtn_dut test simulation with seed 1335945901
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 3531.842 ms
-
[INFO ]
-
: frames starts at 2, that is,simTime 56,
-
[INFO ]
-
: test for generator intrlvFtn passed
101-th frame:
input :
0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 190 more elements...
1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 190 more elements...
1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 190 more elements...
1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 190 more elements...
56 more cycles...
0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 190 more elements...
1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 190 more elements...
1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 190 more elements...
1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 190 more elements...
yours :
0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 190 more elements...
0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 190 more elements...
1 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 190 more elements...
0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 190 more elements...
56 more cycles...
0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 190 more elements...
1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 190 more elements...
0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 190 more elements...
0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 190 more elements...
golden:
0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 190 more elements...
0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 190 more elements...
1 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 190 more elements...
0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 190 more elements...
56 more cycles...
0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 190 more elements...
1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 190 more elements...
0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 190 more elements...
0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 190 more elements...
-
27.26 s
qammodFtn
-
27.26 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on QammodFtn----
-
[INFO ]
-
: testing vector length: 1641856, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:01:31
[Progress] at 135.436 : Elaborate components
-
[INFO ]
-
:
----qammod with bit & power alloc----
bitAlloc for adaptive qammod: 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
powAlloc for adaptive qammod: 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
[Progress] at 136.071 : Checks and transforms
[Progress] at 136.703 : Generate Verilog
[Warning] 2 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 137.305
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testQammodFtn
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 3785.886 ms
[Progress] Start QammodFtn_dut test simulation with seed 1797407303
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 14878.573 ms
-
[INFO ]
-
: frames starts at 6, that is,simTime 64,
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: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
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[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
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[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
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[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
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[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: test for generator QammodFtn passed
101-th frame:
input :
0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 190 more elements...
0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 190 more elements...
1 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 190 more elements...
0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 190 more elements...
56 more cycles...
0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 190 more elements...
1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 190 more elements...
0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 190 more elements...
0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 190 more elements...
yours :
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0.9482421875 + 0.31591796875i 0.31591796875 + -0.31591796875i 0.9482421875 + -0.31591796875i 0.31591796875 + 0.31591796875i -0.9482421875 + 0.9482421875i -0.9482421875 + 0.9482421875i 0.9482421875 + -0.9482421875i 0.9482421875 + 0.9482421875i 0.31591796875 + 0.9482421875i -0.9482421875 + 0.9482421875i -0.9482421875 + 0.31591796875i 0.31591796875 + 0.9482421875i -0.9482421875 + -0.9482421875i 0.31591796875 + 0.31591796875i 0.9482421875 + 0.31591796875i -0.9482421875 + 0.9482421875i 238 more elements...
0.31591796875 + 0.9482421875i -0.9482421875 + 0.31591796875i -0.9482421875 + 0.31591796875i -0.9482421875 + -0.31591796875i 0.31591796875 + -0.31591796875i 0.9482421875 + 0.9482421875i -0.9482421875 + 0.9482421875i -0.9482421875 + 0.31591796875i -0.31591796875 + -0.31591796875i 0.31591796875 + 0.31591796875i 0.31591796875 + -0.9482421875i 0.31591796875 + 0.31591796875i -0.31591796875 + 0.31591796875i -0.9482421875 + 0.31591796875i -0.31591796875 + -0.9482421875i 0.9482421875 + -0.9482421875i 238 more elements...
-0.31591796875 + 0.31591796875i -0.9482421875 + -0.31591796875i 0.9482421875 + -0.31591796875i 0.9482421875 + 0.31591796875i -0.31591796875 + -0.31591796875i -0.9482421875 + 0.31591796875i -0.9482421875 + -0.9482421875i -0.9482421875 + -0.31591796875i -0.9482421875 + -0.31591796875i -0.31591796875 + 0.9482421875i -0.9482421875 + 0.31591796875i 0.31591796875 + 0.31591796875i 0.31591796875 + 0.31591796875i -0.31591796875 + 0.9482421875i 0.31591796875 + -0.31591796875i -0.9482421875 + 0.31591796875i 238 more elements...
8 more cycles...
0.31591796875 + -0.9482421875i -0.31591796875 + -0.31591796875i -0.31591796875 + -0.9482421875i 0.31591796875 + 0.31591796875i -0.9482421875 + -0.9482421875i -0.9482421875 + 0.31591796875i -0.9482421875 + -0.9482421875i -0.31591796875 + -0.9482421875i -0.9482421875 + -0.9482421875i 0.31591796875 + 0.31591796875i 0.31591796875 + 0.31591796875i 0.9482421875 + 0.31591796875i 0.31591796875 + 0.9482421875i 0.31591796875 + -0.31591796875i 0.31591796875 + -0.9482421875i -0.9482421875 + 0.31591796875i 238 more elements...
-0.9482421875 + -0.31591796875i -0.9482421875 + -0.9482421875i -0.9482421875 + -0.31591796875i 0.9482421875 + -0.9482421875i 0.9482421875 + 0.31591796875i 0.9482421875 + -0.31591796875i 0.9482421875 + 0.31591796875i -0.9482421875 + 0.31591796875i -0.9482421875 + -0.31591796875i 0.31591796875 + 0.31591796875i 0.31591796875 + -0.9482421875i 0.31591796875 + 0.9482421875i 0.9482421875 + 0.9482421875i -0.31591796875 + 0.31591796875i -0.31591796875 + -0.9482421875i 0.31591796875 + -0.31591796875i 238 more elements...
-0.9482421875 + 0.9482421875i -0.31591796875 + 0.31591796875i 0.9482421875 + -0.31591796875i -0.9482421875 + 0.9482421875i -0.9482421875 + -0.9482421875i -0.9482421875 + 0.31591796875i 0.9482421875 + 0.9482421875i 0.31591796875 + -0.31591796875i 0.31591796875 + -0.31591796875i 0.31591796875 + -0.31591796875i -0.9482421875 + -0.31591796875i 0.31591796875 + -0.9482421875i 0.9482421875 + -0.31591796875i -0.9482421875 + -0.9482421875i 0.9482421875 + -0.9482421875i -0.31591796875 + 0.31591796875i 238 more elements...
-0.9482421875 + -0.9482421875i -0.9482421875 + -0.9482421875i -0.31591796875 + 0.9482421875i 0.31591796875 + 0.9482421875i 0.9482421875 + -0.31591796875i -0.9482421875 + -0.31591796875i 0.9482421875 + -0.31591796875i -0.9482421875 + -0.9482421875i -0.9482421875 + 0.9482421875i -0.31591796875 + -0.9482421875i -0.31591796875 + -0.9482421875i -0.9482421875 + 0.9482421875i -0.31591796875 + 0.9482421875i -0.31591796875 + 0.31591796875i 0.31591796875 + 0.31591796875i -0.31591796875 + 0.31591796875i 238 more elements...
golden:
-0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i 0.31622776601683794 + -0.9486832980505138i 0.9486832980505138 + 0.31622776601683794i -0.31622776601683794 + 0.9486832980505138i 0.9486832980505138 + 0.31622776601683794i 0.9486832980505138 + -0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i 0.9486832980505138 + -0.9486832980505138i 0.9486832980505138 + 0.31622776601683794i 0.9486832980505138 + -0.31622776601683794i 0.9486832980505138 + 0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i 0.31622776601683794 + -0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i -0.31622776601683794 + -0.9486832980505138i 238 more elements...
0.9486832980505138 + 0.31622776601683794i 0.31622776601683794 + -0.31622776601683794i 0.9486832980505138 + -0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i -0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i 0.9486832980505138 + -0.9486832980505138i 0.9486832980505138 + 0.9486832980505138i 0.31622776601683794 + 0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i 0.31622776601683794 + 0.9486832980505138i -0.9486832980505138 + -0.9486832980505138i 0.31622776601683794 + 0.31622776601683794i 0.9486832980505138 + 0.31622776601683794i -0.9486832980505138 + 0.9486832980505138i 238 more elements...
0.31622776601683794 + 0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i -0.9486832980505138 + 0.31622776601683794i -0.9486832980505138 + -0.31622776601683794i 0.31622776601683794 + -0.31622776601683794i 0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i -0.31622776601683794 + -0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i 0.31622776601683794 + -0.9486832980505138i 0.31622776601683794 + 0.31622776601683794i -0.31622776601683794 + 0.31622776601683794i -0.9486832980505138 + 0.31622776601683794i -0.31622776601683794 + -0.9486832980505138i 0.9486832980505138 + -0.9486832980505138i 238 more elements...
-0.31622776601683794 + 0.31622776601683794i -0.9486832980505138 + -0.31622776601683794i 0.9486832980505138 + -0.31622776601683794i 0.9486832980505138 + 0.31622776601683794i -0.31622776601683794 + -0.31622776601683794i -0.9486832980505138 + 0.31622776601683794i -0.9486832980505138 + -0.9486832980505138i -0.9486832980505138 + -0.31622776601683794i -0.9486832980505138 + -0.31622776601683794i -0.31622776601683794 + 0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i -0.31622776601683794 + 0.9486832980505138i 0.31622776601683794 + -0.31622776601683794i -0.9486832980505138 + 0.31622776601683794i 238 more elements...
8 more cycles...
0.31622776601683794 + -0.9486832980505138i -0.31622776601683794 + -0.31622776601683794i -0.31622776601683794 + -0.9486832980505138i 0.31622776601683794 + 0.31622776601683794i -0.9486832980505138 + -0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i -0.9486832980505138 + -0.9486832980505138i -0.31622776601683794 + -0.9486832980505138i -0.9486832980505138 + -0.9486832980505138i 0.31622776601683794 + 0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i 0.9486832980505138 + 0.31622776601683794i 0.31622776601683794 + 0.9486832980505138i 0.31622776601683794 + -0.31622776601683794i 0.31622776601683794 + -0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i 238 more elements...
-0.9486832980505138 + -0.31622776601683794i -0.9486832980505138 + -0.9486832980505138i -0.9486832980505138 + -0.31622776601683794i 0.9486832980505138 + -0.9486832980505138i 0.9486832980505138 + 0.31622776601683794i 0.9486832980505138 + -0.31622776601683794i 0.9486832980505138 + 0.31622776601683794i -0.9486832980505138 + 0.31622776601683794i -0.9486832980505138 + -0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i 0.31622776601683794 + -0.9486832980505138i 0.31622776601683794 + 0.9486832980505138i 0.9486832980505138 + 0.9486832980505138i -0.31622776601683794 + 0.31622776601683794i -0.31622776601683794 + -0.9486832980505138i 0.31622776601683794 + -0.31622776601683794i 238 more elements...
-0.9486832980505138 + 0.9486832980505138i -0.31622776601683794 + 0.31622776601683794i 0.9486832980505138 + -0.31622776601683794i -0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + -0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i 0.9486832980505138 + 0.9486832980505138i 0.31622776601683794 + -0.31622776601683794i 0.31622776601683794 + -0.31622776601683794i 0.31622776601683794 + -0.31622776601683794i -0.9486832980505138 + -0.31622776601683794i 0.31622776601683794 + -0.9486832980505138i 0.9486832980505138 + -0.31622776601683794i -0.9486832980505138 + -0.9486832980505138i 0.9486832980505138 + -0.9486832980505138i -0.31622776601683794 + 0.31622776601683794i 238 more elements...
-0.9486832980505138 + -0.9486832980505138i -0.9486832980505138 + -0.9486832980505138i -0.31622776601683794 + 0.9486832980505138i 0.31622776601683794 + 0.9486832980505138i 0.9486832980505138 + -0.31622776601683794i -0.9486832980505138 + -0.31622776601683794i 0.9486832980505138 + -0.31622776601683794i -0.9486832980505138 + -0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i -0.31622776601683794 + -0.9486832980505138i -0.31622776601683794 + -0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i -0.31622776601683794 + 0.9486832980505138i -0.31622776601683794 + 0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i -0.31622776601683794 + 0.31622776601683794i 238 more elements...
-
29.48 s
ifftftn
-
29.48 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on ifftFtn----
-
[INFO ]
-
: testing vector length: 410464, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:01:54
[Progress] at 159.332 : Elaborate components
[Progress] at 159.665 : Checks and transforms
[Progress] at 161.784 : Generate Verilog
[Warning] 213 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 162.410
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testIfftFtn
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 2521.485 ms
[Progress] Start ifftFtn_dut test simulation with seed 1163883373
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 13483.016 ms
-
[INFO ]
-
: frames starts at 77, that is,simTime 206,
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
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[INFO ]
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[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
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[INFO ]
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[INFO ]
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[INFO ]
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[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
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[INFO ]
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: frame ber: 0.0
-
[INFO ]
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: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: test for generator ifftFtn passed
101-th frame:
input :
-0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i 0.31622776601683794 + -0.9486832980505138i 0.9486832980505138 + 0.31622776601683794i -0.31622776601683794 + 0.9486832980505138i 0.9486832980505138 + 0.31622776601683794i 0.9486832980505138 + -0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i 0.9486832980505138 + -0.9486832980505138i 0.9486832980505138 + 0.31622776601683794i 0.9486832980505138 + -0.31622776601683794i 0.9486832980505138 + 0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i 0.31622776601683794 + -0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i -0.31622776601683794 + -0.9486832980505138i 238 more elements...
0.9486832980505138 + 0.31622776601683794i 0.31622776601683794 + -0.31622776601683794i 0.9486832980505138 + -0.31622776601683794i 0.31622776601683794 + 0.31622776601683794i -0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i 0.9486832980505138 + -0.9486832980505138i 0.9486832980505138 + 0.9486832980505138i 0.31622776601683794 + 0.9486832980505138i -0.9486832980505138 + 0.9486832980505138i -0.9486832980505138 + 0.31622776601683794i 0.31622776601683794 + 0.9486832980505138i -0.9486832980505138 + -0.9486832980505138i 0.31622776601683794 + 0.31622776601683794i 0.9486832980505138 + 0.31622776601683794i -0.9486832980505138 + 0.9486832980505138i 238 more elements...
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8 more cycles...
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yours :
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56 more cycles...
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golden:
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-0.329252597536777 -0.08956276767377336 -0.05671247525197093 -0.634456675380026 0.2744628669006819 0.8070028754794087 0.7766446992813751 -0.2681680829553325 -0.08760586956834104 -0.7483317676037542 -0.7946177230227487 0.0945573710593059 0.8256070998370799 0.2533780415704694 0.4162325939622271 -0.06275192777240113 0.3557562367689428 0.5076535003821442 -1.5904826845938098 -0.8221185156999659 1.1921903203599395 0.7957543983796385 1.123362885283022 1.479818850727339 0.03723663744544514 -0.06495522658780839 0.3906108496587307 1.3166328235108935 -1.1415131647128258 0.4892589788879014 0.4101285464163442 0.7572139790994935 0.9779227259271017 -0.9530506404015914 0.3931350598071149 0.6933317020897587 -0.8561901516623575 -1.384571662139175 1.3401135710960346 -0.8004338283500487 0.762697041739004 1.5123307671548674 1.3139418526451443 -0.33591314367023184 -0.5864405848892893 0.5693010309315887 -0.03291860784336764 0.9671129632447404 0.1401448558582673 -0.6171116003865882 -0.3809867780632761 -0.10977892798056393 1.5036759418980192 -1.0764023899950665 -0.6437772258487111 -0.14312362475654808 -0.8740206783622115 1.0765445658265473 0.27766629434797774 -1.0126269842116462 0.12203585550180221 0.09212727696821903 -0.25281163135640333 0.2368519268998644 68 more elements...
0.5000747305434095 -0.08793422075197188 0.13618156017734095 -0.6065670374717125 -0.5641291157765085 -2.0544721199957414 -0.5041439855397456 -0.17620343739210476 0.027800510334143547 1.243641322121065 0.7231289090472947 -0.46480564709953665 0.31622776601683794 1.6944039534041913 -0.6900888308577673 1.0963236422214535 -0.1757072801027526 -0.19259659428655368 -0.07381388616818407 -0.3903704477757015 -0.35629384185852775 -0.06204886824070527 0.4374357131842181 -0.05707229513483661 0.2560703388302581 0.2445985090209768 0.6153182060684397 -0.4885688078933321 -0.4988213216173989 -0.26648477494304695 -0.41761249231859066 -0.6483470455690994 0.2019998641175292 1.4557928505874664 0.9189814366739514 0.44977004548425104 -0.3793139419695375 0.7860929401002007 0.2715106348638672 0.37179191216589047 0.9130151532991629 -0.3422874964730809 -1.1468300153833977 -1.0129775496423084 -0.49165373142845137 0.5200639852152524 -0.1199430752174322 -0.9661367146958959 0.24951122389390445 -0.11638313841805387 0.15546643560744788 -0.2948050822208946 -0.00972258825172212 -0.7992948194005082 0.4725310443025059 0.35487943436943936 -0.20329095208950537 -0.1644221529351546 0.29158398964084686 -1.2383841373119102 0.990041338448931 0.6858806376427943 -0.05141240782098638 0.2596283123555113 68 more elements...
0.616153901772039 1.3959300914287158 -0.9838255841777201 -0.04446239478249614 -0.4024702948312819 -0.899527590545441 -1.1499325949285182 0.4747972077455733 0.9486832980505138 -0.28188567142559207 -0.1382310597124975 -0.1649781860725149 0.14417158108303596 0.3408973870813236 -0.19066989069455542 0.7733671239454406 0.540793211927981 0.8879128215858381 0.6717400634434768 -0.1536252479627369 0.4421763754970875 -1.3973763025916548 -0.5583670860074257 -0.7159979104732418 0.8790178788934193 1.0065519397098655 -0.7977934820655597 0.6463361144926378 0.2524228303953382 -0.1551293696177839 0.15039468749669532 0.13694486811742895 1.1701021255027724 0.2034605427045219 0.8059631127036009 -0.4763279970106716 -0.5405622928714735 0.7481814738828283 -0.232040123046526 1.8281668646332128 -1.3096257497360195 0.29449000162031136 0.628186745252037 -0.615233085928409 0.2168160564957622 0.7903983977202063 0.019740851993465147 0.024954490933354584 -0.3061210574697418 0.372348289762486 0.4608142746254302 1.5784896633761374 0.6825950983779567 -0.49328107304631047 0.6063027517674848 0.9067777963521333 0.0421855670959938 1.0182280775743053 0.4377071813449312 -0.27042877841055046 0.38451480670950855 -0.6366638497805234 -0.39141159727019126 0.003150152012331417 68 more elements...
56 more cycles...
-0.9009833038091799 -0.5057690183243752 -0.5562968362716327 2.0841455986962645 -0.31446290262084137 0.327736937337871 0.030876307729171826 -1.5098014000626834 -0.1834323744975015 0.1118579912390687 1.8309179497473291 0.16848407124303164 -1.279695389743949 0.2292300943870591 -0.0964874545046443 -0.46097425601418296 -0.4625966489323498 -1.2925156954575836 0.08116361990057788 -0.20572313989678176 0.7905694150420943 -0.5036805057125169 -0.031218856923840882 0.4582814042913772 -0.17400107828432118 -1.1605447025760305 -0.9333449649598574 -0.4144707150171558 0.28382911538374567 -0.6543682171256191 0.23559527910761846 -0.13267231734559318 -1.0096242502788166 -0.3004673038049869 -0.5523122108622192 -0.4454280356218742 0.07511596003692167 1.1645477749706292 0.9906551263095403 -0.06889587174007397 -0.6351485448719727 0.5885552627455928 0.7277386492357154 0.5146957679767326 0.18836202008865083 1.4504102196249253 -0.1839040044808868 -0.5352399595154373 -0.30769880767493873 0.9637047829242784 0.323733460203382 -0.3799070934602118 0.1520240284963308 -1.1944158131969227 0.013857165890635348 -0.49942656175278877 -0.0974752117745864 -0.7397039331065003 0.0539171890107365 -0.3326591661051913 -1.1771857460922008 1.0983184913003825 -0.8072178506639209 0.6482977393094156 68 more elements...
1.422199961079523 -0.09423394573667565 0.15884569618124422 -0.6443059273856256 0.016869989305543787 0.08344805356642215 0.21924062973172778 -0.3393336115555994 0.057560912688587526 0.04838958457478229 0.15228906372239015 -0.8773286170770715 -0.15810556092415637 -0.5576602982095102 0.07204869165498667 -0.6496842858780376 -0.5138701197773616 -0.0035547360732414157 -0.6020416722097576 -0.6467423182979237 0.27230333266650386 -0.48316420692485257 -0.266796760735728 0.64747970051287 0.3753833991586678 -0.050643840966103 1.303245634530703 0.643915643502339 0.8961148357645141 0.35560290885871326 0.11759624743837055 0.49908786428479696 0.1818469235736877 -1.405021631201501 -1.18847160469458 -0.47977381754974036 -1.1116343561159583 1.1658456952741048 0.25349763030663897 -0.7049763347995962 -0.610435107149151 -0.28342234630671737 -0.05410819439604589 -1.4125969885026435 -0.16967264022976702 -0.2420104425206332 -0.4934841489049451 -0.6313889997595556 -0.2840820855615926 -0.8302050245183595 -0.0729083941390817 -0.044579124892034694 -0.066436697092714 0.17142261163678302 0.23492977220405364 -0.6094497400909694 0.4560160179458239 0.0014458952726557478 -1.2122294482740614 0.5656052781521475 -0.8647314015743788 -0.385184492111967 -0.6621465505170281 -0.22449974255656197 68 more elements...
-0.19487403444517967 -0.3116446665938116 0.8690178661695867 -0.2446064516594071 -0.14986221485637025 0.750943604233168 0.6202257068683648 -1.089656784518537 0.20543388591395348 1.4282792596420868 0.43343484278833444 0.1738221844407455 1.5416103593320847 -0.27800403164048976 -0.309166972242816 0.20338122948483484 -0.11326845490810869 -0.01824461945913658 0.43913690304873965 -0.34521386924592123 -0.49899850184206584 0.9511373316013041 -1.327273795999965 -0.6190842637319384 0.09489063181496044 0.38409709852259577 -0.37591446997540706 -0.5326443705047639 1.4227729673187404 1.2527353147012137 -0.625123067681097 -1.1707661646354688 0.1327900093687203 0.23770576544947253 0.10667064872461879 -0.846277396939781 -0.21532318807655854 -0.6912563687140468 -0.7406471786339479 -0.06920144223388192 0.40917293394131904 -1.3181845645185368 0.658697680928591 0.6237625170601884 -0.5038074538066895 -0.1895190612521969 0.16798225331273597 -0.31359136932308396 0.38616019081625597 -0.07631369168419222 -0.5203339249739828 -0.08996946900802016 -1.2593885863332583 0.9245692335770054 1.0345051610055516 -0.8513136694283882 -0.28555445852921096 -0.17800609829087388 0.5707967539898815 0.12045019486152714 0.1963362293399828 -0.07703802608802751 0.7443211261875079 -0.2823046131352932 68 more elements...
-0.7849754766676131 -0.3436866369463578 -0.4787447068635614 0.373467023427703 0.20699338497185898 0.47353991075189283 1.425667034567499 -0.463280968239934 1.1067971810589328 0.6294706075388901 0.6182648785974137 -0.1895894479985048 0.28924650560678067 0.08922977373830204 -0.48267561646204493 0.1405948775112994 0.15789029786746356 0.4574899491683595 0.193045172561373 0.35997488751604734 0.5673693967877338 0.2506631813943171 -0.7983650532523059 1.0111752172019348 0.9132519728752264 0.46123684061964976 -0.049079182499825236 -0.7152817792976512 0.5358378116568623 -1.1268538567454631 -0.2788144617860173 0.9042507074234452 -0.12237799880188836 0.10941333745182738 -0.06726777718543603 -0.9840171020181239 -0.4324506535323469 -0.18024261950524484 0.6962828815186828 -1.0938234560522588 0.7149224523761606 -0.28302559482842754 0.9168716394107407 -0.33136493080863627 0.3438297427080602 -0.01633400904351992 0.3862381515334449 -0.26762622273011005 -0.8276189760116079 0.6384519681960211 -1.5868627652313443 -0.34752150812141114 1.0606508163092134 0.10965463717146728 -0.7943678786883472 0.3291854659041597 0.40422504044952967 0.5410753425586162 1.2902632626740334 0.1322044613731519 0.09517503991379625 0.21244318429079057 0.48446286012728457 -0.9343647985389707 68 more elements...
-
2.93 s
rvFftPre
-
2.93 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on rvFftPre----
-
[INFO ]
-
: testing vector length: 4224, containing 4 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:02:24
[Progress] at 188.626 : Elaborate components
[Progress] at 188.686 : Checks and transforms
[Progress] at 188.761 : Generate Verilog
[Warning] 10 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 188.809
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testRvFftPre
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 2608.022 ms
[Progress] Start rvFftPre_dut test simulation with seed 1636058353
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 32 cycles, 4 frames in total
[Done] Simulation done in 80.953 ms
-
[INFO ]
-
: frames starts at 9, that is,simTime 70,
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: test for generator rvFftPre passed
4-th frame:
input :
0.5537043539978121 0.8850886134694483 0.26355046670260296 0.9870626261778755 0.34814969842239685 0.35903202133862244 0.48412908099871266 0.5323603036271298 124 more elements...
0.6225963412350932 0.6421956348885589 0.886700607923358 0.589604979071421 0.012924085523587592 0.850991377166384 0.01577926303700672 0.8402596047947964 124 more elements...
0.25440102248260954 0.3240097078184754 0.6594532911983386 0.9966242340526597 0.5960251703755096 0.08952974401766245 0.8963863837116657 0.9370434693200461 124 more elements...
0.10049779160334926 0.8107222236867289 0.8098306259845574 0.371306247250755 0.6845083690418472 0.32623607688604295 0.5952655109947591 0.04548175970849078 124 more elements...
0.7600484032877516 0.05478943487292298 0.5560690073390525 0.24919860896237755 0.582431392604601 0.7938290496876933 0.13436615655327655 0.5476137437812684 124 more elements...
0.3177763229387849 0.20074726220482975 0.8505167898453989 0.9627801263574155 0.22611811493113343 0.8216889874428452 0.4181044165207146 0.9251302729378552 124 more elements...
0.9036703938267754 0.13253635136612907 0.4383787939831024 0.133265327105334 0.2806785838553181 0.9994138068536834 0.5476283531369478 0.21416538666620477 124 more elements...
0.48570226855327125 0.003421574895921431 0.5307769278127814 0.31451337405428026 0.5946959154272223 0.8546162697025829 0.5879309282412104 0.29862394361398736 124 more elements...
yours :
0.47509765625 + 0.849609375i 0.59326171875 + 0.02490234375i 0.57373046875 + 0.62060546875i 0.5732421875 + 0.79638671875i 0.83740234375 + 0.18408203125i 0.96044921875 + 0.4775390625i 0.93212890625 + 0.79296875i 0.48291015625 + 0.29248046875i 56 more elements...
0.3076171875 + 0.72509765625i 0.06103515625 + 0.064453125i 0.80224609375 + 0.33740234375i 0.96923828125 + 0.115234375i 0.36572265625 + 0.12109375i 0.37060546875 + 0.5576171875i 0.626953125 + 0.857421875i 0.86328125 + 0.36865234375i 56 more elements...
0.08837890625 + 0.7060546875i 0.673828125 + 0.64599609375i 0.36865234375 + 0.86376953125i 0.6552734375 + 0.14404296875i 0.42578125 + 0.841796875i 0.21826171875 + 0.8037109375i 0.63916015625 + 0.24462890625i 0.03173828125 + 0.90966796875i 56 more elements...
0.0458984375 + 0.4375i 0.7001953125 + 0.2958984375i 0.67138671875 + 0.17431640625i 0.23046875 + 0.60595703125i 0.90625 + 0.7060546875i 0.5712890625 + 0.78955078125i 0.85498046875 + 0.763671875i 0.8515625 + 0.501953125i 56 more elements...
0.884765625 + 0.32763671875i 0.96142578125 + 0.4453125i 0.755859375 + 0.802734375i 0.0869140625 + 0.9921875i 0.9638671875 + 0.8828125i 0.103515625 + 0.298828125i 0.7548828125 + 0.97900390625i 0.43994140625 + 0.21142578125i 56 more elements...
0.94287109375 + 0.70947265625i 0.234375 + 0.8330078125i 0.96826171875 + 0.4970703125i 0.3115234375 + 0.46484375i 0.177734375 + 0.50146484375i 0.5048828125 + 0.73046875i 0.0673828125 + 0.86865234375i 0.07275390625 + 0.490234375i 56 more elements...
0.34716796875 + 0.99072265625i 0.66064453125 + 0.9140625i 0.611328125 + 0.87939453125i 0.59423828125 + 0.767578125i 0.70751953125 + 0.81201171875i 0.88427734375 + 0.50537109375i 0.42529296875 + 0.47900390625i 0.09228515625 + 0.08349609375i 56 more elements...
0.16943359375 + 0.81591796875i 0.1513671875 + 0.26318359375i 0.60400390625 + 0.0986328125i 0.134765625 + 0.12841796875i 0.44921875 + 0.33935546875i 0.17724609375 + 0.4716796875i 0.0244140625 + 0.5830078125i 0.81201171875 + 0.9345703125i 56 more elements...
golden:
0.47507246894710464 + 0.8493886202318678i 0.5932944471067996 + 0.024840152986387642i 0.5736050334221166 + 0.6205885785503121i 0.5732968364286114 + 0.7964799584565521i 0.8374140777055049 + 0.1839050586175539i 0.9605411562061915 + 0.4776680123035243i 0.9319716410601885 + 0.7930477620161147i 0.48290912406726316 + 0.29240471655995726i 56 more elements...
0.30782045809408365 + 0.7249663963480912i 0.061196847634366947 + 0.06463512756783785i 0.8022254417225543 + 0.3373223547608202i 0.9693894183632685 + 0.11515155043021574i 0.36555817455358586 + 0.12131022965916494i 0.3706376824957971 + 0.5576791762100499i 0.6269395388555596 + 0.857283782791704i 0.8632217664055426 + 0.36881256080090485i 56 more elements...
0.08845802809497216 + 0.7062045050387231i 0.673785239123793 + 0.645751998368925i 0.36849721058585105 + 0.8639337865795048i 0.6550374393066071 + 0.14394647572287422i 0.42566632226725876 + 0.8416328191668633i 0.21842957706657717 + 0.80355409972718i 0.6389261997707057 + 0.24481960457546814i 0.0316195107987548 + 0.9097985578865195i 56 more elements...
0.04569780103960219 + 0.437297207930488i 0.7003463498521172 + 0.29585460470359604i 0.6716137198698856 + 0.17452162097604118i 0.2306681777322459 + 0.6061710487429761i 0.9064129548476287 + 0.7061576873773872i 0.5711352272883113 + 0.7894234351323627i 0.8550286127182456 + 0.7638490266691706i 0.8516102156768706 + 0.5018472906277142i 56 more elements...
0.8846318702021785 + 0.3278805963898671i 0.9612533791349953 + 0.44525568719163555i 0.7560930722462486 + 0.8025719116692629i 0.08705314467706116 + 0.9920383230979002i 0.9638674418561337 + 0.8826272307870606i 0.10370014896195778 + 0.29870736732441594i 0.7549340883765816 + 0.9792186981964509i 0.4399366336166325 + 0.21124065693616967i 56 more elements...
0.942981711099973 + 0.709282741000372i 0.23421592701184424 + 0.8331669366531017i 0.9680281309188059 + 0.49720787803179245i 0.3115580804815563 + 0.4649180287296816i 0.1777442080894952 + 0.5014912932104884i 0.5050468713013164 + 0.730365707421445i 0.06717034161194713 + 0.8686780664144215i 0.0728263186749587 + 0.49030795597167365i 56 more elements...
0.347348181958986 + 0.9907735728189163i 0.6605300133379554 + 0.9139489386946328i 0.611336393429491 + 0.8794399130062823i 0.5943929664313953 + 0.7675867027658335i 0.7076526595395732 + 0.8121573152578281i 0.8843249113216574 + 0.5051477032367i 0.42535535038303696 + 0.4791294442345544i 0.09224175723976458 + 0.0836758103766847i 56 more elements...
0.1694615092784464 + 0.8158148987426376i 0.15132808197544567 + 0.26336123750504337i 0.6040100889815129 + 0.09841565062630231i 0.13486203639893368 + 0.12847761175391237i 0.44934730306831805 + 0.3392402155911628i 0.17716095684460686 + 0.4718422520857827i 0.02444743816305439 + 0.5828779585342785i 0.8121302455610443 + 0.9345182226213486i 56 more elements...
-
3.11 s
rvFftPost
-
3.11 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on rvFftPost----
-
[INFO ]
-
: testing vector length: 4096, containing 8 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:02:27
[Progress] at 191.557 : Elaborate components
[Progress] at 191.649 : Checks and transforms
[Progress] at 191.867 : Generate Verilog
[Warning] 1 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 191.964
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testRvFftPost
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 2461.156 ms
[Progress] Start rvFftPost_dut test simulation with seed 296907099
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 64 cycles, 8 frames in total
[Done] Simulation done in 137.147 ms
-
[INFO ]
-
: frames starts at 9, that is,simTime 70,
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: frame ber: 0.0
-
[INFO ]
-
: test for generator rvFftPost passed
8-th frame:
input :
0.7955490846114993 + 0.946046359897543i 0.8466689796334931 + 0.535849470025157i 0.30413251628091764 + 0.6503381039410638i 0.48768103546538544 + 0.22123701568258125i 0.1828500935307037 + 0.3144009893031351i 0.5681728482627203 + 0.8442065786700639i 0.3326283251923243 + 0.2583148557093412i 0.5510918116546821 + 0.7674623146693565i 56 more elements...
0.23757945607703745 + 0.1895001012494436i 0.3347902786651561 + 0.8833370192044788i 0.11744884729405103 + 0.9567610137720328i 0.14936076518981445 + 0.5774380085503908i 0.49136229605752824 + 0.16735577127435042i 0.783626541056667 + 0.46599066242802256i 0.8482467296388831 + 0.10005431157608047i 0.04709040254807195 + 0.41929220983546545i 56 more elements...
0.798330750333316 + 0.3535119918143935i 0.686518275275772 + 0.24067659675075515i 0.4813974747955807 + 0.6650673520328702i 0.34406779162172907 + 0.38696928652569607i 0.15756026635065667 + 0.6572090440422474i 0.7847543735482915 + 0.2824167403623231i 0.25472916826362335 + 0.9362020418657149i 0.029779011112334608 + 0.9105305686201695i 56 more elements...
0.8294083767916126 + 0.46651392277893544i 0.6728461555488565 + 0.30483345052186095i 0.808283294938453 + 0.5677576081038352i 0.08562373260989187 + 0.484399843942915i 0.30776868061072793 + 0.43916274122296683i 0.6846516311484581 + 0.6924153660313096i 0.7019903538336584 + 0.2895441629046738i 0.7242218861875971 + 0.037477350546395005i 56 more elements...
0.6716755771683611 + 0.9290080688567489i 0.6321500126117181 + 0.8479680916465423i 0.9059189658659164 + 0.48565263731437214i 0.861483005479101 + 0.9357439984776431i 0.8700699812196347 + 0.8529890659899475i 0.9762964252867603 + 0.4826124168001642i 0.5479528737964358 + 0.023687142998732535i 0.641616158977731 + 0.14037780960724522i 56 more elements...
0.6552533658805078 + 0.5135669776956172i 0.4701886827226859 + 0.7174363839313832i 0.9776250418219725 + 0.2678934970303365i 0.6327328270301907 + 0.03846131664084629i 0.574304466147491 + 0.9230305655797326i 0.5325496487080371 + 0.8273290640385849i 0.35854705616928606 + 0.34305774282836776i 0.5792916940387417 + 0.1034224793648395i 56 more elements...
0.09952064925479975 + 0.3648334655692993i 0.6601038346780759 + 0.8357894693549993i 0.6222297794362802 + 0.791941670171413i 0.8340932433423535 + 0.32145671808698983i 0.9520702144468252 + 0.35820008658848557i 0.6061550350770183 + 0.28858178802194645i 0.9077111036498733 + 0.7929030303499186i 0.6207112084880565 + 0.35474726235727994i 56 more elements...
0.3131140318126904 + 0.9995206769821744i 0.2424199698121915 + 0.2007738127715223i 0.8340693463404129 + 0.9635788714960208i 0.3739171148719789 + 0.5450804458117159i 0.33672314585722607 + 0.5519807898731518i 0.8297390844725178 + 0.8160823779313009i 0.1773910042092285 + 0.2592904254990699i 0.13547024220220327 + 0.8664333108893622i 56 more elements...
yours :
0.54541015625 + -0.203125i 0.48974609375 + -0.21142578125i 0.53466796875 + -0.2080078125i 1.16845703125 + 0.01416015625i 0.7314453125 + -0.3046875i 1.3701171875 + 0.58740234375i 0.697265625 + 0.2236328125i 57 more elements...
0.810546875 + 0.0029296875i 1.11279296875 + 0.08740234375i 1.04931640625 + 0.08251953125i 1.38916015625 + -0.29638671875i 1.6962890625 + -0.751953125i 0.71240234375 + -0.1982421875i 1.87255859375 + -0.021484375i 57 more elements...
0.53369140625 + -0.17236328125i 0.63671875 + 0.326171875i 0.65283203125 + 0.09423828125i 0.87939453125 + -0.693359375i 1.251953125 + 0.55712890625i 0.1083984375 + 0.33740234375i 1.1630859375 + 0.28125i 57 more elements...
0.92431640625 + 0.099609375i 1.07080078125 + 0.22998046875i 1.02099609375 + -0.04833984375i 0.890625 + 0.03662109375i 1.16943359375 + -0.572265625i 0.8310546875 + -0.46923828125i 1.37060546875 + 0.0029296875i 57 more elements...
0.8369140625 + 0.16943359375i 1.67431640625 + 0.03173828125i 0.8212890625 + 0.06640625i 0.94775390625 + 0.267578125i 0.7333984375 + 0.1416015625i 0.5693359375 + 0.21484375i 0.47607421875 + 0.09423828125i 57 more elements...
0.25244140625 + 0.06689453125i 1.22802734375 + -0.17822265625i 0.9521484375 + 0.0i 1.037109375 + 0.61865234375i 1.59375 + 0.10107421875i 1.1337890625 + -0.03271484375i 0.76611328125 + -0.787109375i 57 more elements...
1.22021484375 + 0.33740234375i 1.2578125 + -0.68994140625i 1.31494140625 + 0.7421875i 1.48388671875 + 0.048828125i 0.8671875 + -0.0859375i 0.57373046875 + -0.23095703125i 0.98974609375 + 0.587890625i 57 more elements...
0.92626953125 + 0.40576171875i 1.34814453125 + -0.478515625i 1.1513671875 + -0.23486328125i 0.54443359375 + -0.6171875i 0.287109375 + 0.10400390625i 0.6611328125 + -0.001953125i 1.62353515625 + -0.20166015625i 53 more elements...
golden:
0.5455529736574202 + -0.20303198008800505i 0.48984716971156406 + -0.21158662324458744i 0.5349124411850825 + -0.20797019026825592i 1.1680429643006747 + 0.01400671853758384i 0.7316927045794237 + -0.30461922370082184i 1.3697288196463893 + 0.5873076262998279i 0.6975394211401489 + 0.22383820330736437i 57 more elements...
0.8105449835478717 + 0.0030765832500013746i 1.112941261949873 + 0.08708517178143194i 1.04952010997367 + 0.08245603426071446i 1.3890606784052897 + -0.2963184944999988i 1.6962749810486142 + -0.752069653323467i 0.7127630849361739 + -0.19828085003792928i 1.87246746671817 + -0.02184910211426261i 57 more elements...
0.5337458762298566 + -0.17227570833629036i 0.6367512541542112 + 0.3259586791905743i 0.6524931421162244 + 0.09433367414199223i 0.8794657180305571 + -0.6931455220617272i 1.2519167683100485 + 0.5570945278788587i 0.10863005128208947 + 0.3372820107198099i 1.16310083711104 + 0.2810163069871975i 57 more elements...
0.9244451843247439 + 0.09925928899292402i 1.071012242782949 + 0.2301105751132243i 1.0211997355102675 + -0.04809067806509204i 0.890509274945392 + 0.03688356530062065i 1.169064841993079 + -0.5722159998160447i 0.8313469931907408 + -0.4695989957389858i 1.370464918276232 + 0.002774837606955849i 57 more elements...
0.8367721688745261 + 0.16921225412367513i 1.674406438802544 + 0.03169726777523396i 0.8212489351195043 + 0.06643605419477505i 0.9476170030388852 + 0.2675451963370249i 0.7331500206369962 + 0.14162013180015554i 0.5695153763094507 + 0.21509235177102826i 0.47592149463134614 + 0.09433841176967361i 57 more elements...
0.2522555082879864 + 0.0667955178586136i 1.228299819356044 + -0.17819240370804423i 0.9521782764756279 + -2.184782291519971E-4i 1.0368652697088603 + 0.61858227984003i 1.5936363887605642 + 0.10123911129388219i 1.1336520639739454 + -0.032752769805036164i 0.7658438182695871 + -0.7870563342552906i 57 more elements...
1.2200844139425027 + 0.3373726094149111i 1.2579790027863735 + -0.6900430290660259i 1.3153095558525711 + 0.7424584317828019i 1.483779126520529 + 0.04907202905742025i 0.8673959534471981 + -0.08550159202249497i 0.5735589467022203 + -0.23120009875978786i 0.9901927746378775 + 0.5876523662762564i 57 more elements...
0.9264161605110257 + 0.4056623742888118i 1.3479471667619984 + -0.4787939873515241i 1.151304325625392 + -0.23491586567423783i 0.5445536968317758 + -0.6170967791844534i 0.2870947040302252 + 0.10377314185269326i 0.6608729589654654 + -0.0016733513983715476i 1.6236387788519415 + -0.2015431675070355i 53 more elements...
-
23.06 s
rvFftFtn
-
23.06 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on RvFftFtn----
-
[INFO ]
-
: testing vector length: 959904, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:02:34
[Progress] at 199.231 : Elaborate components
[Progress] at 199.451 : Checks and transforms
[Progress] at 200.992 : Generate Verilog
[Warning] 249 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 201.369
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testRvFftFtn
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 2923.468 ms
[Progress] Start RvFftFtn_dut test simulation with seed 908513421
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 10335.764 ms
-
[INFO ]
-
: frames starts at 77, that is,simTime 206,
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[INFO ]
-
: test for generator RvFftFtn passed
101-th frame:
input :
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64 more cycles...
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golden:
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64 more cycles...
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1 m 7 s
qamdemodFtn
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1 m 7 s
passedshould work
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[INFO ]
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:
----starting ChainsawTest on QamdemodFtn----
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[INFO ]
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: testing vector length: 410464, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:02:57
[Progress] at 221.431 : Elaborate components
[Progress] at 221.610 : Checks and transforms
[Progress] at 222.003 : Generate Verilog
[Warning] 4 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 222.228
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testQamdemodFtn
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 2584.337 ms
[Progress] Start QamdemodFtn_dut test simulation with seed 1917232278
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[INFO ]
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:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 6069.197 ms
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: test for generator QamdemodFtn passed
101-th frame:
input :
-5.19383828662222 + 4.163506922466825i -3.9686624118571086 + 3.3653144131834103i 1.412013316433868 + -3.046665088597567i 2.9250999642583464 + 1.0329046212190676i -0.7610687666530616 + 2.3266284980431577i 2.0904928790195823 + 0.6081242053369997i 1.8340442608956573 + -1.8106217479176483i -1.4745738799609955 + 0.513400823303127i 1.4508052632696464 + -1.5300200784258333i 1.438195687166309 + 0.3726105011796472i 1.2548250120947761 + -0.4672570152332346i 1.2177826411989303 + 0.24688276551533678i 0.3731040256080473 + 0.340107903583611i 0.38643545427963516 + -0.38258991964035677i 0.3710743708004514 + 0.3093729634908488i -0.35285085586214726 + -0.994831857568737i 238 more elements...
4.471072400096279 + 2.180782610800975i 1.3067617062627643 + -0.9912421458862365i 3.0885800992838113 + -0.5922633485114908i 0.7928141421402048 + 0.7209509441165116i -2.4718339061064905 + 2.2082591385740993i -2.084398595873417 + 2.0472537076021102i 1.6587251698628827 + -1.700835533548465i 1.5377465939602812 + 1.6041599174321972i 0.506936369624217 + 1.4301782721110008i -1.25587376801593 + 1.329081404923425i -1.2643370537139171 + 0.4253741358377535i 0.4409088925921914 + 1.1174613761597143i -1.102016766651111 + -1.0208683497855646i 0.36282406997070576 + 0.32015433534933574i 0.9810707778855413 + 0.24483428611759359i -0.8431293811976269 + 1.0043673869138179i 238 more elements...
1.4623836859220591 + 5.335126803004162i -3.4451883492158606 + 0.9501865586318934i -2.798866388818885 + 0.8428415719410391i -2.4575833770414115 + -0.9119420043468447i 1.0094760776490566 + -0.5190244205362923i 2.18153716057239 + 2.0267356880457386i -1.468739768025835 + 1.989198464780001i -1.3971638634490617 + 0.7075727982427881i -0.3211486845739609 + -0.38935426140874035i 0.5763959943421768 + 0.4634425268587777i 0.4962450532853421 + -1.1163749072058629i 0.514624079634098 + 0.5025566234455275i -0.21487201244104862 + 0.45093615783994806i -0.8949299614289671 + 0.4383109510575554i -0.29952203378400394 + -0.8569750308721727i 0.9542202769851511 + -0.9183593584267313i 238 more elements...
-1.6449021542471098 + 1.2623344854384273i -3.299155752124009 + -1.496226442721286i 3.286614637440001 + -0.8118544957472097i 2.7133544471816102 + 0.9909075233981992i -0.6559459470091006 + -0.8197711960442093i -1.874481455656205 + 0.7834423958445429i -1.7668355980135877 + -1.682274655937935i -1.6020948670469093 + -0.5441915610105137i -1.5069631825052856 + -0.36307628652058477i -0.37130709105918447 + 1.3932428200147173i -1.207944498451205 + 0.4772149093873582i 0.4119289068342179 + 0.381967546609097i 0.3691582253855547 + 0.3921853077267411i -0.3045200976607849 + 1.0949457612139977i 0.3507102524347455 + -0.28835469420832177i -0.921565529010413 + 0.43437428509865184i 238 more elements...
8 more cycles...
3.7168786070004924 + -4.533430988861963i -0.10001586760124742 + -1.2260448405151188i -0.29645600008949363 + -3.0371626803332115i 1.5688542993744794 + 1.1141428609002622i -1.805197619889131 + -2.396034954643448i -1.5715335305875144 + 0.7955309620298152i -1.3192963093360255 + -1.6401296784459918i -0.1118396182062647 + -1.4112907047466265i -1.10812383829783 + -1.2522477540427701i 0.7104921278424151 + 0.5799298941528712i 0.7571691227033024 + 0.4875599621554123i 1.4332877609354928 + 0.44576549340306254i 0.6307127056011324 + 1.1635609342776723i 0.5452736940409069 + -0.21187570347516005i 0.4583895403939898 + -0.8096125260600028i -0.7471521615007912 + 0.5291440475128342i 238 more elements...
-4.0903914457085735 + -2.2265838070936543i -3.1263219789428556 + -3.9907870513699075i -2.906845427039408 + -1.4469931515084347i 2.7104699783148343 + -2.4846094319415553i 2.250766558066484 + 0.8637621270169764i 2.0070517564788273 + -0.5873591409403375i 1.7829911428379372 + 0.6609880332052611i -1.4859069036110875 + 0.6127113497049083i -1.262056637192401 + -0.4876903066452639i 0.4476352057276962 + 0.3104708851914255i 0.35966335957428613 + -1.2735220110983603i 0.4635171365072408 + 1.1800222654970456i 1.0685644226730746 + 0.9655560495025501i -0.29248492958272315 + 0.3830392179984285i -0.3586904929756626 + -0.9718901994026602i 0.3525219969271127 + -0.326927709918284i 238 more elements...
-5.231020850773762 + 4.009665031148942i -1.2251614104799478 + 1.019076995895817i 3.395457577331655 + -0.973379997787262i -2.5512211864587586 + 2.5191423706282636i -2.098586637387175 + -2.32393095479282i -1.984834236700623 + 0.6760543592239422i 1.7616021561088815 + 1.8562422589162393i 0.56912603730013 + -0.4678397668240497i 0.45747337156940376 + -0.430790965062791i 0.5769282688974996 + -0.41898604766553255i -1.1731601053893106 + -0.34802651670758056i 0.3582590628822485 + -1.1037280972892962i 1.0076820790433316 + -0.3473488837797516i -1.0411995631133442 + -0.9304902878610612i 0.9383996640753789 + -0.9469090393962649i -0.27206776598308957 + 0.3206631999750107i 238 more elements...
-3.944260913411732 + -5.5672312509535i -3.3096831945178855 + -3.9684285387491305i -1.1655924070648123 + 3.0344595641780416i 0.8285159892936587 + 2.7246823243045792i 2.2335927725712708 + -0.7814961872727071i -1.980616347545482 + -0.6507457537933371i 1.7614241900198584 + -0.5302927163219394i -1.6058798351590036 + -1.4548034812915671i -1.2808824214723207 + 1.5445849175143438i -0.48802671430053884 + -1.2396206365057818i -0.4323026974111294 + -1.2683798481515378i -1.1405755770871473 + 1.2114260349758161i -0.3240474978199356 + 1.1073640970912992i -0.2929219938262633 + 0.39893914740354136i 0.2869545122848488 + 0.30444363197213103i -0.25704225011430115 + 0.3230946740214822i 238 more elements...
yours :
0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 190 more elements...
0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 190 more elements...
1 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 190 more elements...
0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 190 more elements...
56 more cycles...
0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 190 more elements...
1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 190 more elements...
0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 190 more elements...
0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 190 more elements...
golden:
0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 190 more elements...
0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 190 more elements...
1 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 190 more elements...
0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 190 more elements...
56 more cycles...
0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 190 more elements...
1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 190 more elements...
0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 190 more elements...
0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 190 more elements...
-
59.75 s
deIntrlvFtn
-
59.75 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on deintrlvFtn----
-
[INFO ]
-
: testing vector length: 1641856, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:04:00
[Progress] at 284.628 : Elaborate components
[Progress] at 284.694 : Checks and transforms
[Progress] at 284.737 : Generate Verilog
[Warning] 1 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 284.790
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testDeIntrlvFtn
[Progress] Verilator compilation started
[info] Found cached verilator binaries
[Progress] Verilator compilation done in 2589.243 ms
[Progress] Start deintrlvFtn_dut test simulation with seed 23573018
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 3463.793 ms
-
[INFO ]
-
: frames starts at 2, that is,simTime 56,
-
[INFO ]
-
: test for generator deintrlvFtn passed
101-th frame:
input :
0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 190 more elements...
0 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 190 more elements...
1 1 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 190 more elements...
0 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 190 more elements...
56 more cycles...
0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 190 more elements...
1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 190 more elements...
0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 1 0 190 more elements...
0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 190 more elements...
yours :
0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 190 more elements...
1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 190 more elements...
1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 190 more elements...
1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 190 more elements...
56 more cycles...
0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 190 more elements...
1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 190 more elements...
1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 190 more elements...
1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 190 more elements...
golden:
0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 190 more elements...
1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 190 more elements...
1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 190 more elements...
1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 190 more elements...
56 more cycles...
0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 190 more elements...
1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 190 more elements...
1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 190 more elements...
1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 190 more elements...
-
3 m 3 s
viterbiFtn
-
3 m 3 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on viterbiFtn----
-
[INFO ]
-
: testing vector length: 1641856, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:04:59
[Progress] at 344.340 : Elaborate components
[Progress] at 345.467 : Checks and transforms
[Progress] at 351.869 : Generate Verilog
[Warning] toplevel/core/cores_0/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_1/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_2/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_3/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_4/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_5/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_6/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_7/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_8/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_9/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_10/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_11/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_12/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_13/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_14/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_15/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_16/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_17/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_18/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_19/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_20/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_21/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_22/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_23/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_24/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_25/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_26/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_27/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_28/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_29/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_30/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_31/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_32/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_33/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_34/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_35/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_36/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_37/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_38/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_39/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_40/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_41/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_42/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_43/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_44/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_45/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_46/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_47/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_48/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_49/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_50/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_51/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_52/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_53/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_54/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_55/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_56/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_57/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_58/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_59/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_60/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_61/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_62/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_63/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_64/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_65/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_66/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_67/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_68/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_69/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_70/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_71/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_72/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_73/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_74/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_75/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_76/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_77/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_78/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_79/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_80/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_81/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_82/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_83/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_84/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_85/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_86/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_87/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_88/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_89/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_90/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_91/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_92/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_93/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_94/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_95/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_96/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_97/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_98/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_99/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_100/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_101/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_102/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_103/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_104/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_105/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_106/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_107/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_108/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_109/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_110/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_111/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_112/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_113/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_114/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_115/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_116/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_117/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_118/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_119/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_120/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_121/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_122/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_123/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_124/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_125/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/cores_126/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] 65659 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 355.111
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testViterbiFtn
[Progress] Verilator compilation started
[Progress] Verilator compilation done in 145105.095 ms
[Progress] Start viterbiFtn_dut test simulation with seed 568317821
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 16419.332 ms
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: test for generator viterbiFtn passed
101-th frame:
input :
0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 190 more elements...
1 0 0 1 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 190 more elements...
1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 190 more elements...
1 0 1 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 190 more elements...
56 more cycles...
0 0 1 1 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 1 190 more elements...
1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 0 190 more elements...
1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 0 0 1 1 190 more elements...
1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 190 more elements...
yours :
0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 63 more elements...
1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 63 more elements...
0 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 63 more elements...
0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1 63 more elements...
56 more cycles...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
golden:
0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 63 more elements...
1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 63 more elements...
0 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 63 more elements...
0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1 63 more elements...
56 more cycles...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
-
45.25 s
tx
-
45.25 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on convFtn_intrlvFtn_QammodFtn_ifftFtn----
-
[INFO ]
-
: testing vector length: 820928, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:08:02
[Progress] at 527.226 : Elaborate components
-
[INFO ]
-
:
----qammod with bit & power alloc----
bitAlloc for adaptive qammod: 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
powAlloc for adaptive qammod: 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
[Progress] at 527.558 : Checks and transforms
[Progress] at 529.919 : Generate Verilog
[Warning] 311 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 530.921
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testTx
[Progress] Verilator compilation started
[Progress] Verilator compilation done in 20198.742 ms
[Progress] Start convFtn_intrlvFtn_QammodFtn_ifftFtn_dut test simulation with seed 55986051
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[INFO ]
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:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 10238.481 ms
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: test for generator convFtn_intrlvFtn_QammodFtn_ifftFtn passed
101-th frame:
input :
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56 more cycles...
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golden:
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-0.329252597536777 -0.08956276767377336 -0.05671247525197093 -0.634456675380026 0.2744628669006819 0.8070028754794087 0.7766446992813751 -0.2681680829553325 -0.08760586956834104 -0.7483317676037542 -0.7946177230227487 0.0945573710593059 0.8256070998370799 0.2533780415704694 0.4162325939622271 -0.06275192777240113 0.3557562367689428 0.5076535003821442 -1.5904826845938098 -0.8221185156999659 1.1921903203599395 0.7957543983796385 1.123362885283022 1.479818850727339 0.03723663744544514 -0.06495522658780839 0.3906108496587307 1.3166328235108935 -1.1415131647128258 0.4892589788879014 0.4101285464163442 0.7572139790994935 0.9779227259271017 -0.9530506404015914 0.3931350598071149 0.6933317020897587 -0.8561901516623575 -1.384571662139175 1.3401135710960346 -0.8004338283500487 0.762697041739004 1.5123307671548674 1.3139418526451443 -0.33591314367023184 -0.5864405848892893 0.5693010309315887 -0.03291860784336764 0.9671129632447404 0.1401448558582673 -0.6171116003865882 -0.3809867780632761 -0.10977892798056393 1.5036759418980192 -1.0764023899950665 -0.6437772258487111 -0.14312362475654808 -0.8740206783622115 1.0765445658265473 0.27766629434797774 -1.0126269842116462 0.12203585550180221 0.09212727696821903 -0.25281163135640333 0.2368519268998644 68 more elements...
0.5000747305434095 -0.08793422075197188 0.13618156017734095 -0.6065670374717125 -0.5641291157765085 -2.0544721199957414 -0.5041439855397456 -0.17620343739210476 0.027800510334143547 1.243641322121065 0.7231289090472947 -0.46480564709953665 0.31622776601683794 1.6944039534041913 -0.6900888308577673 1.0963236422214535 -0.1757072801027526 -0.19259659428655368 -0.07381388616818407 -0.3903704477757015 -0.35629384185852775 -0.06204886824070527 0.4374357131842181 -0.05707229513483661 0.2560703388302581 0.2445985090209768 0.6153182060684397 -0.4885688078933321 -0.4988213216173989 -0.26648477494304695 -0.41761249231859066 -0.6483470455690994 0.2019998641175292 1.4557928505874664 0.9189814366739514 0.44977004548425104 -0.3793139419695375 0.7860929401002007 0.2715106348638672 0.37179191216589047 0.9130151532991629 -0.3422874964730809 -1.1468300153833977 -1.0129775496423084 -0.49165373142845137 0.5200639852152524 -0.1199430752174322 -0.9661367146958959 0.24951122389390445 -0.11638313841805387 0.15546643560744788 -0.2948050822208946 -0.00972258825172212 -0.7992948194005082 0.4725310443025059 0.35487943436943936 -0.20329095208950537 -0.1644221529351546 0.29158398964084686 -1.2383841373119102 0.990041338448931 0.6858806376427943 -0.05141240782098638 0.2596283123555113 68 more elements...
0.616153901772039 1.3959300914287158 -0.9838255841777201 -0.04446239478249614 -0.4024702948312819 -0.899527590545441 -1.1499325949285182 0.4747972077455733 0.9486832980505138 -0.28188567142559207 -0.1382310597124975 -0.1649781860725149 0.14417158108303596 0.3408973870813236 -0.19066989069455542 0.7733671239454406 0.540793211927981 0.8879128215858381 0.6717400634434768 -0.1536252479627369 0.4421763754970875 -1.3973763025916548 -0.5583670860074257 -0.7159979104732418 0.8790178788934193 1.0065519397098655 -0.7977934820655597 0.6463361144926378 0.2524228303953382 -0.1551293696177839 0.15039468749669532 0.13694486811742895 1.1701021255027724 0.2034605427045219 0.8059631127036009 -0.4763279970106716 -0.5405622928714735 0.7481814738828283 -0.232040123046526 1.8281668646332128 -1.3096257497360195 0.29449000162031136 0.628186745252037 -0.615233085928409 0.2168160564957622 0.7903983977202063 0.019740851993465147 0.024954490933354584 -0.3061210574697418 0.372348289762486 0.4608142746254302 1.5784896633761374 0.6825950983779567 -0.49328107304631047 0.6063027517674848 0.9067777963521333 0.0421855670959938 1.0182280775743053 0.4377071813449312 -0.27042877841055046 0.38451480670950855 -0.6366638497805234 -0.39141159727019126 0.003150152012331417 68 more elements...
56 more cycles...
-0.9009833038091799 -0.5057690183243752 -0.5562968362716327 2.0841455986962645 -0.31446290262084137 0.327736937337871 0.030876307729171826 -1.5098014000626834 -0.1834323744975015 0.1118579912390687 1.8309179497473291 0.16848407124303164 -1.279695389743949 0.2292300943870591 -0.0964874545046443 -0.46097425601418296 -0.4625966489323498 -1.2925156954575836 0.08116361990057788 -0.20572313989678176 0.7905694150420943 -0.5036805057125169 -0.031218856923840882 0.4582814042913772 -0.17400107828432118 -1.1605447025760305 -0.9333449649598574 -0.4144707150171558 0.28382911538374567 -0.6543682171256191 0.23559527910761846 -0.13267231734559318 -1.0096242502788166 -0.3004673038049869 -0.5523122108622192 -0.4454280356218742 0.07511596003692167 1.1645477749706292 0.9906551263095403 -0.06889587174007397 -0.6351485448719727 0.5885552627455928 0.7277386492357154 0.5146957679767326 0.18836202008865083 1.4504102196249253 -0.1839040044808868 -0.5352399595154373 -0.30769880767493873 0.9637047829242784 0.323733460203382 -0.3799070934602118 0.1520240284963308 -1.1944158131969227 0.013857165890635348 -0.49942656175278877 -0.0974752117745864 -0.7397039331065003 0.0539171890107365 -0.3326591661051913 -1.1771857460922008 1.0983184913003825 -0.8072178506639209 0.6482977393094156 68 more elements...
1.422199961079523 -0.09423394573667565 0.15884569618124422 -0.6443059273856256 0.016869989305543787 0.08344805356642215 0.21924062973172778 -0.3393336115555994 0.057560912688587526 0.04838958457478229 0.15228906372239015 -0.8773286170770715 -0.15810556092415637 -0.5576602982095102 0.07204869165498667 -0.6496842858780376 -0.5138701197773616 -0.0035547360732414157 -0.6020416722097576 -0.6467423182979237 0.27230333266650386 -0.48316420692485257 -0.266796760735728 0.64747970051287 0.3753833991586678 -0.050643840966103 1.303245634530703 0.643915643502339 0.8961148357645141 0.35560290885871326 0.11759624743837055 0.49908786428479696 0.1818469235736877 -1.405021631201501 -1.18847160469458 -0.47977381754974036 -1.1116343561159583 1.1658456952741048 0.25349763030663897 -0.7049763347995962 -0.610435107149151 -0.28342234630671737 -0.05410819439604589 -1.4125969885026435 -0.16967264022976702 -0.2420104425206332 -0.4934841489049451 -0.6313889997595556 -0.2840820855615926 -0.8302050245183595 -0.0729083941390817 -0.044579124892034694 -0.066436697092714 0.17142261163678302 0.23492977220405364 -0.6094497400909694 0.4560160179458239 0.0014458952726557478 -1.2122294482740614 0.5656052781521475 -0.8647314015743788 -0.385184492111967 -0.6621465505170281 -0.22449974255656197 68 more elements...
-0.19487403444517967 -0.3116446665938116 0.8690178661695867 -0.2446064516594071 -0.14986221485637025 0.750943604233168 0.6202257068683648 -1.089656784518537 0.20543388591395348 1.4282792596420868 0.43343484278833444 0.1738221844407455 1.5416103593320847 -0.27800403164048976 -0.309166972242816 0.20338122948483484 -0.11326845490810869 -0.01824461945913658 0.43913690304873965 -0.34521386924592123 -0.49899850184206584 0.9511373316013041 -1.327273795999965 -0.6190842637319384 0.09489063181496044 0.38409709852259577 -0.37591446997540706 -0.5326443705047639 1.4227729673187404 1.2527353147012137 -0.625123067681097 -1.1707661646354688 0.1327900093687203 0.23770576544947253 0.10667064872461879 -0.846277396939781 -0.21532318807655854 -0.6912563687140468 -0.7406471786339479 -0.06920144223388192 0.40917293394131904 -1.3181845645185368 0.658697680928591 0.6237625170601884 -0.5038074538066895 -0.1895190612521969 0.16798225331273597 -0.31359136932308396 0.38616019081625597 -0.07631369168419222 -0.5203339249739828 -0.08996946900802016 -1.2593885863332583 0.9245692335770054 1.0345051610055516 -0.8513136694283882 -0.28555445852921096 -0.17800609829087388 0.5707967539898815 0.12045019486152714 0.1963362293399828 -0.07703802608802751 0.7443211261875079 -0.2823046131352932 68 more elements...
-0.7849754766676131 -0.3436866369463578 -0.4787447068635614 0.373467023427703 0.20699338497185898 0.47353991075189283 1.425667034567499 -0.463280968239934 1.1067971810589328 0.6294706075388901 0.6182648785974137 -0.1895894479985048 0.28924650560678067 0.08922977373830204 -0.48267561646204493 0.1405948775112994 0.15789029786746356 0.4574899491683595 0.193045172561373 0.35997488751604734 0.5673693967877338 0.2506631813943171 -0.7983650532523059 1.0111752172019348 0.9132519728752264 0.46123684061964976 -0.049079182499825236 -0.7152817792976512 0.5358378116568623 -1.1268538567454631 -0.2788144617860173 0.9042507074234452 -0.12237799880188836 0.10941333745182738 -0.06726777718543603 -0.9840171020181239 -0.4324506535323469 -0.18024261950524484 0.6962828815186828 -1.0938234560522588 0.7149224523761606 -0.28302559482842754 0.9168716394107407 -0.33136493080863627 0.3438297427080602 -0.01633400904351992 0.3862381515334449 -0.26762622273011005 -0.8276189760116079 0.6384519681960211 -1.5868627652313443 -0.34752150812141114 1.0606508163092134 0.10965463717146728 -0.7943678786883472 0.3291854659041597 0.40422504044952967 0.5410753425586162 1.2902632626740334 0.1322044613731519 0.09517503991379625 0.21244318429079057 0.48446286012728457 -0.9343647985389707 68 more elements...
-
3 m 4 s
rx
-
3 m 4 s
passedshould work
-
[INFO ]
-
:
----starting ChainsawTest on QamdemodFtn_deintrlvFtn_viterbiFtn----
-
[INFO ]
-
: testing vector length: 410464, containing 101 frames
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:08:48
[Progress] at 572.452 : Elaborate components
[Progress] at 573.303 : Checks and transforms
[Progress] at 580.456 : Generate Verilog
[Warning] toplevel/core/core1/core/cores_0/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_1/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_2/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_3/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_4/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_5/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_6/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_7/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_8/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_9/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_10/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_11/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_12/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_13/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_14/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_15/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_16/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_17/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_18/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_19/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_20/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_21/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_22/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_23/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_24/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_25/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_26/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_27/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_28/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_29/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_30/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_31/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_32/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_33/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_34/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_35/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_36/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_37/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_38/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_39/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_40/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_41/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_42/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_43/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_44/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_45/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_46/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_47/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_48/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_49/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_50/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_51/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_52/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_53/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_54/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_55/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_56/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_57/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_58/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_59/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_60/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_61/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_62/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_63/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_64/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_65/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_66/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_67/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_68/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_69/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_70/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_71/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_72/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_73/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_74/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_75/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_76/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_77/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_78/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_79/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_80/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_81/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_82/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_83/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_84/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_85/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_86/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_87/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_88/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_89/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_90/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_91/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_92/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_93/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_94/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_95/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_96/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_97/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_98/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_99/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_100/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_101/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_102/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_103/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_104/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_105/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_106/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_107/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_108/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_109/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_110/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_111/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_112/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_113/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_114/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_115/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_116/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_117/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_118/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_119/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_120/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_121/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_122/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_123/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_124/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_125/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core/core1/core/cores_126/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] 65805 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 583.315
[Info] Workspace 'testTx' was reallocated as 'testTx_1' to avoid collision
[Progress] Simulation workspace in /home/ltr/IdeaProjects/Chainsaw2/./simWorkspace/testTx_1
[Progress] Verilator compilation started
[Progress] Verilator compilation done in 144400.060 ms
[Progress] Start QamdemodFtn_deintrlvFtn_viterbiFtn_dut test simulation with seed 306214337
-
[INFO ]
-
:
----Chainsaw test status----
modules set as naive:
data length = 7272 cycles, 101 frames in total
[Done] Simulation done in 17731.128 ms
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: test for generator QamdemodFtn_deintrlvFtn_viterbiFtn passed
101-th frame:
input :
-5.19383828662222 + 4.163506922466825i -3.9686624118571086 + 3.3653144131834103i 1.412013316433868 + -3.046665088597567i 2.9250999642583464 + 1.0329046212190676i -0.7610687666530616 + 2.3266284980431577i 2.0904928790195823 + 0.6081242053369997i 1.8340442608956573 + -1.8106217479176483i -1.4745738799609955 + 0.513400823303127i 1.4508052632696464 + -1.5300200784258333i 1.438195687166309 + 0.3726105011796472i 1.2548250120947761 + -0.4672570152332346i 1.2177826411989303 + 0.24688276551533678i 0.3731040256080473 + 0.340107903583611i 0.38643545427963516 + -0.38258991964035677i 0.3710743708004514 + 0.3093729634908488i -0.35285085586214726 + -0.994831857568737i 238 more elements...
4.471072400096279 + 2.180782610800975i 1.3067617062627643 + -0.9912421458862365i 3.0885800992838113 + -0.5922633485114908i 0.7928141421402048 + 0.7209509441165116i -2.4718339061064905 + 2.2082591385740993i -2.084398595873417 + 2.0472537076021102i 1.6587251698628827 + -1.700835533548465i 1.5377465939602812 + 1.6041599174321972i 0.506936369624217 + 1.4301782721110008i -1.25587376801593 + 1.329081404923425i -1.2643370537139171 + 0.4253741358377535i 0.4409088925921914 + 1.1174613761597143i -1.102016766651111 + -1.0208683497855646i 0.36282406997070576 + 0.32015433534933574i 0.9810707778855413 + 0.24483428611759359i -0.8431293811976269 + 1.0043673869138179i 238 more elements...
1.4623836859220591 + 5.335126803004162i -3.4451883492158606 + 0.9501865586318934i -2.798866388818885 + 0.8428415719410391i -2.4575833770414115 + -0.9119420043468447i 1.0094760776490566 + -0.5190244205362923i 2.18153716057239 + 2.0267356880457386i -1.468739768025835 + 1.989198464780001i -1.3971638634490617 + 0.7075727982427881i -0.3211486845739609 + -0.38935426140874035i 0.5763959943421768 + 0.4634425268587777i 0.4962450532853421 + -1.1163749072058629i 0.514624079634098 + 0.5025566234455275i -0.21487201244104862 + 0.45093615783994806i -0.8949299614289671 + 0.4383109510575554i -0.29952203378400394 + -0.8569750308721727i 0.9542202769851511 + -0.9183593584267313i 238 more elements...
-1.6449021542471098 + 1.2623344854384273i -3.299155752124009 + -1.496226442721286i 3.286614637440001 + -0.8118544957472097i 2.7133544471816102 + 0.9909075233981992i -0.6559459470091006 + -0.8197711960442093i -1.874481455656205 + 0.7834423958445429i -1.7668355980135877 + -1.682274655937935i -1.6020948670469093 + -0.5441915610105137i -1.5069631825052856 + -0.36307628652058477i -0.37130709105918447 + 1.3932428200147173i -1.207944498451205 + 0.4772149093873582i 0.4119289068342179 + 0.381967546609097i 0.3691582253855547 + 0.3921853077267411i -0.3045200976607849 + 1.0949457612139977i 0.3507102524347455 + -0.28835469420832177i -0.921565529010413 + 0.43437428509865184i 238 more elements...
8 more cycles...
3.7168786070004924 + -4.533430988861963i -0.10001586760124742 + -1.2260448405151188i -0.29645600008949363 + -3.0371626803332115i 1.5688542993744794 + 1.1141428609002622i -1.805197619889131 + -2.396034954643448i -1.5715335305875144 + 0.7955309620298152i -1.3192963093360255 + -1.6401296784459918i -0.1118396182062647 + -1.4112907047466265i -1.10812383829783 + -1.2522477540427701i 0.7104921278424151 + 0.5799298941528712i 0.7571691227033024 + 0.4875599621554123i 1.4332877609354928 + 0.44576549340306254i 0.6307127056011324 + 1.1635609342776723i 0.5452736940409069 + -0.21187570347516005i 0.4583895403939898 + -0.8096125260600028i -0.7471521615007912 + 0.5291440475128342i 238 more elements...
-4.0903914457085735 + -2.2265838070936543i -3.1263219789428556 + -3.9907870513699075i -2.906845427039408 + -1.4469931515084347i 2.7104699783148343 + -2.4846094319415553i 2.250766558066484 + 0.8637621270169764i 2.0070517564788273 + -0.5873591409403375i 1.7829911428379372 + 0.6609880332052611i -1.4859069036110875 + 0.6127113497049083i -1.262056637192401 + -0.4876903066452639i 0.4476352057276962 + 0.3104708851914255i 0.35966335957428613 + -1.2735220110983603i 0.4635171365072408 + 1.1800222654970456i 1.0685644226730746 + 0.9655560495025501i -0.29248492958272315 + 0.3830392179984285i -0.3586904929756626 + -0.9718901994026602i 0.3525219969271127 + -0.326927709918284i 238 more elements...
-5.231020850773762 + 4.009665031148942i -1.2251614104799478 + 1.019076995895817i 3.395457577331655 + -0.973379997787262i -2.5512211864587586 + 2.5191423706282636i -2.098586637387175 + -2.32393095479282i -1.984834236700623 + 0.6760543592239422i 1.7616021561088815 + 1.8562422589162393i 0.56912603730013 + -0.4678397668240497i 0.45747337156940376 + -0.430790965062791i 0.5769282688974996 + -0.41898604766553255i -1.1731601053893106 + -0.34802651670758056i 0.3582590628822485 + -1.1037280972892962i 1.0076820790433316 + -0.3473488837797516i -1.0411995631133442 + -0.9304902878610612i 0.9383996640753789 + -0.9469090393962649i -0.27206776598308957 + 0.3206631999750107i 238 more elements...
-3.944260913411732 + -5.5672312509535i -3.3096831945178855 + -3.9684285387491305i -1.1655924070648123 + 3.0344595641780416i 0.8285159892936587 + 2.7246823243045792i 2.2335927725712708 + -0.7814961872727071i -1.980616347545482 + -0.6507457537933371i 1.7614241900198584 + -0.5302927163219394i -1.6058798351590036 + -1.4548034812915671i -1.2808824214723207 + 1.5445849175143438i -0.48802671430053884 + -1.2396206365057818i -0.4323026974111294 + -1.2683798481515378i -1.1405755770871473 + 1.2114260349758161i -0.3240474978199356 + 1.1073640970912992i -0.2929219938262633 + 0.39893914740354136i 0.2869545122848488 + 0.30444363197213103i -0.25704225011430115 + 0.3230946740214822i 238 more elements...
yours :
0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 63 more elements...
1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 63 more elements...
0 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 63 more elements...
0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1 63 more elements...
56 more cycles...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
golden:
0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 0 1 1 63 more elements...
1 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 0 1 1 1 1 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 0 0 1 0 63 more elements...
0 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 63 more elements...
0 1 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1 63 more elements...
56 more cycles...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 63 more elements...
-
56 m 16 s
synths
-
1 m 12 s
passedshould synth for convFtn
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:11:51
[Progress] at 756.183 : Elaborate components
[Progress] at 756.256 : Checks and transforms
[Progress] at 756.319 : Generate Verilog
[Done] at 756.360
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog synthConvFtn.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthConvFtn -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthConvFtn -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 18873
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5612.348 ; gain = 337.793 ; free physical = 37039 ; free virtual = 73293
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthConvFtn' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthConvFtn/synthConvFtn.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthConvFtn' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthConvFtn/synthConvFtn.v:6]
WARNING: [Synth 8-7129] Port lastIn in module synthConvFtn is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5703.285 ; gain = 428.730 ; free physical = 38113 ; free virtual = 74368
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5721.098 ; gain = 446.543 ; free physical = 38113 ; free virtual = 74368
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5721.098 ; gain = 446.543 ; free physical = 38113 ; free virtual = 74368
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5721.098 ; gain = 0.000 ; free physical = 38107 ; free virtual = 74362
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthConvFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthConvFtn/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5899.691 ; gain = 0.000 ; free physical = 38001 ; free virtual = 74255
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5899.691 ; gain = 0.000 ; free physical = 38000 ; free virtual = 74255
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 5899.691 ; gain = 625.137 ; free physical = 38102 ; free virtual = 74357
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 5899.691 ; gain = 625.137 ; free physical = 38102 ; free virtual = 74357
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 5899.691 ; gain = 625.137 ; free physical = 38102 ; free virtual = 74357
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 5899.691 ; gain = 625.137 ; free physical = 38105 ; free virtual = 74362
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---XORs :
3 Input 1 Bit XORs := 81
4 Input 1 Bit XORs := 100
2 Input 1 Bit XORs := 200
+---Registers :
1 Bit Registers := 1016
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port lastIn in module synthConvFtn is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 5899.691 ; gain = 625.137 ; free physical = 38092 ; free virtual = 74354
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 6043.238 ; gain = 768.684 ; free physical = 37647 ; free virtual = 73909
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 6054.254 ; gain = 779.699 ; free physical = 37644 ; free virtual = 73906
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `synthConvFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthConvFtn' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:23 ; elapsed = 00:00:25 . Memory (MB): peak = 6064.277 ; gain = 789.723 ; free physical = 37642 ; free virtual = 73904
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 6072.215 ; gain = 797.660 ; free physical = 37625 ; free virtual = 73887
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 6072.215 ; gain = 797.660 ; free physical = 37625 ; free virtual = 73887
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 6072.215 ; gain = 797.660 ; free physical = 37627 ; free virtual = 73889
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 6072.215 ; gain = 797.660 ; free physical = 37627 ; free virtual = 73889
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 6072.215 ; gain = 797.660 ; free physical = 37627 ; free virtual = 73889
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 6072.215 ; gain = 797.660 ; free physical = 37627 ; free virtual = 73889
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT2 | 127|
|2 |LUT6 | 254|
|3 |FDCE | 762|
|4 |FDRE | 254|
+------+-----+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 6072.215 ; gain = 797.660 ; free physical = 37627 ; free virtual = 73889
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 6072.215 ; gain = 619.066 ; free physical = 37656 ; free virtual = 73918
Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:28 . Memory (MB): peak = 6072.223 ; gain = 797.660 ; free physical = 37656 ; free virtual = 73918
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6079.152 ; gain = 0.000 ; free physical = 37723 ; free virtual = 73985
WARNING: [Netlist 29-101] Netlist 'synthConvFtn' is not ideal for floorplanning, since the cellview 'synthConvFtn' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthConvFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthConvFtn/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6204.480 ; gain = 0.000 ; free physical = 37418 ; free virtual = 73680
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: f17fdfb6
INFO: [Common 17-83] Releasing license: Synthesis
17 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:42 ; elapsed = 00:00:40 . Memory (MB): peak = 6204.480 ; gain = 1036.684 ; free physical = 37597 ; free virtual = 73859
# write_checkpoint -force synthConvFtn_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthConvFtn/synthConvFtn_after_synth.dcp' has been generated.
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:12:41 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthConvFtn
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| CLB LUTs* | 318 | 0 | 0 | 1182240 | 0.03 |
| LUT as Logic | 318 | 0 | 0 | 1182240 | 0.03 |
| LUT as Memory | 0 | 0 | 0 | 591840 | 0.00 |
| CLB Registers | 1016 | 0 | 0 | 2364480 | 0.04 |
| Register as Flip Flop | 1016 | 0 | 0 | 2364480 | 0.04 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 147780 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 591120 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 762 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 254 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDCE | 762 | Register |
| LUT6 | 254 | CLB |
| FDRE | 254 | Register |
| LUT2 | 127 | CLB |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:12:59 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthConvFtn
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (MET) : 0.839ns (required time - arrival time)
Source: _zz_dataOut_100_1_reg[0]/C
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: _zz_dataOut_100_11_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 0.393ns (logic 0.227ns (57.761%) route 0.166ns (42.239%))
Logic Levels: 1 (LUT6=1)
Clock Path Skew: -0.008ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.028ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=1015, unset) 0.028 0.028 clk
FDCE r _zz_dataOut_100_1_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_FDCE_C_Q) 0.077 0.105 r _zz_dataOut_100_1_reg[0]/Q
net (fo=2, unplaced) 0.118 0.223 _zz_dataOut_100_1
LUT6 (Prop_LUT6_I0_O) 0.150 0.373 r _zz_dataOut_100_11[0]_i_1/O
net (fo=1, unplaced) 0.048 0.421 _zz_dataOut_100_110
FDRE r _zz_dataOut_100_11_reg[0]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=1015, unset) 0.020 1.270 clk
FDRE r _zz_dataOut_100_11_reg[0]/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDRE (Setup_FDRE_C_D) 0.025 1.260 _zz_dataOut_100_11_reg[0]
-------------------------------------------------------------------
required time 1.260
arrival time -0.421
-------------------------------------------------------------------
slack 0.839
report_timing: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 7071.840 ; gain = 690.480 ; free physical = 37395 ; free virtual = 73658
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:12:59 2022...
-
[INFO ]
-
: binary adder cost = 0
-
[INFO ]
-
: ternary adder cost = 0
-
[INFO ]
-
: reg cost = 1016
-
[INFO ]
-
:
LUT: 318
FF: 1016
DSP: 0
BRAM: 0
CARRY8: 0
-
[INFO ]
-
:
fmax = 2433.0900243308997 MHz
-
1 m 17 s
passedshould synth for intrlvFtn
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:13:03
[Progress] at 828.143 : Elaborate components
[Progress] at 828.209 : Checks and transforms
[Progress] at 828.242 : Generate Verilog
[Done] at 828.261
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog synthIntrlvFtn.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthIntrlvFtn -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthIntrlvFtn -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 19909
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5612.352 ; gain = 337.793 ; free physical = 37109 ; free virtual = 73363
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthIntrlvFtn' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIntrlvFtn/synthIntrlvFtn.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthIntrlvFtn' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIntrlvFtn/synthIntrlvFtn.v:6]
WARNING: [Synth 8-7129] Port validIn in module synthIntrlvFtn is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5677.289 ; gain = 402.730 ; free physical = 38206 ; free virtual = 74460
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5695.102 ; gain = 420.543 ; free physical = 38209 ; free virtual = 74463
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5695.102 ; gain = 420.543 ; free physical = 38209 ; free virtual = 74463
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5695.102 ; gain = 0.000 ; free physical = 38202 ; free virtual = 74457
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIntrlvFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIntrlvFtn/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5844.695 ; gain = 0.000 ; free physical = 38089 ; free virtual = 74344
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 5844.695 ; gain = 0.000 ; free physical = 38089 ; free virtual = 74344
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 5844.695 ; gain = 570.137 ; free physical = 38182 ; free virtual = 74438
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 5844.695 ; gain = 570.137 ; free physical = 38182 ; free virtual = 74438
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 5844.695 ; gain = 570.137 ; free physical = 38182 ; free virtual = 74438
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 5844.695 ; gain = 570.137 ; free physical = 38175 ; free virtual = 74431
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
+---Muxes :
2 Input 254 Bit Muxes := 7
2 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port validIn in module synthIntrlvFtn is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:17 ; elapsed = 00:00:17 . Memory (MB): peak = 5844.695 ; gain = 570.137 ; free physical = 38150 ; free virtual = 74410
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 6054.273 ; gain = 779.715 ; free physical = 37805 ; free virtual = 74065
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37737 ; free virtual = 73997
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `synthIntrlvFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIntrlvFtn' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37733 ; free virtual = 73992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37732 ; free virtual = 73992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37732 ; free virtual = 73992
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37732 ; free virtual = 73991
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37732 ; free virtual = 73991
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37732 ; free virtual = 73991
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37732 ; free virtual = 73991
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT2 | 1|
|2 |LUT3 | 4|
|3 |LUT4 | 2|
|4 |LUT5 | 259|
|5 |LUT6 | 767|
|6 |FDCE | 8|
|7 |FDRE | 254|
+------+-----+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 6232.539 ; gain = 957.980 ; free physical = 37732 ; free virtual = 73991
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 6232.539 ; gain = 808.387 ; free physical = 37763 ; free virtual = 74023
Synthesis Optimization Complete : Time (s): cpu = 00:00:32 ; elapsed = 00:00:34 . Memory (MB): peak = 6232.547 ; gain = 957.980 ; free physical = 37763 ; free virtual = 74023
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6232.547 ; gain = 0.000 ; free physical = 37853 ; free virtual = 74113
WARNING: [Netlist 29-101] Netlist 'synthIntrlvFtn' is not ideal for floorplanning, since the cellview 'synthIntrlvFtn' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIntrlvFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIntrlvFtn/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6238.477 ; gain = 0.000 ; free physical = 37744 ; free virtual = 74003
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: 748c01b5
INFO: [Common 17-83] Releasing license: Synthesis
17 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:47 ; elapsed = 00:00:45 . Memory (MB): peak = 6238.477 ; gain = 1070.676 ; free physical = 37988 ; free virtual = 74248
# write_checkpoint -force synthIntrlvFtn_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIntrlvFtn/synthIntrlvFtn_after_synth.dcp' has been generated.
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:13:58 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthIntrlvFtn
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| CLB LUTs* | 1033 | 0 | 0 | 1182240 | 0.09 |
| LUT as Logic | 1033 | 0 | 0 | 1182240 | 0.09 |
| LUT as Memory | 0 | 0 | 0 | 591840 | 0.00 |
| CLB Registers | 262 | 0 | 0 | 2364480 | 0.01 |
| Register as Flip Flop | 262 | 0 | 0 | 2364480 | 0.01 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 147780 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 591120 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 8 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 254 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 767 | CLB |
| LUT5 | 259 | CLB |
| FDRE | 254 | Register |
| FDCE | 8 | Register |
| LUT3 | 4 | CLB |
| LUT4 | 2 | CLB |
| LUT2 | 1 | CLB |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:14:17 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthIntrlvFtn
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -0.579ns (required time - arrival time)
Source: localCounter_value_reg[4]/C
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: ret_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 1.811ns (logic 0.568ns (31.364%) route 1.243ns (68.636%))
Logic Levels: 6 (LUT5=2 LUT6=4)
Clock Path Skew: -0.008ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.028ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=261, unset) 0.028 0.028 clk
FDCE r localCounter_value_reg[4]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_FDCE_C_Q) 0.077 0.105 r localCounter_value_reg[4]/Q
net (fo=5, unplaced) 0.126 0.231 localCounter_value[4]
LUT5 (Prop_LUT5_I0_O) 0.125 0.356 r ret[0]_i_2/O
net (fo=129, unplaced) 0.246 0.602 ret[0]_i_2_n_0
LUT6 (Prop_LUT6_I1_O) 0.090 0.692 r localCounter_value[6]_i_1/O
net (fo=128, unplaced) 0.288 0.980 p_0_in[6]
LUT6 (Prop_LUT6_I4_O) 0.038 1.018 r ret[0]_i_30/O
net (fo=4, unplaced) 0.169 1.187 _zz_ret_5[134]
LUT6 (Prop_LUT6_I0_O) 0.100 1.287 r ret[0]_i_10/O
net (fo=4, unplaced) 0.169 1.456 _zz_ret_3[158]
LUT6 (Prop_LUT6_I0_O) 0.100 1.556 r ret[0]_i_5/O
net (fo=2, unplaced) 0.197 1.753 _zz_ret_1[0]
LUT5 (Prop_LUT5_I4_O) 0.038 1.791 r ret[0]_i_1/O
net (fo=1, unplaced) 0.048 1.839 _zz_ret[0]
FDRE r ret_reg[0]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=261, unset) 0.020 1.270 clk
FDRE r ret_reg[0]/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDRE (Setup_FDRE_C_D) 0.025 1.260 ret_reg[0]
-------------------------------------------------------------------
required time 1.260
arrival time -1.839
-------------------------------------------------------------------
slack -0.579
report_timing: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 7065.875 ; gain = 688.496 ; free physical = 37487 ; free virtual = 73747
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:14:17 2022...
-
[INFO ]
-
: binary adder cost = 7
-
[INFO ]
-
: ternary adder cost = 0
-
[INFO ]
-
: reg cost = 7
-
[INFO ]
-
:
LUT: 1033
FF: 262
DSP: 0
BRAM: 0
CARRY8: 0
-
[INFO ]
-
:
fmax = 546.7468562055768 MHz
-
1 m 51 s
passedshould synth for qammodFtn
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:14:21
[Progress] at 905.526 : Elaborate components
-
[INFO ]
-
:
----qammod with bit & power alloc----
bitAlloc for adaptive qammod: 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
powAlloc for adaptive qammod: 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
[Progress] at 905.706 : Checks and transforms
[Progress] at 906.036 : Generate Verilog
[Warning] 1 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 906.325
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog unamed.v
# read_verilog unamed_1.v
# read_verilog synthQammodFtn.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthQammodFtn -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthQammodFtn -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 21015
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5613.328 ; gain = 338.793 ; free physical = 37179 ; free virtual = 73435
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthQammodFtn' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/synthQammodFtn.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_0.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5347]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_1.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5356]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_2.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5365]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_3.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5374]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_4.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5383]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_5.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5392]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_6.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5401]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_7.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5410]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_8.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5419]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_9.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5428]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_10.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5437]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_11.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5446]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_12.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5455]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_13.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5464]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_14.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5473]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_15.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5482]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_16.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5491]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_17.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5500]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_18.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5509]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_19.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5518]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_20.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5527]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_21.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5536]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_22.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5545]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_23.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5554]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_24.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5563]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_25.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5572]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_26.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5581]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_27.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5590]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_28.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5599]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_29.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5608]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_30.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5617]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_31.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5626]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_32.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5635]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_33.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5644]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_34.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5653]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_35.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5662]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_36.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5671]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_37.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5680]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_38.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5689]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_39.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5698]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_40.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5707]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_41.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5716]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_42.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5725]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_43.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5734]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_44.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5743]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_45.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5752]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_46.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5761]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_47.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5770]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_48.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5779]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_49.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5788]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_50.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5797]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_51.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5806]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_52.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5815]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_53.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5824]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_54.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5833]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_55.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5842]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_56.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5851]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_57.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5860]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_58.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5869]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_59.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5878]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_60.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5887]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_61.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5896]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_62.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5905]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_63.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5914]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_64.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5923]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_65.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5932]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_66.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5941]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_67.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5950]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_68.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5959]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_69.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5968]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_70.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5977]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_71.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5986]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_72.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:5995]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_73.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6004]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_74.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6013]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_75.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6022]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_76.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6031]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_77.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6040]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_78.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6049]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_79.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6058]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_80.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6067]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_81.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6076]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_82.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6085]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_83.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6094]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_84.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6103]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_85.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6112]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_86.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6121]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_87.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6130]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_88.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6139]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_89.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6148]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_90.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6157]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_91.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6166]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_92.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6175]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_93.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6184]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_94.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6193]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_95.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6202]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_96.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6211]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_97.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6220]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_98.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6229]
INFO: [Synth 8-3876] $readmem data file 'synthQammodFtn.v_toplevel_core_qamLuts_99.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6238]
INFO: [Common 17-14] Message 'Synth 8-3876' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6155] done synthesizing module 'unamed' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_1' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed_1.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_1' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/unamed_1.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthQammodFtn' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/synthQammodFtn.v:6]
WARNING: [Synth 8-7129] Port validIn in module unamed_1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5726.234 ; gain = 451.699 ; free physical = 38244 ; free virtual = 74502
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5741.078 ; gain = 466.543 ; free physical = 38244 ; free virtual = 74502
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 5741.078 ; gain = 466.543 ; free physical = 38244 ; free virtual = 74502
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 5741.078 ; gain = 0.000 ; free physical = 38236 ; free virtual = 74494
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5922.672 ; gain = 0.000 ; free physical = 38114 ; free virtual = 74372
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.09 . Memory (MB): peak = 5922.672 ; gain = 0.000 ; free physical = 38112 ; free virtual = 74369
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 5922.672 ; gain = 648.137 ; free physical = 38230 ; free virtual = 74488
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 5922.672 ; gain = 648.137 ; free physical = 38230 ; free virtual = 74488
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 5922.672 ; gain = 648.137 ; free physical = 38233 ; free virtual = 74491
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 5922.672 ; gain = 648.137 ; free physical = 38188 ; free virtual = 74447
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 2 Bit Adders := 1
+---Registers :
36 Bit Registers := 254
2 Bit Registers := 1
1 Bit Registers := 1778
+---Muxes :
17 Input 36 Bit Muxes := 254
2 Input 2 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[2]' (FD) to '_zz_qamLuts_57_port0_reg[7]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[3]' (FD) to '_zz_qamLuts_57_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[4]' (FD) to '_zz_qamLuts_57_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[5]' (FD) to '_zz_qamLuts_57_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[6]' (FD) to '_zz_qamLuts_57_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[7]' (FD) to '_zz_qamLuts_57_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[8]' (FD) to '_zz_qamLuts_57_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[11]' (FD) to '_zz_qamLuts_57_port0_reg[12]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[12]' (FD) to '_zz_qamLuts_57_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[13]' (FD) to '_zz_qamLuts_57_port0_reg[14]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[14]' (FD) to '_zz_qamLuts_57_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[15]' (FD) to '_zz_qamLuts_57_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[16]' (FD) to '_zz_qamLuts_57_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[20]' (FD) to '_zz_qamLuts_57_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[21]' (FD) to '_zz_qamLuts_57_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[22]' (FD) to '_zz_qamLuts_57_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[23]' (FD) to '_zz_qamLuts_57_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[24]' (FD) to '_zz_qamLuts_57_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[25]' (FD) to '_zz_qamLuts_57_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[26]' (FD) to '_zz_qamLuts_57_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[29]' (FD) to '_zz_qamLuts_57_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[30]' (FD) to '_zz_qamLuts_57_port0_reg[31]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[31]' (FD) to '_zz_qamLuts_57_port0_reg[32]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[32]' (FD) to '_zz_qamLuts_57_port0_reg[33]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[33]' (FD) to '_zz_qamLuts_57_port0_reg[34]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[34]' (FD) to '_zz_qamLuts_57_port0_reg[35]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[2]' (FD) to '_zz_qamLuts_58_port0_reg[7]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[3]' (FD) to '_zz_qamLuts_58_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[4]' (FD) to '_zz_qamLuts_58_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[5]' (FD) to '_zz_qamLuts_58_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[6]' (FD) to '_zz_qamLuts_58_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[7]' (FD) to '_zz_qamLuts_58_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[8]' (FD) to '_zz_qamLuts_58_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[11]' (FD) to '_zz_qamLuts_58_port0_reg[12]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[12]' (FD) to '_zz_qamLuts_58_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[13]' (FD) to '_zz_qamLuts_58_port0_reg[14]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[14]' (FD) to '_zz_qamLuts_58_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[15]' (FD) to '_zz_qamLuts_58_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[16]' (FD) to '_zz_qamLuts_58_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[20]' (FD) to '_zz_qamLuts_58_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[21]' (FD) to '_zz_qamLuts_58_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[22]' (FD) to '_zz_qamLuts_58_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[23]' (FD) to '_zz_qamLuts_58_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[24]' (FD) to '_zz_qamLuts_58_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[25]' (FD) to '_zz_qamLuts_58_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[26]' (FD) to '_zz_qamLuts_58_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[29]' (FD) to '_zz_qamLuts_58_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[30]' (FD) to '_zz_qamLuts_58_port0_reg[31]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[31]' (FD) to '_zz_qamLuts_58_port0_reg[32]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[32]' (FD) to '_zz_qamLuts_58_port0_reg[33]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[33]' (FD) to '_zz_qamLuts_58_port0_reg[34]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[34]' (FD) to '_zz_qamLuts_58_port0_reg[35]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[2]' (FD) to '_zz_qamLuts_59_port0_reg[7]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[3]' (FD) to '_zz_qamLuts_59_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[4]' (FD) to '_zz_qamLuts_59_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[5]' (FD) to '_zz_qamLuts_59_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[6]' (FD) to '_zz_qamLuts_59_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[7]' (FD) to '_zz_qamLuts_59_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[8]' (FD) to '_zz_qamLuts_59_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[11]' (FD) to '_zz_qamLuts_59_port0_reg[12]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[12]' (FD) to '_zz_qamLuts_59_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[13]' (FD) to '_zz_qamLuts_59_port0_reg[14]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[14]' (FD) to '_zz_qamLuts_59_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[15]' (FD) to '_zz_qamLuts_59_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[16]' (FD) to '_zz_qamLuts_59_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[20]' (FD) to '_zz_qamLuts_59_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[21]' (FD) to '_zz_qamLuts_59_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[22]' (FD) to '_zz_qamLuts_59_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[23]' (FD) to '_zz_qamLuts_59_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[24]' (FD) to '_zz_qamLuts_59_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[25]' (FD) to '_zz_qamLuts_59_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[26]' (FD) to '_zz_qamLuts_59_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[29]' (FD) to '_zz_qamLuts_59_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[30]' (FD) to '_zz_qamLuts_59_port0_reg[31]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[31]' (FD) to '_zz_qamLuts_59_port0_reg[32]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[32]' (FD) to '_zz_qamLuts_59_port0_reg[33]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[33]' (FD) to '_zz_qamLuts_59_port0_reg[34]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[34]' (FD) to '_zz_qamLuts_59_port0_reg[35]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[2]' (FD) to '_zz_qamLuts_60_port0_reg[7]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[3]' (FD) to '_zz_qamLuts_60_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[4]' (FD) to '_zz_qamLuts_60_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[5]' (FD) to '_zz_qamLuts_60_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[6]' (FD) to '_zz_qamLuts_60_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[7]' (FD) to '_zz_qamLuts_60_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[8]' (FD) to '_zz_qamLuts_60_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[11]' (FD) to '_zz_qamLuts_60_port0_reg[12]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[12]' (FD) to '_zz_qamLuts_60_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[13]' (FD) to '_zz_qamLuts_60_port0_reg[14]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[14]' (FD) to '_zz_qamLuts_60_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[15]' (FD) to '_zz_qamLuts_60_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[16]' (FD) to '_zz_qamLuts_60_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[20]' (FD) to '_zz_qamLuts_60_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[21]' (FD) to '_zz_qamLuts_60_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[22]' (FD) to '_zz_qamLuts_60_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[23]' (FD) to '_zz_qamLuts_60_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[24]' (FD) to '_zz_qamLuts_60_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[25]' (FD) to '_zz_qamLuts_60_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[26]' (FD) to '_zz_qamLuts_60_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[29]' (FD) to '_zz_qamLuts_60_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[30]' (FD) to '_zz_qamLuts_60_port0_reg[31]'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:47 . Memory (MB): peak = 5922.672 ; gain = 648.137 ; free physical = 28949 ; free virtual = 65235
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:55 . Memory (MB): peak = 6068.250 ; gain = 793.715 ; free physical = 28291 ; free virtual = 64586
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:56 . Memory (MB): peak = 6092.266 ; gain = 817.730 ; free physical = 28266 ; free virtual = 64562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-5816] Retiming module `synthQammodFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthQammodFtn' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:57 . Memory (MB): peak = 6108.281 ; gain = 833.746 ; free physical = 28238 ; free virtual = 64538
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:33 ; elapsed = 00:01:01 . Memory (MB): peak = 6116.219 ; gain = 841.684 ; free physical = 28172 ; free virtual = 64472
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:33 ; elapsed = 00:01:01 . Memory (MB): peak = 6116.219 ; gain = 841.684 ; free physical = 28172 ; free virtual = 64472
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:33 ; elapsed = 00:01:01 . Memory (MB): peak = 6116.219 ; gain = 841.684 ; free physical = 28169 ; free virtual = 64469
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:33 ; elapsed = 00:01:01 . Memory (MB): peak = 6116.219 ; gain = 841.684 ; free physical = 28169 ; free virtual = 64469
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:33 ; elapsed = 00:01:01 . Memory (MB): peak = 6116.219 ; gain = 841.684 ; free physical = 28167 ; free virtual = 64467
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:33 ; elapsed = 00:01:01 . Memory (MB): peak = 6116.219 ; gain = 841.684 ; free physical = 28167 ; free virtual = 64467
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT1 | 508|
|2 |LUT2 | 1020|
|3 |LUT3 | 1|
|4 |FDCE | 2|
|5 |FDRE | 4318|
+------+-----+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:33 ; elapsed = 00:01:01 . Memory (MB): peak = 6116.219 ; gain = 841.684 ; free physical = 28167 ; free virtual = 64467
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:32 ; elapsed = 00:01:00 . Memory (MB): peak = 6120.129 ; gain = 664.000 ; free physical = 36984 ; free virtual = 73284
Synthesis Optimization Complete : Time (s): cpu = 00:00:37 ; elapsed = 00:01:05 . Memory (MB): peak = 6120.129 ; gain = 845.594 ; free physical = 36991 ; free virtual = 73284
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6125.125 ; gain = 0.000 ; free physical = 36976 ; free virtual = 73269
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6217.406 ; gain = 0.000 ; free physical = 36788 ; free virtual = 73081
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: 910cbf97
INFO: [Common 17-83] Releasing license: Synthesis
227 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:49 ; elapsed = 00:01:18 . Memory (MB): peak = 6217.406 ; gain = 1049.629 ; free physical = 37004 ; free virtual = 73296
# write_checkpoint -force synthQammodFtn_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQammodFtn/synthQammodFtn_after_synth.dcp' has been generated.
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:15:49 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthQammodFtn
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| CLB LUTs* | 1529 | 0 | 0 | 1182240 | 0.13 |
| LUT as Logic | 1529 | 0 | 0 | 1182240 | 0.13 |
| LUT as Memory | 0 | 0 | 0 | 591840 | 0.00 |
| CLB Registers | 4320 | 0 | 0 | 2364480 | 0.18 |
| Register as Flip Flop | 4320 | 0 | 0 | 2364480 | 0.18 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 147780 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 591120 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 2 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 4318 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 4318 | Register |
| LUT2 | 1020 | CLB |
| LUT1 | 508 | CLB |
| FDCE | 2 | Register |
| LUT3 | 1 | CLB |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:16:08 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthQammodFtn
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (MET) : 0.570ns (required time - arrival time)
Source: s2p/counter_value_reg[0]/C
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: s2p/buffers_0_0_reg[0]/CE
(rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 0.576ns (logic 0.115ns (19.965%) route 0.461ns (80.035%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.008ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.028ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=4319, unset) 0.028 0.028 s2p/clk
FDCE r s2p/counter_value_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_FDCE_C_Q) 0.077 0.105 f s2p/counter_value_reg[0]/Q
net (fo=5, unplaced) 0.167 0.272 s2p/counter_value[0]
LUT2 (Prop_LUT2_I1_O) 0.038 0.310 r s2p/buffers_0_0[0]_i_1/O
net (fo=254, unplaced) 0.294 0.604 s2p/when_S2P_l32
FDRE r s2p/buffers_0_0_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=4319, unset) 0.020 1.270 s2p/clk
FDRE r s2p/buffers_0_0_reg[0]/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDRE (Setup_FDRE_C_CE) -0.061 1.174 s2p/buffers_0_0_reg[0]
-------------------------------------------------------------------
required time 1.174
arrival time -0.604
-------------------------------------------------------------------
slack 0.570
report_timing: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 7096.746 ; gain = 712.457 ; free physical = 35698 ; free virtual = 71992
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:16:08 2022...
-
[INFO ]
-
: binary adder cost = 2
-
[INFO ]
-
: ternary adder cost = 0
-
[INFO ]
-
: reg cost = 10924
-
[INFO ]
-
:
LUT: 1529
FF: 4320
DSP: 0
BRAM: 0
CARRY8: 0
-
[INFO ]
-
:
fmax = 1470.5882352941173 MHz
-
7 m 57 s
passedshould synth for hsIfftFtn
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:16:12
[Progress] at 1016.949 : Elaborate components
[Progress] at 1017.121 : Checks and transforms
[Progress] at 1018.973 : Generate Verilog
[Warning] 212 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 1019.728
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog ComplexMult.v
# read_verilog unamed.v
# read_verilog unamed_3.v
# read_verilog unamed_11.v
# read_verilog unamed_20.v
# read_verilog unamed_21.v
# read_verilog unamed_22.v
# read_verilog unamed_23.v
# read_verilog unamed_24.v
# read_verilog unamed_25.v
# read_verilog unamed_26.v
# read_verilog unamed_31.v
# read_verilog unamed_32.v
# read_verilog unamed_33.v
# read_verilog unamed_34.v
# read_verilog unamed_38.v
# read_verilog unamed_40.v
# read_verilog unamed_41.v
# read_verilog unamed_42.v
# read_verilog unamed_47.v
# read_verilog unamed_48.v
# read_verilog unamed_49.v
# read_verilog unamed_50.v
# read_verilog unamed_56.v
# read_verilog unamed_57.v
# read_verilog unamed_58.v
# read_verilog unamed_65.v
# read_verilog unamed_66.v
# read_verilog unamed_74.v
# read_verilog unamed_91.v
# read_verilog unamed_92.v
# read_verilog unamed_94.v
# read_verilog unamed_95.v
# read_verilog unamed_103.v
# read_verilog matintrlv_r64_c8_w36_sw64_dut.v
# read_verilog matintrlv_r8_c64_w36_sw64_dut.v
# read_verilog ifft_n64_factors_8_8_scales_2_2_dut.v
# read_verilog ifft_n8_factors_8_scales_1_dut.v
# read_verilog anon.v
# read_verilog unamed_104.v
# read_verilog unamed_105.v
# read_verilog anon_1.v
# read_verilog unamed_106.v
# read_verilog hsIfftPre_dut.v
# read_verilog ifft_n512_sw64_factors_8_8_8_dut.v
# read_verilog S2P_s64_p512_dut.v
# read_verilog hsIfftPost_dut.v
# read_verilog P2S_s132_p528_bl1_bw18_dut.v
# read_verilog synthIfftFtn.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthIfftFtn -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthIfftFtn -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 23006
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5613.348 ; gain = 337.793 ; free physical = 35135 ; free virtual = 71396
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthIfftFtn' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/synthIfftFtn.v:6]
INFO: [Synth 8-6157] synthesizing module 'hsIfftPre_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/hsIfftPre_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'anon' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/anon.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_103' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_103.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_103' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_103.v:6]
INFO: [Synth 8-6155] done synthesizing module 'anon' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/anon.v:6]
INFO: [Synth 8-6155] done synthesizing module 'hsIfftPre_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/hsIfftPre_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'ifft_n512_sw64_factors_8_8_8_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ifft_n512_sw64_factors_8_8_8_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_104' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:6]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_0.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2365]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_1.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2374]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_2.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2383]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_3.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2392]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_4.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2401]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_5.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2410]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_6.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2419]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_7.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2428]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_8.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2437]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_9.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2446]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_10.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2455]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_11.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2464]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_12.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2473]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_13.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2482]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_14.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2491]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_15.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2500]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_16.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2509]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_17.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2518]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_18.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2527]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_19.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2536]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_20.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2545]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_21.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2554]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_22.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2563]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_23.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2572]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_24.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2581]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_25.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2590]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_26.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2599]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_27.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2608]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_28.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2617]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_29.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2626]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_30.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2635]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_31.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2644]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_32.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2653]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_33.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2662]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_34.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2671]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_35.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2680]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_36.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2689]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_37.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2698]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_38.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2707]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_39.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2716]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_40.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2725]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_41.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2734]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_42.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2743]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_43.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2752]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_44.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2761]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_45.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2770]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_46.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2779]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_47.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2788]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_48.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2797]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_49.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2806]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_50.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2815]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_51.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2824]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_52.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2833]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_53.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2842]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_54.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2851]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_55.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2860]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_56.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2869]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_57.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2878]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_58.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2887]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_59.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2896]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_60.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2905]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_61.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2914]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_62.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2923]
INFO: [Synth 8-3876] $readmem data file 'synthIfftFtn.v_toplevel_ifftCore_core_twiddleFactorROMs_63.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:2932]
INFO: [Synth 8-6157] synthesizing module 'matintrlv_r64_c8_w36_sw64_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/matintrlv_r64_c8_w36_sw64_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_91' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_91.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_91' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_91.v:6]
INFO: [Synth 8-6155] done synthesizing module 'matintrlv_r64_c8_w36_sw64_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/matintrlv_r64_c8_w36_sw64_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'matintrlv_r8_c64_w36_sw64_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/matintrlv_r8_c64_w36_sw64_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_92' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_92.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_92' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_92.v:6]
INFO: [Synth 8-6155] done synthesizing module 'matintrlv_r8_c64_w36_sw64_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/matintrlv_r8_c64_w36_sw64_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'ifft_n64_factors_8_8_scales_2_2_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ifft_n64_factors_8_8_scales_2_2_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_94' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_94.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_3' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_3.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_3' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_3.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_11' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_11.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_11' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_11.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_20' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_20.v:6]
INFO: [Synth 8-6157] synthesizing module 'ComplexMult' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:6]
INFO: [Synth 8-6155] done synthesizing module 'ComplexMult' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_20' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_20.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_21' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_21.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_21' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_21.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_22' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_22.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_22' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_22.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_23' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_23.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_23' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_23.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_24' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_24.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_24' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_24.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_25' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_25.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_25' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_25.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_26' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_26.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_26' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_26.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_31' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_31.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_31' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_31.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_32' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_32.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_32' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_32.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_33' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_33.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_33' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_33.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_34' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_34.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_34' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_34.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_38' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_38.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_38' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_38.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_40' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_40.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_40' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_40.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_41' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_41.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_41' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_41.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_42' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_42.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_42' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_42.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_47' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_47.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_47' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_47.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_48' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_48.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_48' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_48.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_49' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_49.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_49' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_49.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_50' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_50.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_50' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_50.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_56' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_56.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_56' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_56.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_57' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_57.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_57' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_57.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_58' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_58.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_58' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_58.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_65' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_65.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_65' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_65.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_66' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_66.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_66' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_66.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_74' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_74.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_74' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_74.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_94' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_94.v:6]
INFO: [Synth 8-6155] done synthesizing module 'ifft_n64_factors_8_8_scales_2_2_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ifft_n64_factors_8_8_scales_2_2_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'ifft_n8_factors_8_scales_1_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ifft_n8_factors_8_scales_1_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_95' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_95.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_95' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_95.v:6]
INFO: [Synth 8-6155] done synthesizing module 'ifft_n8_factors_8_scales_1_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ifft_n8_factors_8_scales_1_dut.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_104' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_104.v:6]
INFO: [Synth 8-6155] done synthesizing module 'ifft_n512_sw64_factors_8_8_8_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ifft_n512_sw64_factors_8_8_8_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'S2P_s64_p512_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/S2P_s64_p512_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_105' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_105.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_105' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_105.v:6]
INFO: [Synth 8-6155] done synthesizing module 'S2P_s64_p512_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/S2P_s64_p512_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'hsIfftPost_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/hsIfftPost_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'anon_1' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/anon_1.v:6]
INFO: [Synth 8-6155] done synthesizing module 'anon_1' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/anon_1.v:6]
INFO: [Synth 8-6155] done synthesizing module 'hsIfftPost_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/hsIfftPost_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'P2S_s132_p528_bl1_bw18_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/P2S_s132_p528_bl1_bw18_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_106' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_106.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_106' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_106.v:6]
INFO: [Synth 8-6155] done synthesizing module 'P2S_s132_p528_bl1_bw18_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/P2S_s132_p528_bl1_bw18_dut.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthIfftFtn' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/synthIfftFtn.v:6]
WARNING: [Synth 8-6014] Unused sequential element merged_512_real_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/anon.v:10314]
WARNING: [Synth 8-6014] Unused sequential element merged_512_imag_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/anon.v:10315]
WARNING: [Synth 8-6014] Unused sequential element merged_256_imag_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/anon.v:8446]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1401]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1402]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1403]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1404]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1405]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1406]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1407]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1408]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1412]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1413]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1414]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1415]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1416]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1417]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1418]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1419]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1423]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1424]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1425]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1426]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1427]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1428]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1429]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1430]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1434]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1435]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1436]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1437]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1438]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1439]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1440]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1441]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1445]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1446]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1447]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1448]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1449]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1450]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1451]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1452]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1456]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1457]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1458]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1459]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1460]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1461]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1462]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1463]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1467]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1468]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1469]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1470]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1471]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1472]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1473]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1474]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1489]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1490]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1491]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1492]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1493]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1494]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1495]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1496]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1500]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1501]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1502]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1503]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1504]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1505]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1506]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1507]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1511]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1512]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1513]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1514]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1515]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1516]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1517]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1518]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1522]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1523]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1524]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1525]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1526]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1527]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1528]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1529]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1533]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1534]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1535]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1536]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1537]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1538]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1539]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1540]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed.v:1544]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-7129] Port validIn in module unamed_106 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module anon_1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_105 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module ComplexMult is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_49 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_47 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_31 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_103 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module anon is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 5920.887 ; gain = 645.332 ; free physical = 36136 ; free virtual = 72403
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 5938.699 ; gain = 663.145 ; free physical = 36132 ; free virtual = 72398
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 5938.699 ; gain = 663.145 ; free physical = 36132 ; free virtual = 72398
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6020.129 ; gain = 0.000 ; free physical = 35906 ; free virtual = 72172
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6497.770 ; gain = 0.000 ; free physical = 34703 ; free virtual = 70970
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 6567.770 ; gain = 70.000 ; free physical = 33181 ; free virtual = 69447
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:46 ; elapsed = 00:00:39 . Memory (MB): peak = 6567.770 ; gain = 1292.215 ; free physical = 33801 ; free virtual = 70068
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:55 ; elapsed = 00:00:50 . Memory (MB): peak = 6567.770 ; gain = 1292.215 ; free physical = 32365 ; free virtual = 68638
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
3 Input 18 Bit Adders := 1462
2 Input 18 Bit Adders := 808
2 Input 3 Bit Adders := 12
2 Input 2 Bit Adders := 1
+---Registers :
288 Bit Registers := 72
36 Bit Registers := 1472
32 Bit Registers := 64
18 Bit Registers := 5567
16 Bit Registers := 648
3 Bit Registers := 36
1 Bit Registers := 281
+---RAMs :
4K Bit (16 X 288 bit) RAMs := 24
+---Muxes :
8 Input 288 Bit Muxes := 24
9 Input 32 Bit Muxes := 64
2 Input 18 Bit Muxes := 512
4 Input 18 Bit Muxes := 132
2 Input 3 Bit Muxes := 35
2 Input 2 Bit Muxes := 1
2 Input 1 Bit Muxes := 4
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-6904] The RAM "synthIfftFtn/rams_7_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthIfftFtn/rams_0_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_7_imag_5_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_3.v:179]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_7_real_15_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_3.v:181]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_7_imag_10_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_3.v:182]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_7_real_10_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_3.v:180]
DSP Report: Generating DSP _zz_ret_7_real_15_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_7_real_14_reg is absorbed into DSP _zz_ret_7_real_15_reg.
DSP Report: register _zz_ret_7_real_15_reg is absorbed into DSP _zz_ret_7_real_15_reg.
DSP Report: operator _zz_ret_7_real_150 is absorbed into DSP _zz_ret_7_real_15_reg.
DSP Report: Generating DSP _zz_ret_7_real_10_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_7_real_9_reg is absorbed into DSP _zz_ret_7_real_10_reg.
DSP Report: register _zz_ret_7_real_10_reg is absorbed into DSP _zz_ret_7_real_10_reg.
DSP Report: operator _zz_ret_7_real_100 is absorbed into DSP _zz_ret_7_real_10_reg.
DSP Report: Generating DSP _zz_ret_7_imag_10_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_7_imag_9_reg is absorbed into DSP _zz_ret_7_imag_10_reg.
DSP Report: register _zz_ret_7_imag_10_reg is absorbed into DSP _zz_ret_7_imag_10_reg.
DSP Report: operator _zz_ret_7_imag_100 is absorbed into DSP _zz_ret_7_imag_10_reg.
DSP Report: Generating DSP _zz_ret_7_imag_5_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_7_imag_4_reg is absorbed into DSP _zz_ret_7_imag_5_reg.
DSP Report: register _zz_ret_7_imag_5_reg is absorbed into DSP _zz_ret_7_imag_5_reg.
DSP Report: operator _zz_ret_7_imag_50 is absorbed into DSP _zz_ret_7_imag_5_reg.
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/_zz_ret_real_4_reg' and it is trimmed from '34' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_31.v:43]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/_zz_ret_imag_1_reg' and it is trimmed from '34' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/unamed_31.v:44]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_140/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_140/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_140/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:62]
INFO: [Common 17-14] Message 'Synth 8-3936' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
DSP Report: Generating DSP unamed_124/complexMult_108/mid_reg, operation Mode is: (((D:0x3fb1)'+(A:0x645)')*B'')'.
DSP Report: register unamed_124/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/arD1_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/mid_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_mid0 is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_124/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_124/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/aiD2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_124/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_124/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_125/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/arD1_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/mid_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_mid0 is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_125/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_125/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/aiD2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_125/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_125/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_126/complexMult_108/mid_reg, operation Mode is: (((D:0x3d3e)'+(A:0x1294)')*B'')'.
DSP Report: register unamed_126/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/arD1_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/mid_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_mid0 is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_126/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_126/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/aiD2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_126/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_126/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_127/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/arD1_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/mid_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_127/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_127/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_127/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_127/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_128/complexMult_108/mid_reg, operation Mode is: (((D:0x3871)'+(A:0x1e2b)')*B'')'.
DSP Report: register unamed_128/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/arD1_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/mid_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_mid0 is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_128/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_128/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/aiD2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_128/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_128/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_129/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/arD1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/mid_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_129/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_129/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/aiD2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_129/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_129/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/mid_reg, operation Mode is: (((D:0x3179)'+(A:0x2899)')*B'')'.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/arD1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/mid_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_130/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/aiD2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_130/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_132/complexMult_108/arD1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/mid_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_mid0 is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_132/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/aiD2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_132/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_133/complexMult_108/arD1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/mid_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_133/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/aiD2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_133/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_134/complexMult_108/arD1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/mid_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_134/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/aiD2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_134/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_135/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_135/_zz_ret_real_1_reg is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: register unamed_135/_zz_ret_real_reg is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: register unamed_135/_zz_ret_real_4_reg is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: register unamed_135/_zz_ret_real_3_reg is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: operator unamed_135/_zz_ret_real_40 is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: operator unamed_135/_zz_ret_real_30 is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_135/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_135/_zz_ret_real_1_reg is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: register unamed_135/_zz_ret_real_reg is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: register unamed_135/_zz_ret_imag_1_reg is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: register unamed_135/_zz_ret_imag_reg is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: operator unamed_135/_zz_ret_imag_10 is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: operator unamed_135/_zz_ret_imag0 is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_136/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_136/complexMult_108/arD1_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/mid_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_136/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_136/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_136/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_136/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_137/complexMult_108/arD1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/mid_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_137/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/aiD2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_137/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_138/complexMult_108/arD1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/mid_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_mid0 is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_138/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_138/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_140/complexMult_108/mid_reg, operation Mode is: (((D:0x3d3e)'+(A:0x1294)')*B'')'.
DSP Report: register unamed_140/complexMult_108/arD1_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_140/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_140/complexMult_108/mid_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_140/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_mid0 is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_140/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_140/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/aiD2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_140/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_140/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_141/complexMult_108/arD1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/mid_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_141/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/aiD2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_141/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/mid_reg, operation Mode is: (((D:0x3179)'+(A:0x2899)')*B'')'.
DSP Report: register unamed_142/complexMult_108/arD1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/mid_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_142/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/aiD2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_142/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_143/complexMult_108/arD1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/mid_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_143/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/aiD2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_143/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_144/complexMult_108/mid_reg, operation Mode is: (((D:0x3fb1)'+(A:0x645)')*B'')'.
DSP Report: register unamed_144/complexMult_108/arD1_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/mid_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_mid0 is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_144/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_144/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/aiD2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_144/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_144/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/mid_reg, operation Mode is: (((D:0xf384)'+(A:0x3ec5)')*B'')'.
DSP Report: register unamed_145/complexMult_108/arD1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/mid_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid0 is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_145/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_145/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/mid_reg, operation Mode is: (((D:0xe1d5)'+(A:0x3871)')*B'')'.
DSP Report: register unamed_146/complexMult_108/arD1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/mid_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_mid0 is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_146/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_146/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_148/complexMult_108/arD1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/mid_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_148/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_148/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_149/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_149/_zz_ret_real_1_reg is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: register unamed_149/_zz_ret_real_reg is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: register unamed_149/_zz_ret_real_4_reg is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: register unamed_149/_zz_ret_real_3_reg is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: operator unamed_149/_zz_ret_real_40 is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: operator unamed_149/_zz_ret_real_30 is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_149/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_149/_zz_ret_real_1_reg is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: register unamed_149/_zz_ret_real_reg is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: register unamed_149/_zz_ret_imag_1_reg is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: register unamed_149/_zz_ret_imag_reg is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: operator unamed_149/_zz_ret_imag_10 is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: operator unamed_149/_zz_ret_imag0 is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_150/complexMult_108/arD1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/mid_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_150/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/aiD2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_150/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_152/complexMult_108/mid_reg, operation Mode is: (((D:0xe783)'+(A:0x3b20)')*B'')'.
DSP Report: register unamed_152/complexMult_108/arD1_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/mid_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_mid0 is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_152/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_152/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_152/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_152/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_153/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_153/_zz_ret_real_1_reg is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: register unamed_153/_zz_ret_real_reg is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: register unamed_153/_zz_ret_real_4_reg is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: register unamed_153/_zz_ret_real_3_reg is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: operator unamed_153/_zz_ret_real_40 is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: operator unamed_153/_zz_ret_real_30 is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_153/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_153/_zz_ret_real_1_reg is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: register unamed_153/_zz_ret_real_reg is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: register unamed_153/_zz_ret_imag_1_reg is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: register unamed_153/_zz_ret_imag_reg is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: operator unamed_153/_zz_ret_imag_10 is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: operator unamed_153/_zz_ret_imag0 is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_154/complexMult_108/mid_reg, operation Mode is: (((D:0xc4e0)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_154/complexMult_108/arD1_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/mid_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_mid0 is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_154/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_154/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_154/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_154/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_156/complexMult_108/mid_reg, operation Mode is: (((D:0x3871)'+(A:0x1e2b)')*B'')'.
DSP Report: register unamed_156/complexMult_108/arD1_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_156/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_156/complexMult_108/mid_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_156/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_mid0 is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_156/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_156/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/aiD2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_156/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_156/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_157/complexMult_108/arD1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/mid_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_157/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_157/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_158/complexMult_108/mid_reg, operation Mode is: (((D:0x3fb1)'+(A:0x645)')*B'')'.
DSP Report: register unamed_158/complexMult_108/arD1_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_158/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_158/complexMult_108/mid_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_158/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_mid0 is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_158/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_158/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_158/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_158/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/mid_reg, operation Mode is: (((D:0xe783)'+(A:0x3b20)')*B'')'.
DSP Report: register unamed_159/complexMult_108/arD1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/mid_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_mid0 is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_159/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/aiD2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_159/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_160/complexMult_108/mid_reg, operation Mode is: (((D:0xce87)'+(A:0x2899)')*B'')'.
DSP Report: register unamed_160/complexMult_108/arD1_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/mid_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_mid0 is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_160/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_160/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_160/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_160/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/mid_reg, operation Mode is: (((D:0xc13b)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_161/complexMult_108/arD1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/mid_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_mid0 is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_161/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_161/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/mid_reg, operation Mode is: (((D:0xc2c2)'+(A:0xed6c)')*B'')'.
DSP Report: register unamed_162/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/arD1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/mid_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_mid0 is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_162/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/aiD2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_162/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_164/complexMult_108/arD1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/mid_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_164/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/aiD2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_164/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_165/complexMult_108/arD1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/mid_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_165/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/aiD2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_165/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/mid_reg, operation Mode is: (((D:0xf384)'+(A:0x3ec5)')*B'')'.
DSP Report: register unamed_166/complexMult_108/arD1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/mid_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid0 is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_166/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/aiD2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_166/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_167/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_167/_zz_ret_real_1_reg is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: register unamed_167/_zz_ret_real_reg is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: register unamed_167/_zz_ret_real_4_reg is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: register unamed_167/_zz_ret_real_3_reg is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: operator unamed_167/_zz_ret_real_40 is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: operator unamed_167/_zz_ret_real_30 is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_167/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_167/_zz_ret_real_1_reg is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: register unamed_167/_zz_ret_real_reg is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: register unamed_167/_zz_ret_imag_1_reg is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: register unamed_167/_zz_ret_imag_reg is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: operator unamed_167/_zz_ret_imag_10 is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: operator unamed_167/_zz_ret_imag0 is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_168/complexMult_108/mid_reg, operation Mode is: (((D:0xc13b)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_168/complexMult_108/arD1_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_168/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_168/complexMult_108/mid_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_168/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_mid0 is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_168/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_168/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/aiD2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_168/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_168/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/mid_reg, operation Mode is: (((D:0xc4e0)'+(A:0xe783)')*B'')'.
DSP Report: register unamed_169/complexMult_108/arD1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/mid_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_mid0 is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_169/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/aiD2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_169/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/mid_reg, operation Mode is: (((D:0xdc72)'+(A:0xcaca)')*B'')'.
DSP Report: register unamed_170/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/arD1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/mid_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_mid0 is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_170/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/aiD2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_170/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_172/complexMult_108/mid_reg, operation Mode is: (((D:0x3179)'+(A:0x2899)')*B'')'.
DSP Report: register unamed_172/complexMult_108/arD1_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_172/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_172/complexMult_108/mid_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_172/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_172/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_172/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/aiD2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_172/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_172/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_173/complexMult_108/arD1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/mid_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_mid0 is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_173/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_173/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/mid_reg, operation Mode is: (((D:0xe1d5)'+(A:0x3871)')*B'')'.
DSP Report: register unamed_174/complexMult_108/arD1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/mid_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_mid0 is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_174/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/aiD2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_174/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/mid_reg, operation Mode is: (((D:0xc4e0)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_175/complexMult_108/arD1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/mid_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_mid0 is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_175/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/aiD2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_175/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_176/complexMult_108/mid_reg, operation Mode is: (((D:0xc2c2)'+(A:0xed6c)')*B'')'.
DSP Report: register unamed_176/complexMult_108/arD1_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_176/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_176/complexMult_108/mid_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_176/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_mid0 is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_176/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_176/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/aiD2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_176/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_176/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/mid_reg, operation Mode is: (((D:0xdc72)'+(A:0xcaca)')*B'')'.
DSP Report: register unamed_177/complexMult_108/arD1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/mid_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_mid0 is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_177/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/aiD2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_177/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/mid_reg, operation Mode is: (((D:0x645)'+(A:0xc04f)')*B'')'.
DSP Report: register unamed_178/complexMult_108/arD1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/mid_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_mid0 is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_178/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/aiD2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_178/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
WARNING: [Synth 8-7129] Port validIn in module synthIfftFtn is either unconnected or has no load
INFO: [Synth 8-6904] The RAM "synthIfftFtn/rams_7_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthIfftFtn/rams_0_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
WARNING: [Synth 8-7129] Port validIn in module unamed_103 is either unconnected or has no load
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_3_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_4_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_5_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_6_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_1_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_2_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_3_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_4_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_5_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_6_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_1_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_2_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-4471] merging register 'complexMult_108/coeff_imag_delay_1_reg[15:0]' into 'complexMult_108/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_109/coeff_imag_delay_1_reg[15:0]' into 'complexMult_109/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_110/coeff_imag_delay_1_reg[15:0]' into 'complexMult_110/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_111/coeff_imag_delay_1_reg[15:0]' into 'complexMult_111/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_112/coeff_imag_delay_1_reg[15:0]' into 'complexMult_112/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_113/coeff_imag_delay_1_reg[15:0]' into 'complexMult_113/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_114/coeff_imag_delay_1_reg[15:0]' into 'complexMult_114/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_115/coeff_imag_delay_1_reg[15:0]' into 'complexMult_115/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_116/coeff_imag_delay_1_reg[15:0]' into 'complexMult_116/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_117/coeff_imag_delay_1_reg[15:0]' into 'complexMult_117/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_118/coeff_imag_delay_1_reg[15:0]' into 'complexMult_118/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_119/coeff_imag_delay_1_reg[15:0]' into 'complexMult_119/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_120/coeff_imag_delay_1_reg[15:0]' into 'complexMult_120/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_121/coeff_imag_delay_1_reg[15:0]' into 'complexMult_121/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_122/coeff_imag_delay_1_reg[15:0]' into 'complexMult_122/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_123/coeff_imag_delay_1_reg[15:0]' into 'complexMult_123/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_124/coeff_imag_delay_1_reg[15:0]' into 'complexMult_124/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_125/coeff_imag_delay_1_reg[15:0]' into 'complexMult_125/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_126/coeff_imag_delay_1_reg[15:0]' into 'complexMult_126/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_127/coeff_imag_delay_1_reg[15:0]' into 'complexMult_127/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_128/coeff_imag_delay_1_reg[15:0]' into 'complexMult_128/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_129/coeff_imag_delay_1_reg[15:0]' into 'complexMult_129/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_130/coeff_imag_delay_1_reg[15:0]' into 'complexMult_130/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_131/coeff_imag_delay_1_reg[15:0]' into 'complexMult_131/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_132/coeff_imag_delay_1_reg[15:0]' into 'complexMult_132/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_133/coeff_imag_delay_1_reg[15:0]' into 'complexMult_133/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_134/coeff_imag_delay_1_reg[15:0]' into 'complexMult_134/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_135/coeff_imag_delay_1_reg[15:0]' into 'complexMult_135/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_136/coeff_imag_delay_1_reg[15:0]' into 'complexMult_136/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_137/coeff_imag_delay_1_reg[15:0]' into 'complexMult_137/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_138/coeff_imag_delay_1_reg[15:0]' into 'complexMult_138/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_139/coeff_imag_delay_1_reg[15:0]' into 'complexMult_139/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_140/coeff_imag_delay_1_reg[15:0]' into 'complexMult_140/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_141/coeff_imag_delay_1_reg[15:0]' into 'complexMult_141/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_142/coeff_imag_delay_1_reg[15:0]' into 'complexMult_142/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_143/coeff_imag_delay_1_reg[15:0]' into 'complexMult_143/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_144/coeff_imag_delay_1_reg[15:0]' into 'complexMult_144/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_145/coeff_imag_delay_1_reg[15:0]' into 'complexMult_145/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_146/coeff_imag_delay_1_reg[15:0]' into 'complexMult_146/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_147/coeff_imag_delay_1_reg[15:0]' into 'complexMult_147/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_148/coeff_imag_delay_1_reg[15:0]' into 'complexMult_148/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_149/coeff_imag_delay_1_reg[15:0]' into 'complexMult_149/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_150/coeff_imag_delay_1_reg[15:0]' into 'complexMult_150/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_151/coeff_imag_delay_1_reg[15:0]' into 'complexMult_151/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_152/coeff_imag_delay_1_reg[15:0]' into 'complexMult_152/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_153/coeff_imag_delay_1_reg[15:0]' into 'complexMult_153/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_154/coeff_imag_delay_1_reg[15:0]' into 'complexMult_154/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_155/coeff_imag_delay_1_reg[15:0]' into 'complexMult_155/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_156/coeff_imag_delay_1_reg[15:0]' into 'complexMult_156/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_157/coeff_imag_delay_1_reg[15:0]' into 'complexMult_157/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_158/coeff_imag_delay_1_reg[15:0]' into 'complexMult_158/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_159/coeff_imag_delay_1_reg[15:0]' into 'complexMult_159/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_160/coeff_imag_delay_1_reg[15:0]' into 'complexMult_160/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_161/coeff_imag_delay_1_reg[15:0]' into 'complexMult_161/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_162/coeff_imag_delay_1_reg[15:0]' into 'complexMult_162/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_163/coeff_imag_delay_1_reg[15:0]' into 'complexMult_163/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_164/coeff_imag_delay_1_reg[15:0]' into 'complexMult_164/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_165/coeff_imag_delay_1_reg[15:0]' into 'complexMult_165/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_166/coeff_imag_delay_1_reg[15:0]' into 'complexMult_166/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_167/coeff_imag_delay_1_reg[15:0]' into 'complexMult_167/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_168/coeff_imag_delay_1_reg[15:0]' into 'complexMult_168/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_169/coeff_imag_delay_1_reg[15:0]' into 'complexMult_169/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_170/coeff_imag_delay_1_reg[15:0]' into 'complexMult_170/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_171/coeff_imag_delay_1_reg[15:0]' into 'complexMult_171/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_108/arD1_reg[17:0]' into 'complexMult_108/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_108/mid_delay_1_reg[34:0]' into 'complexMult_108/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_109/arD1_reg[17:0]' into 'complexMult_109/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_109/mid_delay_1_reg[34:0]' into 'complexMult_109/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_110/arD1_reg[17:0]' into 'complexMult_110/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_110/mid_delay_1_reg[34:0]' into 'complexMult_110/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_111/arD1_reg[17:0]' into 'complexMult_111/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_111/mid_delay_1_reg[34:0]' into 'complexMult_111/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_112/arD1_reg[17:0]' into 'complexMult_112/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_112/mid_delay_1_reg[34:0]' into 'complexMult_112/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_113/arD1_reg[17:0]' into 'complexMult_113/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_113/mid_delay_1_reg[34:0]' into 'complexMult_113/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_114/arD1_reg[17:0]' into 'complexMult_114/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_114/mid_delay_1_reg[34:0]' into 'complexMult_114/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_115/arD1_reg[17:0]' into 'complexMult_115/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_115/mid_delay_1_reg[34:0]' into 'complexMult_115/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_116/arD1_reg[17:0]' into 'complexMult_116/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_116/mid_delay_1_reg[34:0]' into 'complexMult_116/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_117/arD1_reg[17:0]' into 'complexMult_117/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_117/mid_delay_1_reg[34:0]' into 'complexMult_117/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_118/arD1_reg[17:0]' into 'complexMult_118/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_118/mid_delay_1_reg[34:0]' into 'complexMult_118/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_119/arD1_reg[17:0]' into 'complexMult_119/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_119/mid_delay_1_reg[34:0]' into 'complexMult_119/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_120/arD1_reg[17:0]' into 'complexMult_120/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_120/mid_delay_1_reg[34:0]' into 'complexMult_120/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_121/arD1_reg[17:0]' into 'complexMult_121/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_121/mid_delay_1_reg[34:0]' into 'complexMult_121/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_122/arD1_reg[17:0]' into 'complexMult_122/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_122/mid_delay_1_reg[34:0]' into 'complexMult_122/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_123/arD1_reg[17:0]' into 'complexMult_123/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_123/mid_delay_1_reg[34:0]' into 'complexMult_123/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_124/arD1_reg[17:0]' into 'complexMult_124/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_124/mid_delay_1_reg[34:0]' into 'complexMult_124/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_125/arD1_reg[17:0]' into 'complexMult_125/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_125/mid_delay_1_reg[34:0]' into 'complexMult_125/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/ComplexMult.v:79]
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3936' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
DSP Report: Generating DSP complexMult_108/mid_reg, operation Mode is: ((D'+(A:0x4000)'')*B'')'.
DSP Report: register complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/arD1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/data_real_delay_2_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_0_port0_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/coeff_real_delay_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/mid_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/_zz_mid_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/_zz_mid_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: operator complexMult_108/_zz_mid_10 is absorbed into DSP complexMult_108/mid_reg.
DSP Report: operator complexMult_108/_zz_mid0 is absorbed into DSP complexMult_108/mid_reg.
DSP Report: Generating DSP complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_108/biD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/biD2_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/data_real_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/arD1_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/mid_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/aiD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real_20 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real_10 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real0 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_108/aiD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/mid_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/brD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/brD2_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/arD1_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag_20 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag_10 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag0 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_109/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_109/coeff_imag_delay_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/arD1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/data_real_delay_2_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_1_port0_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/coeff_real_delay_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/mid_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/_zz_mid_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/_zz_mid_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: operator complexMult_109/_zz_mid_10 is absorbed into DSP complexMult_109/mid_reg.
DSP Report: operator complexMult_109/_zz_mid0 is absorbed into DSP complexMult_109/mid_reg.
DSP Report: Generating DSP complexMult_109/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_109/biD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/biD2_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/data_real_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/arD1_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/mid_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/aiD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real_20 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real_10 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real0 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_109/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_109/aiD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/mid_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/brD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/brD2_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/arD1_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag_20 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag_10 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag0 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_110/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_110/coeff_imag_delay_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/arD1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/data_real_delay_2_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_2_port0_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/coeff_real_delay_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/mid_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/_zz_mid_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/_zz_mid_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: operator complexMult_110/_zz_mid_10 is absorbed into DSP complexMult_110/mid_reg.
DSP Report: operator complexMult_110/_zz_mid0 is absorbed into DSP complexMult_110/mid_reg.
DSP Report: Generating DSP complexMult_110/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_110/biD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/biD2_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/data_real_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/arD1_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/mid_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/aiD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real_20 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real_10 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real0 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_110/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_110/aiD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/mid_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/brD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/brD2_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/arD1_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag_20 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag_10 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag0 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_111/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_111/coeff_imag_delay_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/arD1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/data_real_delay_2_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_3_port0_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/coeff_real_delay_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/mid_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/_zz_mid_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/_zz_mid_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: operator complexMult_111/_zz_mid_10 is absorbed into DSP complexMult_111/mid_reg.
DSP Report: operator complexMult_111/_zz_mid0 is absorbed into DSP complexMult_111/mid_reg.
DSP Report: Generating DSP complexMult_111/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_111/biD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/biD2_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/data_real_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/arD1_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/mid_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/aiD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real_20 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real_10 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real0 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_111/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_111/aiD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/mid_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/brD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/brD2_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/arD1_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag_20 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag_10 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag0 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_112/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_112/coeff_imag_delay_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/arD1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/data_real_delay_2_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_4_port0_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/coeff_real_delay_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/mid_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/_zz_mid_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/_zz_mid_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: operator complexMult_112/_zz_mid_10 is absorbed into DSP complexMult_112/mid_reg.
DSP Report: operator complexMult_112/_zz_mid0 is absorbed into DSP complexMult_112/mid_reg.
DSP Report: Generating DSP complexMult_112/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_112/biD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/biD2_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/data_real_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/arD1_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/mid_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/aiD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real_20 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real_10 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real0 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_112/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_112/aiD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/mid_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/brD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/brD2_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/arD1_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag_20 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag_10 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag0 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_113/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_113/coeff_imag_delay_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/arD1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/data_real_delay_2_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_5_port0_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/coeff_real_delay_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/mid_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/_zz_mid_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/_zz_mid_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: operator complexMult_113/_zz_mid_10 is absorbed into DSP complexMult_113/mid_reg.
DSP Report: operator complexMult_113/_zz_mid0 is absorbed into DSP complexMult_113/mid_reg.
DSP Report: Generating DSP complexMult_113/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_113/biD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/biD2_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/data_real_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/arD1_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/mid_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/aiD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real_20 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real_10 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real0 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_113/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_113/aiD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/mid_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/brD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/brD2_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/arD1_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag_20 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag_10 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag0 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_114/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_114/coeff_imag_delay_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/arD1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/data_real_delay_2_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_6_port0_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/coeff_real_delay_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/mid_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/_zz_mid_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/_zz_mid_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: operator complexMult_114/_zz_mid_10 is absorbed into DSP complexMult_114/mid_reg.
DSP Report: operator complexMult_114/_zz_mid0 is absorbed into DSP complexMult_114/mid_reg.
DSP Report: Generating DSP complexMult_114/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_114/biD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/biD2_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/data_real_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/arD1_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/mid_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/aiD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real_20 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real_10 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real0 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_114/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_114/aiD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/mid_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/brD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/brD2_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/arD1_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag_20 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag_10 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag0 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_115/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_115/coeff_imag_delay_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/arD1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/data_real_delay_2_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_7_port0_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/coeff_real_delay_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/mid_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/_zz_mid_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/_zz_mid_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: operator complexMult_115/_zz_mid_10 is absorbed into DSP complexMult_115/mid_reg.
DSP Report: operator complexMult_115/_zz_mid0 is absorbed into DSP complexMult_115/mid_reg.
DSP Report: Generating DSP complexMult_115/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_115/biD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/biD2_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/data_real_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/arD1_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/mid_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/aiD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real_20 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real_10 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real0 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_115/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_115/aiD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/mid_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/brD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/brD2_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/arD1_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag_20 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag_10 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag0 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_116/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_116/coeff_imag_delay_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/arD1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/data_real_delay_2_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_8_port0_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/coeff_real_delay_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/mid_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/_zz_mid_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/_zz_mid_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: operator complexMult_116/_zz_mid_10 is absorbed into DSP complexMult_116/mid_reg.
DSP Report: operator complexMult_116/_zz_mid0 is absorbed into DSP complexMult_116/mid_reg.
DSP Report: Generating DSP complexMult_116/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_116/biD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/biD2_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/data_real_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/arD1_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/mid_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/aiD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real_20 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real_10 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real0 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_116/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_116/aiD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/mid_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/brD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/brD2_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/arD1_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag_20 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag_10 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag0 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_117/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_117/coeff_imag_delay_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/arD1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/data_real_delay_2_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_9_port0_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/coeff_real_delay_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/mid_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/_zz_mid_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/_zz_mid_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: operator complexMult_117/_zz_mid_10 is absorbed into DSP complexMult_117/mid_reg.
DSP Report: operator complexMult_117/_zz_mid0 is absorbed into DSP complexMult_117/mid_reg.
DSP Report: Generating DSP complexMult_117/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_117/biD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/biD2_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/data_real_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/arD1_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/mid_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/aiD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real_20 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real_10 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real0 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_117/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_117/aiD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/mid_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/brD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/brD2_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/arD1_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag_20 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag_10 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag0 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_118/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_118/coeff_imag_delay_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/arD1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/data_real_delay_2_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_10_port0_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/coeff_real_delay_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/mid_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/_zz_mid_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/_zz_mid_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: operator complexMult_118/_zz_mid_10 is absorbed into DSP complexMult_118/mid_reg.
DSP Report: operator complexMult_118/_zz_mid0 is absorbed into DSP complexMult_118/mid_reg.
DSP Report: Generating DSP complexMult_118/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_118/biD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/biD2_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/data_real_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/arD1_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/mid_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/aiD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real_20 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real_10 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real0 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_118/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_118/aiD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/mid_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/brD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/brD2_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/arD1_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag_20 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag_10 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag0 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_119/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_119/coeff_imag_delay_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/arD1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/data_real_delay_2_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_11_port0_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/coeff_real_delay_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/mid_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/_zz_mid_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/_zz_mid_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: operator complexMult_119/_zz_mid_10 is absorbed into DSP complexMult_119/mid_reg.
DSP Report: operator complexMult_119/_zz_mid0 is absorbed into DSP complexMult_119/mid_reg.
DSP Report: Generating DSP complexMult_119/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_119/biD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/biD2_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/data_real_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/arD1_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/mid_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/aiD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real_20 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real_10 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real0 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_119/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_119/aiD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/mid_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/brD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/brD2_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/arD1_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag_20 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag_10 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag0 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_120/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_120/coeff_imag_delay_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/arD1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/data_real_delay_2_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_12_port0_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/coeff_real_delay_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/mid_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/_zz_mid_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/_zz_mid_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: operator complexMult_120/_zz_mid_10 is absorbed into DSP complexMult_120/mid_reg.
DSP Report: operator complexMult_120/_zz_mid0 is absorbed into DSP complexMult_120/mid_reg.
DSP Report: Generating DSP complexMult_120/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_120/biD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/biD2_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/data_real_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/arD1_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/mid_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/aiD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real_20 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real_10 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real0 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_120/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_120/aiD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/mid_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/brD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/brD2_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/arD1_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag_20 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag_10 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag0 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_121/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_121/coeff_imag_delay_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/arD1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/data_real_delay_2_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_13_port0_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/coeff_real_delay_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/mid_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/_zz_mid_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/_zz_mid_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: operator complexMult_121/_zz_mid_10 is absorbed into DSP complexMult_121/mid_reg.
DSP Report: operator complexMult_121/_zz_mid0 is absorbed into DSP complexMult_121/mid_reg.
DSP Report: Generating DSP complexMult_121/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_121/biD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/biD2_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/data_real_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/arD1_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/mid_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/aiD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real_20 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real_10 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real0 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_121/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_121/aiD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/mid_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/brD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/brD2_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/arD1_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag_20 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag_10 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag0 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_122/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_122/coeff_imag_delay_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/arD1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/data_real_delay_2_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_14_port0_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/coeff_real_delay_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/mid_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/_zz_mid_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/_zz_mid_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: operator complexMult_122/_zz_mid_10 is absorbed into DSP complexMult_122/mid_reg.
DSP Report: operator complexMult_122/_zz_mid0 is absorbed into DSP complexMult_122/mid_reg.
DSP Report: Generating DSP complexMult_122/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_122/biD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/biD2_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/data_real_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/arD1_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/mid_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/aiD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real_20 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real_10 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real0 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_122/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_122/aiD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/mid_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/brD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/brD2_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/arD1_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag_20 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag_10 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag0 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_123/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_123/coeff_imag_delay_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/arD1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/data_real_delay_2_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_15_port0_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/coeff_real_delay_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/mid_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/_zz_mid_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/_zz_mid_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: operator complexMult_123/_zz_mid_10 is absorbed into DSP complexMult_123/mid_reg.
DSP Report: operator complexMult_123/_zz_mid0 is absorbed into DSP complexMult_123/mid_reg.
DSP Report: Generating DSP complexMult_123/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_123/biD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/biD2_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/data_real_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/arD1_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/mid_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/aiD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real_20 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real_10 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real0 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_123/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_123/aiD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/mid_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/brD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/brD2_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/arD1_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag_20 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag_10 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag0 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_124/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_124/coeff_imag_delay_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/arD1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/data_real_delay_2_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_16_port0_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/coeff_real_delay_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/mid_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/_zz_mid_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/_zz_mid_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: operator complexMult_124/_zz_mid_10 is absorbed into DSP complexMult_124/mid_reg.
DSP Report: operator complexMult_124/_zz_mid0 is absorbed into DSP complexMult_124/mid_reg.
DSP Report: Generating DSP complexMult_124/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_124/biD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/biD2_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/data_real_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/arD1_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/mid_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/aiD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real_20 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real_10 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real0 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_124/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_124/aiD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/mid_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/brD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/brD2_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/arD1_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag_20 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag_10 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag0 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_125/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_125/coeff_imag_delay_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/arD1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/data_real_delay_2_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_17_port0_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/coeff_real_delay_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/mid_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/_zz_mid_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/_zz_mid_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: operator complexMult_125/_zz_mid_10 is absorbed into DSP complexMult_125/mid_reg.
DSP Report: operator complexMult_125/_zz_mid0 is absorbed into DSP complexMult_125/mid_reg.
DSP Report: Generating DSP complexMult_125/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_125/biD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/biD2_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/data_real_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/arD1_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/mid_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/aiD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real_20 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real_10 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real0 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_125/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_125/aiD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/mid_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/brD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/brD2_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/arD1_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag_20 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag_10 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag0 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_126/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_126/coeff_imag_delay_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/arD1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/data_real_delay_2_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_18_port0_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/coeff_real_delay_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/mid_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/_zz_mid_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/_zz_mid_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: operator complexMult_126/_zz_mid_10 is absorbed into DSP complexMult_126/mid_reg.
DSP Report: operator complexMult_126/_zz_mid0 is absorbed into DSP complexMult_126/mid_reg.
DSP Report: Generating DSP complexMult_126/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_126/biD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/biD2_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/data_real_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/arD1_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/mid_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/aiD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real_20 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real_10 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real0 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_126/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_126/aiD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/mid_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/brD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/brD2_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/arD1_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag_20 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag_10 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag0 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_127/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_127/coeff_imag_delay_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/arD1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/data_real_delay_2_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_19_port0_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/coeff_real_delay_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/mid_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/_zz_mid_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/_zz_mid_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: operator complexMult_127/_zz_mid_10 is absorbed into DSP complexMult_127/mid_reg.
DSP Report: operator complexMult_127/_zz_mid0 is absorbed into DSP complexMult_127/mid_reg.
DSP Report: Generating DSP complexMult_127/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_127/biD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/biD2_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/data_real_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/arD1_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/mid_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/aiD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real_20 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real_10 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real0 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_127/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_127/aiD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/mid_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/brD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/brD2_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/arD1_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag_20 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag_10 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag0 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_128/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_128/coeff_imag_delay_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/arD1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/data_real_delay_2_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_20_port0_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/coeff_real_delay_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/mid_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/_zz_mid_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/_zz_mid_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: operator complexMult_128/_zz_mid_10 is absorbed into DSP complexMult_128/mid_reg.
DSP Report: operator complexMult_128/_zz_mid0 is absorbed into DSP complexMult_128/mid_reg.
DSP Report: Generating DSP complexMult_128/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_128/biD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/biD2_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/data_real_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/arD1_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/mid_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/aiD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real_20 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real_10 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real0 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_128/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_128/aiD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/mid_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/brD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/brD2_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/arD1_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag_20 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag_10 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag0 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_129/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_129/coeff_imag_delay_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/arD1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/data_real_delay_2_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_21_port0_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/coeff_real_delay_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/mid_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/_zz_mid_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/_zz_mid_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: operator complexMult_129/_zz_mid_10 is absorbed into DSP complexMult_129/mid_reg.
DSP Report: operator complexMult_129/_zz_mid0 is absorbed into DSP complexMult_129/mid_reg.
DSP Report: Generating DSP complexMult_129/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_129/biD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/biD2_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/data_real_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/arD1_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/mid_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/aiD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real_20 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real_10 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real0 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_129/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_129/aiD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/mid_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/brD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/brD2_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/arD1_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag_20 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag_10 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag0 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_130/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_130/coeff_imag_delay_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/arD1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/data_real_delay_2_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_22_port0_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/coeff_real_delay_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/mid_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/_zz_mid_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/_zz_mid_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: operator complexMult_130/_zz_mid_10 is absorbed into DSP complexMult_130/mid_reg.
DSP Report: operator complexMult_130/_zz_mid0 is absorbed into DSP complexMult_130/mid_reg.
DSP Report: Generating DSP complexMult_130/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_130/biD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/biD2_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/data_real_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/arD1_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/mid_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/aiD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real_20 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real_10 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real0 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_130/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_130/aiD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/mid_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/brD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/brD2_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/arD1_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag_20 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag_10 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag0 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_131/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_131/coeff_imag_delay_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/arD1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/data_real_delay_2_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_23_port0_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/coeff_real_delay_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/mid_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/_zz_mid_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/_zz_mid_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: operator complexMult_131/_zz_mid_10 is absorbed into DSP complexMult_131/mid_reg.
DSP Report: operator complexMult_131/_zz_mid0 is absorbed into DSP complexMult_131/mid_reg.
DSP Report: Generating DSP complexMult_131/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_131/biD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/biD2_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/data_real_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/arD1_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/mid_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/aiD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real_20 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real_10 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real0 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_131/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_131/aiD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/mid_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/brD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/brD2_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/arD1_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag_20 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag_10 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag0 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_132/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_132/coeff_imag_delay_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/arD1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/data_real_delay_2_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_24_port0_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/coeff_real_delay_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/mid_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/_zz_mid_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/_zz_mid_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: operator complexMult_132/_zz_mid_10 is absorbed into DSP complexMult_132/mid_reg.
DSP Report: operator complexMult_132/_zz_mid0 is absorbed into DSP complexMult_132/mid_reg.
DSP Report: Generating DSP complexMult_132/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_132/biD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/biD2_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/data_real_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/arD1_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/mid_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/aiD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real_20 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real_10 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real0 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_132/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_132/aiD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/mid_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/brD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/brD2_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/arD1_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag_20 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag_10 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag0 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_133/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_133/coeff_imag_delay_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/arD1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/data_real_delay_2_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_25_port0_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/coeff_real_delay_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/mid_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/_zz_mid_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/_zz_mid_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: operator complexMult_133/_zz_mid_10 is absorbed into DSP complexMult_133/mid_reg.
DSP Report: operator complexMult_133/_zz_mid0 is absorbed into DSP complexMult_133/mid_reg.
DSP Report: Generating DSP complexMult_133/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_133/biD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/biD2_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/data_real_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/arD1_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/mid_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/aiD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real_20 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real_10 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real0 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_133/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_133/aiD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/mid_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/brD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/brD2_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/arD1_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag_20 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag_10 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag0 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_134/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_134/coeff_imag_delay_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/arD1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/data_real_delay_2_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_26_port0_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/coeff_real_delay_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/mid_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/_zz_mid_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/_zz_mid_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: operator complexMult_134/_zz_mid_10 is absorbed into DSP complexMult_134/mid_reg.
DSP Report: operator complexMult_134/_zz_mid0 is absorbed into DSP complexMult_134/mid_reg.
DSP Report: Generating DSP complexMult_134/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_134/biD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/biD2_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/data_real_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/arD1_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/mid_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/aiD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real_20 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real_10 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real0 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_134/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_134/aiD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/mid_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/brD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/brD2_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/arD1_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag_20 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag_10 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag0 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_135/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_135/coeff_imag_delay_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/arD1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/data_real_delay_2_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_27_port0_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/coeff_real_delay_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/mid_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/_zz_mid_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/_zz_mid_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: operator complexMult_135/_zz_mid_10 is absorbed into DSP complexMult_135/mid_reg.
DSP Report: operator complexMult_135/_zz_mid0 is absorbed into DSP complexMult_135/mid_reg.
DSP Report: Generating DSP complexMult_135/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_135/biD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/biD2_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/data_real_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/arD1_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/mid_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/aiD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real_20 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real_10 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real0 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_135/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_135/aiD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/mid_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/brD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/brD2_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/arD1_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag_20 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag_10 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag0 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_136/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_136/coeff_imag_delay_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/arD1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/data_real_delay_2_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_28_port0_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/coeff_real_delay_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/mid_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/_zz_mid_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/_zz_mid_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: operator complexMult_136/_zz_mid_10 is absorbed into DSP complexMult_136/mid_reg.
DSP Report: operator complexMult_136/_zz_mid0 is absorbed into DSP complexMult_136/mid_reg.
DSP Report: Generating DSP complexMult_136/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_136/biD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/biD2_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/data_real_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/arD1_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/mid_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/aiD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real_20 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real_10 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real0 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_136/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_136/aiD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/mid_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/brD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/brD2_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/arD1_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag_20 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag_10 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag0 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_137/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_137/coeff_imag_delay_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/arD1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/data_real_delay_2_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_29_port0_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/coeff_real_delay_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/mid_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/_zz_mid_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/_zz_mid_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: operator complexMult_137/_zz_mid_10 is absorbed into DSP complexMult_137/mid_reg.
DSP Report: operator complexMult_137/_zz_mid0 is absorbed into DSP complexMult_137/mid_reg.
DSP Report: Generating DSP complexMult_137/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_137/biD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/biD2_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/data_real_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/arD1_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/mid_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/aiD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real_20 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real_10 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real0 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_137/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_137/aiD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/mid_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/brD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/brD2_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/arD1_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag_20 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag_10 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag0 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_138/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_138/coeff_imag_delay_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/arD1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/data_real_delay_2_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_30_port0_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/coeff_real_delay_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/mid_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/_zz_mid_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/_zz_mid_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: operator complexMult_138/_zz_mid_10 is absorbed into DSP complexMult_138/mid_reg.
DSP Report: operator complexMult_138/_zz_mid0 is absorbed into DSP complexMult_138/mid_reg.
DSP Report: Generating DSP complexMult_138/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_138/biD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/biD2_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/data_real_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/arD1_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/mid_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/aiD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real_20 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real_10 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real0 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_138/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_138/aiD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/mid_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/brD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/brD2_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/arD1_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag_20 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag_10 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag0 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_139/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_139/coeff_imag_delay_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/arD1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/data_real_delay_2_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_31_port0_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/coeff_real_delay_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/mid_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/_zz_mid_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/_zz_mid_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: operator complexMult_139/_zz_mid_10 is absorbed into DSP complexMult_139/mid_reg.
DSP Report: operator complexMult_139/_zz_mid0 is absorbed into DSP complexMult_139/mid_reg.
DSP Report: Generating DSP complexMult_139/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_139/biD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/biD2_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/data_real_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/arD1_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/mid_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/aiD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real_20 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real_10 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real0 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_139/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_139/aiD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/mid_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/brD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/brD2_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/arD1_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag_20 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag_10 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag0 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_140/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_140/coeff_imag_delay_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/arD1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/data_real_delay_2_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_32_port0_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/coeff_real_delay_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/mid_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/_zz_mid_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/_zz_mid_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: operator complexMult_140/_zz_mid_10 is absorbed into DSP complexMult_140/mid_reg.
DSP Report: operator complexMult_140/_zz_mid0 is absorbed into DSP complexMult_140/mid_reg.
DSP Report: Generating DSP complexMult_140/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_140/biD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/biD2_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/data_real_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/arD1_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/mid_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/aiD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real_20 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real_10 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real0 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_140/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_140/aiD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/mid_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/brD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/brD2_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/arD1_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag_20 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag_10 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag0 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_141/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_141/coeff_imag_delay_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/arD1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/data_real_delay_2_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_33_port0_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/coeff_real_delay_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/mid_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/_zz_mid_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/_zz_mid_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: operator complexMult_141/_zz_mid_10 is absorbed into DSP complexMult_141/mid_reg.
DSP Report: operator complexMult_141/_zz_mid0 is absorbed into DSP complexMult_141/mid_reg.
DSP Report: Generating DSP complexMult_141/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_141/biD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/biD2_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/data_real_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/arD1_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/mid_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/aiD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real_20 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real_10 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real0 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_141/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_141/aiD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/mid_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/brD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/brD2_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/arD1_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag_20 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag_10 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag0 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_142/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_142/coeff_imag_delay_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/arD1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/data_real_delay_2_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_34_port0_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/coeff_real_delay_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/mid_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/_zz_mid_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/_zz_mid_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: operator complexMult_142/_zz_mid_10 is absorbed into DSP complexMult_142/mid_reg.
DSP Report: operator complexMult_142/_zz_mid0 is absorbed into DSP complexMult_142/mid_reg.
DSP Report: Generating DSP complexMult_142/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_142/biD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/biD2_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/data_real_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/arD1_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/mid_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/aiD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real_20 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real_10 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real0 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_142/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_142/aiD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/mid_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/brD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/brD2_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/arD1_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag_20 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag_10 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag0 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_143/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_143/coeff_imag_delay_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/arD1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/data_real_delay_2_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_35_port0_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/coeff_real_delay_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/mid_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/_zz_mid_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/_zz_mid_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: operator complexMult_143/_zz_mid_10 is absorbed into DSP complexMult_143/mid_reg.
DSP Report: operator complexMult_143/_zz_mid0 is absorbed into DSP complexMult_143/mid_reg.
DSP Report: Generating DSP complexMult_143/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_143/biD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/biD2_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/data_real_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/arD1_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/mid_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/aiD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real_20 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real_10 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real0 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_143/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_143/aiD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/mid_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/brD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/brD2_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/arD1_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag_20 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag_10 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag0 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_144/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_144/coeff_imag_delay_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/arD1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/data_real_delay_2_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_36_port0_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/coeff_real_delay_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/mid_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/_zz_mid_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/_zz_mid_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: operator complexMult_144/_zz_mid_10 is absorbed into DSP complexMult_144/mid_reg.
DSP Report: operator complexMult_144/_zz_mid0 is absorbed into DSP complexMult_144/mid_reg.
DSP Report: Generating DSP complexMult_144/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_144/biD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/biD2_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/data_real_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/arD1_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/mid_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/aiD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real_20 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real_10 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real0 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_144/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_144/aiD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/mid_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/brD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/brD2_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/arD1_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag_20 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag_10 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag0 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_145/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_145/coeff_imag_delay_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/arD1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/data_real_delay_2_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_37_port0_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/coeff_real_delay_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/mid_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/_zz_mid_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/_zz_mid_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: operator complexMult_145/_zz_mid_10 is absorbed into DSP complexMult_145/mid_reg.
DSP Report: operator complexMult_145/_zz_mid0 is absorbed into DSP complexMult_145/mid_reg.
DSP Report: Generating DSP complexMult_145/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_145/biD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/biD2_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/data_real_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/arD1_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/mid_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/aiD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real_20 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real_10 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real0 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_145/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_145/aiD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/mid_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/brD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/brD2_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/arD1_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag_20 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag_10 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag0 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_146/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_146/coeff_imag_delay_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/arD1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/data_real_delay_2_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_38_port0_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/coeff_real_delay_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/mid_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/_zz_mid_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/_zz_mid_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: operator complexMult_146/_zz_mid_10 is absorbed into DSP complexMult_146/mid_reg.
DSP Report: operator complexMult_146/_zz_mid0 is absorbed into DSP complexMult_146/mid_reg.
DSP Report: Generating DSP complexMult_146/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_146/biD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/biD2_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/data_real_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/arD1_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/mid_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/aiD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real_20 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real_10 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real0 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_146/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_146/aiD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/mid_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/brD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/brD2_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/arD1_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag_20 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag_10 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag0 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_147/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_147/coeff_imag_delay_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/arD1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/data_real_delay_2_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_39_port0_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/coeff_real_delay_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/mid_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/_zz_mid_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/_zz_mid_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: operator complexMult_147/_zz_mid_10 is absorbed into DSP complexMult_147/mid_reg.
DSP Report: operator complexMult_147/_zz_mid0 is absorbed into DSP complexMult_147/mid_reg.
DSP Report: Generating DSP complexMult_147/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_147/biD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/biD2_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/data_real_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/arD1_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/mid_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/aiD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real_20 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real_10 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real0 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_147/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_147/aiD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/mid_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/brD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/brD2_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/arD1_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag_20 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag_10 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag0 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_148/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_148/coeff_imag_delay_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/arD1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/data_real_delay_2_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_40_port0_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/coeff_real_delay_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/mid_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/_zz_mid_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/_zz_mid_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: operator complexMult_148/_zz_mid_10 is absorbed into DSP complexMult_148/mid_reg.
DSP Report: operator complexMult_148/_zz_mid0 is absorbed into DSP complexMult_148/mid_reg.
DSP Report: Generating DSP complexMult_148/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_148/biD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/biD2_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/data_real_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/arD1_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/mid_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/aiD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real_20 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real_10 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real0 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_148/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_148/aiD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/mid_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/brD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/brD2_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/arD1_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag_20 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag_10 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag0 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_149/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_149/coeff_imag_delay_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/arD1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/data_real_delay_2_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_41_port0_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/coeff_real_delay_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/mid_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/_zz_mid_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/_zz_mid_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: operator complexMult_149/_zz_mid_10 is absorbed into DSP complexMult_149/mid_reg.
DSP Report: operator complexMult_149/_zz_mid0 is absorbed into DSP complexMult_149/mid_reg.
DSP Report: Generating DSP complexMult_149/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_149/biD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/biD2_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/data_real_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/arD1_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/mid_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/aiD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real_20 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real_10 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real0 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_149/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_149/aiD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/mid_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/brD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/brD2_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/arD1_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag_20 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag_10 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag0 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_150/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_150/coeff_imag_delay_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/arD1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/data_real_delay_2_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_42_port0_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/coeff_real_delay_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/mid_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/_zz_mid_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/_zz_mid_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: operator complexMult_150/_zz_mid_10 is absorbed into DSP complexMult_150/mid_reg.
DSP Report: operator complexMult_150/_zz_mid0 is absorbed into DSP complexMult_150/mid_reg.
DSP Report: Generating DSP complexMult_150/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_150/biD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/biD2_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/data_real_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/arD1_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/mid_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/aiD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real_20 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real_10 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real0 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_150/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_150/aiD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/mid_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/brD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/brD2_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/arD1_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag_20 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag_10 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag0 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_151/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_151/coeff_imag_delay_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/arD1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/data_real_delay_2_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_43_port0_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/coeff_real_delay_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/mid_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/_zz_mid_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/_zz_mid_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: operator complexMult_151/_zz_mid_10 is absorbed into DSP complexMult_151/mid_reg.
DSP Report: operator complexMult_151/_zz_mid0 is absorbed into DSP complexMult_151/mid_reg.
DSP Report: Generating DSP complexMult_151/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_151/biD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/biD2_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/data_real_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/arD1_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/mid_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/aiD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real_20 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real_10 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real0 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_151/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_151/aiD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/mid_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/brD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/brD2_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/arD1_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag_20 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag_10 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag0 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_152/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_152/coeff_imag_delay_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/arD1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/data_real_delay_2_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_44_port0_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/coeff_real_delay_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/mid_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/_zz_mid_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/_zz_mid_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: operator complexMult_152/_zz_mid_10 is absorbed into DSP complexMult_152/mid_reg.
DSP Report: operator complexMult_152/_zz_mid0 is absorbed into DSP complexMult_152/mid_reg.
DSP Report: Generating DSP complexMult_152/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_152/biD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/biD2_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/data_real_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/arD1_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/mid_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/aiD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real_20 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real_10 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real0 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_152/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_152/aiD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/mid_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/brD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/brD2_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/arD1_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag_20 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag_10 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag0 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_153/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_153/coeff_imag_delay_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/arD1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/data_real_delay_2_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_45_port0_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/coeff_real_delay_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/mid_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/_zz_mid_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/_zz_mid_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: operator complexMult_153/_zz_mid_10 is absorbed into DSP complexMult_153/mid_reg.
DSP Report: operator complexMult_153/_zz_mid0 is absorbed into DSP complexMult_153/mid_reg.
DSP Report: Generating DSP complexMult_153/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_153/biD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/biD2_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/data_real_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/arD1_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/mid_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/aiD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real_20 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real_10 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real0 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_153/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_153/aiD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/mid_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/brD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/brD2_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/arD1_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag_20 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag_10 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag0 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_154/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_154/coeff_imag_delay_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/arD1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/data_real_delay_2_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_46_port0_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/coeff_real_delay_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/mid_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/_zz_mid_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/_zz_mid_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: operator complexMult_154/_zz_mid_10 is absorbed into DSP complexMult_154/mid_reg.
DSP Report: operator complexMult_154/_zz_mid0 is absorbed into DSP complexMult_154/mid_reg.
DSP Report: Generating DSP complexMult_154/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_154/biD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/biD2_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/data_real_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/arD1_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/mid_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/aiD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real_20 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real_10 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real0 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_154/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_154/aiD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/mid_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/brD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/brD2_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/arD1_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag_20 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag_10 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag0 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_155/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_155/coeff_imag_delay_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/arD1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/data_real_delay_2_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_47_port0_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/coeff_real_delay_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/mid_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/_zz_mid_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/_zz_mid_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: operator complexMult_155/_zz_mid_10 is absorbed into DSP complexMult_155/mid_reg.
DSP Report: operator complexMult_155/_zz_mid0 is absorbed into DSP complexMult_155/mid_reg.
DSP Report: Generating DSP complexMult_155/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_155/biD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/biD2_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/data_real_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/arD1_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/mid_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/aiD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real_20 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real_10 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real0 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_155/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_155/aiD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/mid_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/brD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/brD2_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/arD1_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag_20 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag_10 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag0 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_156/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_156/coeff_imag_delay_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/arD1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/data_real_delay_2_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_48_port0_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/coeff_real_delay_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/mid_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/_zz_mid_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/_zz_mid_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: operator complexMult_156/_zz_mid_10 is absorbed into DSP complexMult_156/mid_reg.
DSP Report: operator complexMult_156/_zz_mid0 is absorbed into DSP complexMult_156/mid_reg.
DSP Report: Generating DSP complexMult_156/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_156/biD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/biD2_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/data_real_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/arD1_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/mid_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/aiD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real_20 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real_10 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real0 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_156/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_156/aiD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/mid_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/brD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/brD2_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/arD1_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag_20 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag_10 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag0 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_157/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_157/coeff_imag_delay_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/arD1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/data_real_delay_2_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_49_port0_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/coeff_real_delay_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/mid_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/_zz_mid_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/_zz_mid_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: operator complexMult_157/_zz_mid_10 is absorbed into DSP complexMult_157/mid_reg.
DSP Report: operator complexMult_157/_zz_mid0 is absorbed into DSP complexMult_157/mid_reg.
DSP Report: Generating DSP complexMult_157/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_157/biD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/biD2_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/data_real_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/arD1_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/mid_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/aiD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real_20 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real_10 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real0 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_157/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_157/aiD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/mid_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/brD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/brD2_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/arD1_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag_20 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag_10 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag0 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_158/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_158/coeff_imag_delay_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/arD1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/data_real_delay_2_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_50_port0_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/coeff_real_delay_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/mid_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/_zz_mid_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/_zz_mid_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: operator complexMult_158/_zz_mid_10 is absorbed into DSP complexMult_158/mid_reg.
DSP Report: operator complexMult_158/_zz_mid0 is absorbed into DSP complexMult_158/mid_reg.
DSP Report: Generating DSP complexMult_158/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_158/biD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/biD2_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/data_real_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/arD1_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/mid_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/aiD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real_20 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real_10 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real0 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_158/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_158/aiD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/mid_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/brD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/brD2_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/arD1_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag_20 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag_10 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag0 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_159/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_159/coeff_imag_delay_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/arD1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/data_real_delay_2_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_51_port0_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/coeff_real_delay_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/mid_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/_zz_mid_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/_zz_mid_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: operator complexMult_159/_zz_mid_10 is absorbed into DSP complexMult_159/mid_reg.
DSP Report: operator complexMult_159/_zz_mid0 is absorbed into DSP complexMult_159/mid_reg.
DSP Report: Generating DSP complexMult_159/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_159/biD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/biD2_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/data_real_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/arD1_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/mid_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/aiD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real_20 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real_10 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real0 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_159/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_159/aiD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/mid_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/brD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/brD2_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/arD1_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag_20 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag_10 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag0 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_160/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_160/coeff_imag_delay_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/arD1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/data_real_delay_2_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_52_port0_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/coeff_real_delay_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/mid_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/_zz_mid_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/_zz_mid_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: operator complexMult_160/_zz_mid_10 is absorbed into DSP complexMult_160/mid_reg.
DSP Report: operator complexMult_160/_zz_mid0 is absorbed into DSP complexMult_160/mid_reg.
DSP Report: Generating DSP complexMult_160/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_160/biD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/biD2_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/data_real_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/arD1_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/mid_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/aiD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real_20 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real_10 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real0 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_160/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_160/aiD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/mid_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/brD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/brD2_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/arD1_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag_20 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag_10 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag0 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_161/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_161/coeff_imag_delay_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/arD1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/data_real_delay_2_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_53_port0_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/coeff_real_delay_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/mid_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/_zz_mid_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/_zz_mid_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: operator complexMult_161/_zz_mid_10 is absorbed into DSP complexMult_161/mid_reg.
DSP Report: operator complexMult_161/_zz_mid0 is absorbed into DSP complexMult_161/mid_reg.
DSP Report: Generating DSP complexMult_161/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_161/biD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/biD2_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/data_real_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/arD1_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/mid_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/aiD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real_20 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real_10 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real0 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_161/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_161/aiD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/mid_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/brD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/brD2_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/arD1_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag_20 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag_10 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag0 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_162/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_162/coeff_imag_delay_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/arD1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/data_real_delay_2_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_54_port0_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/coeff_real_delay_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/mid_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/_zz_mid_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/_zz_mid_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: operator complexMult_162/_zz_mid_10 is absorbed into DSP complexMult_162/mid_reg.
DSP Report: operator complexMult_162/_zz_mid0 is absorbed into DSP complexMult_162/mid_reg.
DSP Report: Generating DSP complexMult_162/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_162/biD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/biD2_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/data_real_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/arD1_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/mid_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/aiD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real_20 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real_10 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real0 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_162/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_162/aiD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/mid_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/brD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/brD2_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/arD1_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag_20 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag_10 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag0 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_163/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_163/coeff_imag_delay_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/arD1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/data_real_delay_2_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_55_port0_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/coeff_real_delay_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/mid_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/_zz_mid_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/_zz_mid_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: operator complexMult_163/_zz_mid_10 is absorbed into DSP complexMult_163/mid_reg.
DSP Report: operator complexMult_163/_zz_mid0 is absorbed into DSP complexMult_163/mid_reg.
DSP Report: Generating DSP complexMult_163/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_163/biD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/biD2_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/data_real_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/arD1_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/mid_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/aiD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real_20 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real_10 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real0 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_163/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_163/aiD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/mid_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/brD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/brD2_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/arD1_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag_20 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag_10 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag0 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_164/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_164/coeff_imag_delay_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/arD1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/data_real_delay_2_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_56_port0_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/coeff_real_delay_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/mid_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/_zz_mid_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/_zz_mid_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: operator complexMult_164/_zz_mid_10 is absorbed into DSP complexMult_164/mid_reg.
DSP Report: operator complexMult_164/_zz_mid0 is absorbed into DSP complexMult_164/mid_reg.
DSP Report: Generating DSP complexMult_164/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_164/biD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/biD2_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/data_real_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/arD1_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/mid_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/aiD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real_20 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real_10 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real0 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_164/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_164/aiD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/mid_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/brD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/brD2_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/arD1_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag_20 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag_10 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag0 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_165/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_165/coeff_imag_delay_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/arD1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/data_real_delay_2_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_57_port0_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/coeff_real_delay_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/mid_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/_zz_mid_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/_zz_mid_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: operator complexMult_165/_zz_mid_10 is absorbed into DSP complexMult_165/mid_reg.
DSP Report: operator complexMult_165/_zz_mid0 is absorbed into DSP complexMult_165/mid_reg.
DSP Report: Generating DSP complexMult_165/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_165/biD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/biD2_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/data_real_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/arD1_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/mid_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/aiD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real_20 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real_10 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real0 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_165/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_165/aiD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/mid_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/brD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/brD2_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/arD1_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag_20 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag_10 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag0 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_166/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_166/coeff_imag_delay_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/arD1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/data_real_delay_2_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_58_port0_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/coeff_real_delay_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/mid_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/_zz_mid_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/_zz_mid_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: operator complexMult_166/_zz_mid_10 is absorbed into DSP complexMult_166/mid_reg.
DSP Report: operator complexMult_166/_zz_mid0 is absorbed into DSP complexMult_166/mid_reg.
DSP Report: Generating DSP complexMult_166/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_166/biD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/biD2_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/data_real_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/arD1_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/mid_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/aiD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real_20 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real_10 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real0 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_166/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_166/aiD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/mid_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/brD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/brD2_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/arD1_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag_20 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag_10 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag0 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_167/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_167/coeff_imag_delay_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/arD1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/data_real_delay_2_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_59_port0_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/coeff_real_delay_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/mid_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/_zz_mid_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/_zz_mid_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: operator complexMult_167/_zz_mid_10 is absorbed into DSP complexMult_167/mid_reg.
DSP Report: operator complexMult_167/_zz_mid0 is absorbed into DSP complexMult_167/mid_reg.
DSP Report: Generating DSP complexMult_167/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_167/biD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/biD2_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/data_real_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/arD1_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/mid_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/aiD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real_20 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real_10 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real0 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_167/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_167/aiD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/mid_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/brD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/brD2_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/arD1_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag_20 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag_10 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag0 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_168/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_168/coeff_imag_delay_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/arD1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/data_real_delay_2_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_60_port0_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/coeff_real_delay_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/mid_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/_zz_mid_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/_zz_mid_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: operator complexMult_168/_zz_mid_10 is absorbed into DSP complexMult_168/mid_reg.
DSP Report: operator complexMult_168/_zz_mid0 is absorbed into DSP complexMult_168/mid_reg.
DSP Report: Generating DSP complexMult_168/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_168/biD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/biD2_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/data_real_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/arD1_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/mid_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/aiD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real_20 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real_10 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real0 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_168/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_168/aiD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/mid_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/brD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/brD2_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/arD1_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag_20 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag_10 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag0 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_169/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_169/coeff_imag_delay_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/arD1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/data_real_delay_2_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_61_port0_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/coeff_real_delay_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/mid_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/_zz_mid_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/_zz_mid_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: operator complexMult_169/_zz_mid_10 is absorbed into DSP complexMult_169/mid_reg.
DSP Report: operator complexMult_169/_zz_mid0 is absorbed into DSP complexMult_169/mid_reg.
DSP Report: Generating DSP complexMult_169/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_169/biD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/biD2_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/data_real_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/arD1_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/mid_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/aiD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real_20 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real_10 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real0 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_169/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_169/aiD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/mid_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/brD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/brD2_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/arD1_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag_20 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag_10 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag0 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_170/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_170/coeff_imag_delay_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/arD1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/data_real_delay_2_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_62_port0_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/coeff_real_delay_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/mid_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/_zz_mid_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/_zz_mid_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: operator complexMult_170/_zz_mid_10 is absorbed into DSP complexMult_170/mid_reg.
DSP Report: operator complexMult_170/_zz_mid0 is absorbed into DSP complexMult_170/mid_reg.
DSP Report: Generating DSP complexMult_170/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_170/biD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/biD2_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/data_real_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/arD1_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/mid_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/aiD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real_20 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real_10 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real0 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_170/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_170/aiD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/mid_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/brD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/brD2_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/arD1_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag_20 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag_10 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag0 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_171/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_171/coeff_imag_delay_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/arD1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/data_real_delay_2_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_63_port0_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/coeff_real_delay_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/mid_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/_zz_mid_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/_zz_mid_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: operator complexMult_171/_zz_mid_10 is absorbed into DSP complexMult_171/mid_reg.
DSP Report: operator complexMult_171/_zz_mid0 is absorbed into DSP complexMult_171/mid_reg.
DSP Report: Generating DSP complexMult_171/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_171/biD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/biD2_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/data_real_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/arD1_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/mid_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/aiD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real_20 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real_10 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real0 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_171/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_171/aiD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/mid_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/brD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/brD2_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/arD1_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag_20 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag_10 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag0 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_63_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_63_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_63_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_63_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_63_port0_reg[11]' (FD) to '_zz_twiddleFactorROMs_63_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_62_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_62_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_62_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_62_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_62_port0_reg[12]' (FD) to '_zz_twiddleFactorROMs_62_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_61_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_61_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_61_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_61_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_60_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_60_port0_reg[19]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_60_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_60_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_60_port0_reg[10]' (FD) to '_zz_twiddleFactorROMs_60_port0_reg[23]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_59_port0_reg[1] )
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_59_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_59_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_59_port0_reg[11]' (FD) to '_zz_twiddleFactorROMs_59_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_57_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_57_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_57_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_57_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_56_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_56_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_56_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_56_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_56_port0_reg[11]' (FD) to '_zz_twiddleFactorROMs_56_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_55_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_55_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_55_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_55_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_55_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_55_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_54_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_54_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_54_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_52_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_52_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_52_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_52_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_52_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_52_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_51_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_51_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_51_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_51_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_51_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_51_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_51_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_51_port0_reg[21]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_49_port0_reg[11] )
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_49_port0_reg[13]' (FD) to '_zz_twiddleFactorROMs_49_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_48_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_48_port0_reg[3]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_48_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_48_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_48_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_48_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_48_port0_reg[10]' (FD) to '_zz_twiddleFactorROMs_48_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_47_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_47_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_47_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_47_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_47_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_47_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_47_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_47_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_46_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_46_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_46_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_46_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_46_port0_reg[11]' (FD) to '_zz_twiddleFactorROMs_46_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_46_port0_reg[13]' (FD) to '_zz_twiddleFactorROMs_46_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_45_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[20]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_45_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_45_port0_reg[20]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_45_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_45_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_45_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_45_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_44_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_44_port0_reg[20]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_44_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[20]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_44_port0_reg[8] )
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_44_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_44_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_43_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_43_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_43_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_43_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_43_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_43_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_42_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_42_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_42_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_42_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_42_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_41_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[20]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_40_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_40_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_40_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_40_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_40_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_39_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[19]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_39_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_39_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_39_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_38_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_38_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_38_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_37_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_37_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_37_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_36_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_36_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_36_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_36_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_36_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_35_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_34_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_34_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_34_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_34_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_34_port0_reg[13]' (FD) to '_zz_twiddleFactorROMs_34_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_34_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_33_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_33_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_33_port0_reg[6]' (FD) to '_zz_twiddleFactorROMs_33_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_33_port0_reg[10]' (FD) to '_zz_twiddleFactorROMs_33_port0_reg[19]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_33_port0_reg[12]' (FD) to '_zz_twiddleFactorROMs_33_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_33_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[3]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[4]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[12]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_30_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_30_port0_reg[19]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_30_port0_reg[6]' (FD) to '_zz_twiddleFactorROMs_30_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_30_port0_reg[10]' (FD) to '_zz_twiddleFactorROMs_30_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_30_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_30_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_29_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_29_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_29_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_29_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_28_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_1_port0_reg[20]'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_18_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_17_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_16_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_15_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_14_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_13_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_12_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_11_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_10_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_9_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_8_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_7_port0_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_7_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_6_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_5_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_4_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_3_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_2_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_1_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[13] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_59_port0_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_47_port0_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_144/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_144/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_143/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_143/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_142/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_142/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_141/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_141/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_32_port0_reg[17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_32_port0_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_32_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_139/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_139/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_138/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_138/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_29_port0_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_29_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_29_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_136/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_136/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_135/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_135/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_134/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_134/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_133/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_133/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_132/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_132/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_131/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_131/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_130/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_130/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_129/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_129/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_128/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_128/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_127/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_127/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_18_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_18_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_17_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_17_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_16_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_16_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_15_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_15_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_14_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_14_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_13_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_13_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_12_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_12_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_11_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_11_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_10_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_10_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_9_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_9_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_8_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_8_port0_reg[31] )
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3917] design S2P_s64_p512_dut has port dataOut_valid driven by constant 1
WARNING: [Synth 8-7129] Port dataIn_valid in module S2P_s64_p512_dut is either unconnected or has no load
WARNING: [Synth 8-3917] design hsIfftPost_dut has port dataOut_valid driven by constant 1
WARNING: [Synth 8-7129] Port validIn in module anon_1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_106 is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:24 ; elapsed = 00:01:27 . Memory (MB): peak = 6567.770 ; gain = 1292.215 ; free physical = 24603 ; free virtual = 61002
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+-------------+------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+------------+-----------+----------------------+----------------+
|unamed__GBM0 | rams_3_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_4_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_5_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_6_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_1_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_2_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthIfftFtn | rams_7_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthIfftFtn | rams_0_reg | Implied | 16 x 288 | RAM32M16 x 21 |
+-------------+------------+-----------+----------------------+----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+-------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+-------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|ComplexMult | (((D:0x3fb1)'+(A:0x645)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3ec5)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3d3e)'+(A:0x1294)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3871)'+(A:0x1e2b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3179)'+(A:0x2899)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3ec5)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_31 | ((D'+A2)*(B:0x2d41))' | 16 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_31 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 16 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|synthIfftFtn | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3ec5)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3d3e)'+(A:0x1294)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3179)'+(A:0x2899)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3fb1)'+(A:0x645)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xf384)'+(A:0x3ec5)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xe1d5)'+(A:0x3871)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|unamed_31 | ((D'+A2)*(B:0x2d41))' | 16 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_31 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 16 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|synthIfftFtn | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xe783)'+(A:0x3b20)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|unamed_49 | ((D'+A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_49 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|synthIfftFtn | (((D:0xc4e0)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3871)'+(A:0x1e2b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3fb1)'+(A:0x645)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xe783)'+(A:0x3b20)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xce87)'+(A:0x2899)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xc13b)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0xc2c2)'+(A:0xed6c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xf384)'+(A:0x3ec5)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_49 | ((D'+A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_49 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|synthIfftFtn | (((D:0xc13b)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xc4e0)'+(A:0xe783)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0xdc72)'+(A:0xcaca)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3179)'+(A:0x2899)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x3ec5)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xe1d5)'+(A:0x3871)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xc4e0)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xc2c2)'+(A:0xed6c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0xdc72)'+(A:0xcaca)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D:0x645)'+(A:0xc04f)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+(A:0x4000)'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
+-------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:37 ; elapsed = 00:01:42 . Memory (MB): peak = 6567.770 ; gain = 1292.215 ; free physical = 25735 ; free virtual = 62230
---------------------------------------------------------------------------------
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Start Timing Optimization
---------------------------------------------------------------------------------
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Finished Timing Optimization : Time (s): cpu = 00:02:23 ; elapsed = 00:02:28 . Memory (MB): peak = 6920.613 ; gain = 1645.059 ; free physical = 24725 ; free virtual = 61247
---------------------------------------------------------------------------------
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+-------------+------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+------------+-----------+----------------------+----------------+
|unamed__GBM0 | rams_3_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_4_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_5_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_6_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_1_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_2_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthIfftFtn | rams_7_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthIfftFtn | rams_0_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_3_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_4_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_5_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_6_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_1_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_2_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthIfftFtn | rams_7_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthIfftFtn | rams_0_reg | Implied | 16 x 288 | RAM32M16 x 21 |
+-------------+------------+-----------+----------------------+----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `anon__GB1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB1' done
INFO: [Synth 8-5816] Retiming module `anon__GB2`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB2' done
INFO: [Synth 8-5816] Retiming module `anon__GB3`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB3' done
INFO: [Synth 8-5816] Retiming module `anon__GB5`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB5' done
INFO: [Synth 8-5816] Retiming module `anon__GB6`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB6' done
INFO: [Synth 8-5816] Retiming module `anon__GB7`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB7' done
INFO: [Synth 8-5816] Retiming module `anon__GB8`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB8' done
INFO: [Synth 8-5816] Retiming module `anon__GB9`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB9' done
INFO: [Synth 8-5816] Retiming module `anon__GB10`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB10' done
INFO: [Synth 8-5816] Retiming module `anon__GB11`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB11' done
INFO: [Synth 8-5816] Retiming module `anon__GB12`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB12' done
INFO: [Synth 8-5816] Retiming module `hsIfftPre_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `hsIfftPre_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `unamed__GBM1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM1' done
INFO: [Synth 8-5816] Retiming module `matintrlv_r64_c8_w36_sw64_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `matintrlv_r64_c8_w36_sw64_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `matintrlv_r8_c64_w36_sw64_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `matintrlv_r8_c64_w36_sw64_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `unamed__GBM1__1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM1__1' done
INFO: [Synth 8-5816] Retiming module `unamed_3`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3:/_zz_ret_3_real_reg[17]_bret
unamed_3:/_zz_ret_3_real_reg[17]_bret__0
unamed_3:/_zz_ret_3_real_reg[17]_bret__1
unamed_3:/_zz_ret_3_real_reg[17]_bret__10
unamed_3:/_zz_ret_3_real_reg[17]_bret__11
unamed_3:/_zz_ret_3_real_reg[17]_bret__12
unamed_3:/_zz_ret_3_real_reg[17]_bret__13
unamed_3:/_zz_ret_3_real_reg[17]_bret__14
unamed_3:/_zz_ret_3_real_reg[17]_bret__15
unamed_3:/_zz_ret_3_real_reg[17]_bret__16
unamed_3:/_zz_ret_3_real_reg[17]_bret__17
unamed_3:/_zz_ret_3_real_reg[17]_bret__18
unamed_3:/_zz_ret_3_real_reg[17]_bret__19
unamed_3:/_zz_ret_3_real_reg[17]_bret__2
unamed_3:/_zz_ret_3_real_reg[17]_bret__20
unamed_3:/_zz_ret_3_real_reg[17]_bret__21
unamed_3:/_zz_ret_3_real_reg[17]_bret__22
unamed_3:/_zz_ret_3_real_reg[17]_bret__23
unamed_3:/_zz_ret_3_real_reg[17]_bret__24
unamed_3:/_zz_ret_3_real_reg[17]_bret__25
unamed_3:/_zz_ret_3_real_reg[17]_bret__26
unamed_3:/_zz_ret_3_real_reg[17]_bret__27
unamed_3:/_zz_ret_3_real_reg[17]_bret__28
unamed_3:/_zz_ret_3_real_reg[17]_bret__29
unamed_3:/_zz_ret_3_real_reg[17]_bret__3
unamed_3:/_zz_ret_3_real_reg[17]_bret__30
unamed_3:/_zz_ret_3_real_reg[17]_bret__31
unamed_3:/_zz_ret_3_real_reg[17]_bret__32
unamed_3:/_zz_ret_3_real_reg[17]_bret__33
unamed_3:/_zz_ret_3_real_reg[17]_bret__34
unamed_3:/_zz_ret_3_real_reg[17]_bret__35
unamed_3:/_zz_ret_3_real_reg[17]_bret__36
unamed_3:/_zz_ret_3_real_reg[17]_bret__37
unamed_3:/_zz_ret_3_real_reg[17]_bret__38
unamed_3:/_zz_ret_3_real_reg[17]_bret__39
unamed_3:/_zz_ret_3_real_reg[17]_bret__4
unamed_3:/_zz_ret_3_real_reg[17]_bret__40
unamed_3:/_zz_ret_3_real_reg[17]_bret__41
unamed_3:/_zz_ret_3_real_reg[17]_bret__42
unamed_3:/_zz_ret_3_real_reg[17]_bret__43
unamed_3:/_zz_ret_3_real_reg[17]_bret__44
unamed_3:/_zz_ret_3_real_reg[17]_bret__45
unamed_3:/_zz_ret_3_real_reg[17]_bret__46
unamed_3:/_zz_ret_3_real_reg[17]_bret__47
unamed_3:/_zz_ret_3_real_reg[17]_bret__48
unamed_3:/_zz_ret_3_real_reg[17]_bret__49
unamed_3:/_zz_ret_3_real_reg[17]_bret__5
unamed_3:/_zz_ret_3_real_reg[17]_bret__50
unamed_3:/_zz_ret_3_real_reg[17]_bret__51
unamed_3:/_zz_ret_3_real_reg[17]_bret__6
unamed_3:/_zz_ret_3_real_reg[17]_bret__7
unamed_3:/_zz_ret_3_real_reg[17]_bret__8
unamed_3:/_zz_ret_3_real_reg[17]_bret__9
unamed_3:/_zz_ret_7_real_17_reg[17]_bret
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__0__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__0__0__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__1
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__10
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__10__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__11
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__11__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__12
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__12__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__13
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__13__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__14
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__14__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__15
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__15__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__16
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__17
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__18
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__19
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__1__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__2
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__20
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__21
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__22
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__23
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__24
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__25
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__26
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__27
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__28
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__29
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__2__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__3
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__30
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__31
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__32
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__33
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__34
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__3__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__4
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__4__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__5
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__5__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__6
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__6__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__7
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__7__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__8
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__8__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__9
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3' done
INFO: [Synth 8-5816] Retiming module `unamed_3__1`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__0
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__1
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__10
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__11
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__12
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__13
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__14
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__15
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__16
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__17
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__18
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__19
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__2
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__20
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__21
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__22
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__23
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__24
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__25
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__26
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__27
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__28
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__29
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__3
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__30
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__31
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__32
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__33
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__34
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__35
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__36
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__37
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__38
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__39
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__4
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__40
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__41
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__42
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__43
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__44
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__45
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__46
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__47
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__48
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__49
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__5
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__50
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__51
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__6
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__7
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__8
ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__9
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__0__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__0__0__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__1
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__10
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__10__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__11
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__11__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__12
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__12__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__13
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__13__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__14
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__14__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__15
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__15__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__16
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__17
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__18
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__19
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__1__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__2
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__20
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__21
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__22
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__23
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__24
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__25
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__26
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__27
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__28
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__29
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__2__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__3
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__30
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__31
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__32
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__33
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__34
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__3__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__4
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__4__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__5
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__5__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__6
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__6__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__7
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__7__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__8
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__8__0
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__9
ifftCore/core/core0/core/unamed_179/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3__1' done
INFO: [Synth 8-5816] Retiming module `unamed_3__2`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3__2:/_zz_ret_3_real_reg[17]_bret
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__0
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__1
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__10
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__11
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__12
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__13
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__14
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__15
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__16
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__17
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__18
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__19
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__2
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__20
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__21
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__22
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__23
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__24
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__25
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__26
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__27
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__28
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__29
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__3
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__30
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__31
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__32
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__33
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__34
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__35
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__36
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__37
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__38
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__39
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__4
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__40
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__41
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__42
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__43
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__44
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__45
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__46
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__47
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__48
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__49
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__5
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__50
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__51
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__6
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__7
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__8
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__9
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__0__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__0__0__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__1
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__10
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__10__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__11
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__11__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__12
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__12__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__13
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__13__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__14
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__14__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__15
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__15__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__16
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__17
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__18
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__19
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__1__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__2
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__20
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__21
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__22
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__23
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__24
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__25
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__26
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__27
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__28
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__29
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__2__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__3
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__30
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__31
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__32
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__33
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__34
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__3__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__4
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__4__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__5
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__5__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__6
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__6__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__7
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__7__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__8
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__8__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__9
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3__2' done
INFO: [Synth 8-5816] Retiming module `unamed_3__3`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__0
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__1
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__10
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__11
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__12
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__13
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__14
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__15
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__16
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__17
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__18
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__19
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__2
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__20
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__21
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__22
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__23
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__24
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__25
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__26
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__27
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__28
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__29
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__3
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__30
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__31
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__32
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__33
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__34
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__35
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__36
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__37
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__38
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__39
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__4
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__40
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__41
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__42
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__43
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__44
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__45
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__46
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__47
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__48
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__49
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__5
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__50
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__51
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__6
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__7
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__8
ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__9
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__0__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__0__0__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__1
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__10
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__10__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__11
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__11__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__12
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__12__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__13
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__13__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__14
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__14__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__15
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__15__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__16
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__17
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__18
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__19
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__1__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__2
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__20
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__21
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__22
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__23
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__24
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__25
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__26
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__27
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__28
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__29
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__2__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__3
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__30
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__31
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__32
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__33
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__34
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__3__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__4
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__4__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__5
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__5__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__6
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__6__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__7
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__7__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__8
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__8__0
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__9
ifftCore/core/core0/core/unamed_183/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3__3' done
INFO: [Synth 8-5816] Retiming module `ifft_n64_factors_8_8_scales_2_2_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `ifft_n64_factors_8_8_scales_2_2_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `unamed_3__4`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3__4:/_zz_ret_3_real_reg[17]_bret
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__0
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__1
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__10
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__11
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__12
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__13
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__14
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__15
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__16
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__17
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__18
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__19
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__2
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__20
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__21
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__22
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__23
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__24
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__25
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__26
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__27
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__28
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__29
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__3
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__30
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__31
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__32
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__33
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__34
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__35
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__36
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__37
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__38
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__39
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__4
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__40
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__41
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__42
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__43
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__44
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__45
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__46
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__47
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__48
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__49
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__5
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__50
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__51
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__6
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__7
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__8
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__9
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__0__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__0__0__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__1
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__10
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__10__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__11
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__11__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__12
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__12__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__13
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__13__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__14
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__14__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__15
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__15__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__16
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__17
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__18
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__19
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__1__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__2
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__20
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__21
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__22
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__23
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__24
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__25
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__26
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__27
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__28
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__29
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__2__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__3
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__30
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__31
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__32
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__33
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__34
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__3__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__4
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__4__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__5
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__5__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__6
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__6__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__7
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__7__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__8
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__8__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__9
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3__4' done
INFO: [Synth 8-5816] Retiming module `ifft_n8_factors_8_scales_1_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `ifft_n8_factors_8_scales_1_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `ifft_n512_sw64_factors_8_8_8_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `ifft_n512_sw64_factors_8_8_8_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `unamed_103_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_103_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `anon__GB4_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GB4_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `unamed__GBM0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `unamed_94__GC0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_94__GC0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GC0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GC0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `S2P_s64_p512_dut_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `S2P_s64_p512_dut_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `hsIfftPost_dut_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `hsIfftPost_dut_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn__GCB2_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn__GCB2_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
INFO: [Synth 8-5816] Retiming module `unamed__GBM0__1_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM0__1_tempName' done
INFO: [Synth 8-5816] Retiming module `synthIfftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthIfftFtn' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:03:39 ; elapsed = 00:03:44 . Memory (MB): peak = 7019.797 ; gain = 1744.242 ; free physical = 21103 ; free virtual = 57615
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:04:16 ; elapsed = 00:04:21 . Memory (MB): peak = 7151.852 ; gain = 1876.297 ; free physical = 21176 ; free virtual = 57835
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:04:17 ; elapsed = 00:04:22 . Memory (MB): peak = 7151.852 ; gain = 1876.297 ; free physical = 21047 ; free virtual = 57707
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:05:10 ; elapsed = 00:05:15 . Memory (MB): peak = 7164.414 ; gain = 1888.859 ; free physical = 20697 ; free virtual = 57356
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:05:11 ; elapsed = 00:05:16 . Memory (MB): peak = 7164.414 ; gain = 1888.859 ; free physical = 19498 ; free virtual = 56158
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:05:15 ; elapsed = 00:05:21 . Memory (MB): peak = 7164.414 ; gain = 1888.859 ; free physical = 20757 ; free virtual = 57416
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:05:17 ; elapsed = 00:05:23 . Memory (MB): peak = 7164.414 ; gain = 1888.859 ; free physical = 20757 ; free virtual = 57417
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+-------------+------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+-------------+------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|synthIfftFtn | ifftCore/core/core0/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_108/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_109/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_110/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_111/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_113/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_114/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_179/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_180/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_181/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_182/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_183/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_185/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_186/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_115/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_115/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_116/ret_real_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_116/ret_imag_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_117/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_117/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_118/ret_real_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_118/ret_imag_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_119/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_119/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_120/ret_real_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_120/ret_imag_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_121/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_121/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_122/ret_real_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_122/ret_imag_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_123/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_123/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_127/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_131/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_131/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_139/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_139/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_145/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_147/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_147/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_151/ret_real_reg[17] | 6 | 17 | NO | NO | YES | 17 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_151/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_155/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_155/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_157/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_161/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_163/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_163/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_171/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_171/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core0/core/unamed_173/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/core1s_0/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core1s_1/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core1s_2/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core1s_3/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core1s_4/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core1s_5/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core1s_6/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/core1s_7/core/unamed_107/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_109/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_109/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_110/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_110/brD2_reg[13] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_111/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_111/brD2_reg[13] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_112/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_112/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_113/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_113/brD2_reg[10] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_114/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_114/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_115/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_115/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_116/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_117/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_118/brD2_reg[13] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_119/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_120/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_121/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_122/brD2_reg[13] | 3 | 10 | NO | NO | YES | 10 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_123/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_124/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_124/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_125/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_125/brD2_reg[13] | 3 | 10 | NO | NO | YES | 10 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_126/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_126/brD2_reg[13] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_127/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_127/brD2_reg[14] | 3 | 10 | NO | NO | YES | 10 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_128/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_128/brD2_reg[14] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_129/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_129/brD2_reg[14] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_130/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_130/brD2_reg[14] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_131/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_131/brD2_reg[14] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_132/brD2_reg[14] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_133/brD2_reg[14] | 3 | 10 | NO | NO | YES | 10 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_134/brD2_reg[14] | 3 | 11 | NO | NO | YES | 11 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_135/brD2_reg[14] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_136/brD2_reg[14] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_137/brD2_reg[14] | 3 | 10 | NO | NO | YES | 10 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_138/brD2_reg[14] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_139/brD2_reg[14] | 3 | 4 | NO | NO | YES | 4 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_140/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_140/brD2_reg[14] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_141/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_141/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_142/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_142/brD2_reg[12] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_143/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_143/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_144/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_144/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_145/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_145/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_146/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_146/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_147/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_147/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_148/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_149/brD2_reg[13] | 3 | 5 | NO | NO | YES | 5 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_150/brD2_reg[13] | 3 | 5 | NO | NO | YES | 5 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_151/brD2_reg[12] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_152/brD2_reg[11] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_153/brD2_reg[12] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_154/brD2_reg[12] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_155/brD2_reg[12] | 3 | 5 | NO | NO | YES | 5 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_156/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_156/brD2_reg[12] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_157/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_157/brD2_reg[12] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_158/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_158/brD2_reg[12] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_159/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_159/brD2_reg[12] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_160/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_160/brD2_reg[12] | 3 | 7 | NO | NO | YES | 7 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_161/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_161/brD2_reg[12] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_162/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_162/brD2_reg[12] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_163/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_163/brD2_reg[14] | 3 | 5 | NO | NO | YES | 5 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_164/brD2_reg[15] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_165/brD2_reg[15] | 3 | 11 | NO | NO | YES | 11 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_166/brD2_reg[15] | 3 | 11 | NO | NO | YES | 11 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_167/brD2_reg[15] | 3 | 10 | NO | NO | YES | 10 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_168/brD2_reg[15] | 3 | 4 | NO | NO | YES | 4 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_169/brD2_reg[15] | 3 | 6 | NO | NO | YES | 6 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_170/brD2_reg[15] | 3 | 9 | NO | NO | YES | 9 | 0 |
|synthIfftFtn | ifftCore/core/complexMult_171/brD2_reg[15] | 3 | 8 | NO | NO | YES | 8 | 0 |
|synthIfftFtn | ifftCore/core/inter0/core/core/writeRefresh_reg | 7 | 1 | YES | NO | YES | 1 | 0 |
|synthIfftFtn | ifftCore/core/inter0/core/core/readRefresh_reg | 8 | 1 | YES | NO | YES | 1 | 0 |
|synthIfftFtn | ifftCore/core/core0/dataIn_payload_last_delay_16_reg | 16 | 1 | YES | NO | YES | 1 | 0 |
|synthIfftFtn | ifftCore/core/inter1/core/core/writeRefresh_reg | 7 | 1 | YES | NO | YES | 1 | 0 |
|synthIfftFtn | ifftCore/core/inter2/core/core/writeRefresh_reg | 6 | 1 | YES | NO | YES | 1 | 0 |
|synthIfftFtn | ifftCore/core/inter1/core/core/readRefresh_reg | 8 | 1 | YES | NO | YES | 1 | 0 |
|synthIfftFtn | ifftCore/core/inter2/core/core/readRefresh_reg | 8 | 1 | YES | NO | YES | 1 | 0 |
|synthIfftFtn | s2p/dataIn_payload_last_delay_8_reg | 8 | 1 | YES | NO | YES | 1 | 0 |
|synthIfftFtn | post/core/lastIn_delay_5_reg | 4 | 1 | YES | NO | YES | 1 | 0 |
+-------------+------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
Retiming Report:
+--------------------+-----+
|Retiming summary: | |
+--------------------+-----+
|Forward Retiming | 0 |
|Backward Retiming | 10 |
|New registers added | 530 |
|Registers deleted | 180 |
+--------------------+-----+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
+-------------+-----------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+-------------+-----------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|ComplexMult | (((D'+A)'*B'')')' | 15 | 18 | - | 0 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 15 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 11 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 11 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 12 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 12 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 13 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 13 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 13 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 13 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 13 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 13 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 13 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 13 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 15 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 15 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|ComplexMult | (((D+A)'*B'')')' | 11 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 11 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 12 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 12 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 12 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_31 | (((D'+A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|unamed_31 | (((D'-A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 14 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 12 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 12 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 11 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|unamed_31 | (((D'+A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|unamed_31 | (((D'-A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|unamed_49 | (((D'+A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|unamed_49 | (((D'-A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 11 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 11 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 18 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 12 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 12 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_49 | (((D'+A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|unamed_49 | (((D'-A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 12 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 12 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 12 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 12 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 13 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthIfftFtn | (((D+A)'*B'')')' | 30 | 18 | - | 11 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 11 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
+-------------+-----------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------------+-------+
| |Cell |Count |
+------+----------------+-------+
|1 |CARRY8 | 8754|
|2 |DSP_ALU | 428|
|3 |DSP_A_B_DATA | 428|
|13 |DSP_C_DATA | 428|
|14 |DSP_MULTIPLIER | 428|
|16 |DSP_M_DATA | 428|
|17 |DSP_OUTPUT | 428|
|19 |DSP_PREADD | 428|
|20 |DSP_PREADD_DATA | 428|
|23 |LUT1 | 11411|
|24 |LUT2 | 41166|
|25 |LUT3 | 16449|
|26 |LUT4 | 1540|
|27 |LUT5 | 168|
|28 |LUT6 | 27482|
|29 |MUXF7 | 9152|
|30 |RAM32M16 | 504|
|31 |SRL16E | 2027|
|32 |FDCE | 761|
|33 |FDPE | 36|
|34 |FDRE | 166673|
|35 |FDSE | 216|
+------+----------------+-------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:05:17 ; elapsed = 00:05:23 . Memory (MB): peak = 7164.414 ; gain = 1888.859 ; free physical = 20856 ; free virtual = 57516
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 427 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:04:53 ; elapsed = 00:05:05 . Memory (MB): peak = 7168.324 ; gain = 1263.699 ; free physical = 32787 ; free virtual = 69447
Synthesis Optimization Complete : Time (s): cpu = 00:05:22 ; elapsed = 00:05:27 . Memory (MB): peak = 7168.324 ; gain = 1892.770 ; free physical = 32809 ; free virtual = 69446
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 7349.500 ; gain = 0.000 ; free physical = 32500 ; free virtual = 69136
INFO: [Netlist 29-17] Analyzing 18838 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 4 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 7714.336 ; gain = 0.000 ; free physical = 31126 ; free virtual = 67763
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 932 instances were transformed.
DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 428 instances
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 504 instances
Synth Design complete, checksum: e13c7d5f
INFO: [Common 17-83] Releasing license: Synthesis
596 Infos, 219 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:06:21 ; elapsed = 00:06:28 . Memory (MB): peak = 7714.336 ; gain = 2546.539 ; free physical = 33072 ; free virtual = 69708
# write_checkpoint -force synthIfftFtn_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthIfftFtn/synthIfftFtn_after_synth.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:34 ; elapsed = 00:00:37 . Memory (MB): peak = 8134.484 ; gain = 420.148 ; free physical = 32572 ; free virtual = 69300
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:23:30 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthIfftFtn
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+----------------------------+--------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+--------+-------+------------+-----------+-------+
| CLB LUTs* | 101719 | 0 | 0 | 1182240 | 8.60 |
| LUT as Logic | 95660 | 0 | 0 | 1182240 | 8.09 |
| LUT as Memory | 6059 | 0 | 0 | 591840 | 1.02 |
| LUT as Distributed RAM | 4032 | 0 | | | |
| LUT as Shift Register | 2027 | 0 | | | |
| CLB Registers | 167686 | 0 | 0 | 2364480 | 7.09 |
| Register as Flip Flop | 167686 | 0 | 0 | 2364480 | 7.09 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 8754 | 0 | 0 | 147780 | 5.92 |
| F7 Muxes | 9152 | 0 | 0 | 591120 | 1.55 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+----------------------------+--------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+--------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+--------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 36 | Yes | - | Set |
| 761 | Yes | - | Reset |
| 216 | Yes | Set | - |
| 166673 | Yes | Reset | - |
+--------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| DSPs | 428 | 0 | 0 | 6840 | 6.26 |
| DSP48E2 only | 428 | | | | |
+----------------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+--------+---------------------+
| Ref Name | Used | Functional Category |
+----------+--------+---------------------+
| FDRE | 166673 | Register |
| LUT2 | 41166 | CLB |
| LUT6 | 27482 | CLB |
| LUT3 | 16449 | CLB |
| LUT1 | 11411 | CLB |
| MUXF7 | 9152 | CLB |
| CARRY8 | 8754 | CLB |
| RAMD32 | 7056 | CLB |
| SRL16E | 2027 | CLB |
| LUT4 | 1540 | CLB |
| RAMS32 | 1008 | CLB |
| FDCE | 761 | Register |
| DSP48E2 | 428 | Arithmetic |
| FDSE | 216 | Register |
| LUT5 | 168 | CLB |
| FDPE | 36 | Register |
+----------+--------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:24:04 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthIfftFtn
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -0.406ns (required time - arrival time)
Source: ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_5_reg/DSP_M_DATA_INST/CLK
(rising edge-triggered cell DSP_M_DATA clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag_reg[15]/D
(rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 1.606ns (logic 1.310ns (81.569%) route 0.296ns (18.431%))
Logic Levels: 5 (CARRY8=2 DSP_ALU=1 DSP_OUTPUT=1 LUT2=1)
Clock Path Skew: -0.040ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.060ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=180344, unset) 0.060 0.060 ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_5_reg/CLK
DSP_M_DATA r ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_5_reg/DSP_M_DATA_INST/CLK
------------------------------------------------------------------- -------------------
DSP_M_DATA (Prop_DSP_M_DATA_CLK_V_DATA[14])
0.277 0.337 r ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_5_reg/DSP_M_DATA_INST/V_DATA[14]
net (fo=1, unplaced) 0.000 0.337 ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_5_reg/DSP_M_DATA.V_DATA<14>
DSP_ALU (Prop_DSP_ALU_V_DATA[14]_ALU_OUT[14])
0.571 0.908 f ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_5_reg/DSP_ALU_INST/ALU_OUT[14]
net (fo=1, unplaced) 0.000 0.908 ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_5_reg/DSP_ALU.ALU_OUT<14>
DSP_OUTPUT (Prop_DSP_OUTPUT_ALU_OUT[14]_P[14])
0.109 1.017 r ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_5_reg/DSP_OUTPUT_INST/P[14]
net (fo=2, unplaced) 0.245 1.262 ifftCore/core/core0/core/unamed_107/_zz_ret_7_imag_6[0]
LUT2 (Prop_LUT2_I1_O) 0.038 1.300 r ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag[7]_i_9/O
net (fo=1, unplaced) 0.020 1.320 ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag[7]_i_9_n_0
CARRY8 (Prop_CARRY8_S[0]_CO[7])
0.199 1.519 r ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag_reg[7]_i_1/CO[7]
net (fo=1, unplaced) 0.005 1.524 ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag_reg[7]_i_1_n_0
CARRY8 (Prop_CARRY8_CI_O[7])
0.116 1.640 r ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag_reg[15]_i_1/O[7]
net (fo=1, unplaced) 0.026 1.666 ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag_reg[15]_i_1_n_8
FDRE r ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag_reg[15]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=180344, unset) 0.020 1.270 ifftCore/core/core0/core/unamed_107/clk
FDRE r ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag_reg[15]/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDRE (Setup_FDRE_C_D) 0.025 1.260 ifftCore/core/core0/core/unamed_107/_zz_ret_3_imag_reg[15]
-------------------------------------------------------------------
required time 1.260
arrival time -1.666
-------------------------------------------------------------------
slack -0.406
report_timing: Time (s): cpu = 00:01:13 ; elapsed = 00:00:33 . Memory (MB): peak = 8647.652 ; gain = 513.168 ; free physical = 31979 ; free virtual = 68707
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:24:05 2022...
-
[INFO ]
-
: binary adder cost = 14582
-
[INFO ]
-
: ternary adder cost = 26316
-
[INFO ]
-
: reg cost = 186739
-
[INFO ]
-
:
LUT: 101719
FF: 167686
DSP: 428
BRAM: 0
CARRY8: 8754
-
[INFO ]
-
:
fmax = 603.8647342995168 MHz
-
9 m 45 s
passedshould synth for viterbiFtn
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:24:09
[Progress] at 1493.749 : Elaborate components
[Progress] at 1494.438 : Checks and transforms
[Progress] at 1500.997 : Generate Verilog
[Warning] toplevel/cores_0/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_1/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_2/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_3/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_4/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_5/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_6/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_7/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_8/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_9/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_10/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_11/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_12/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_13/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_14/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_15/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_16/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_17/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_18/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_19/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_20/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_21/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_22/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_23/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_24/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_25/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_26/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_27/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_28/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_29/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_30/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_31/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_32/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_33/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_34/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_35/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_36/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_37/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_38/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_39/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_40/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_41/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_42/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_43/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_44/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_45/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_46/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_47/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_48/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_49/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_50/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_51/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_52/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_53/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_54/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_55/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_56/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_57/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_58/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_59/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_60/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_61/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_62/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_63/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_64/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_65/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_66/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_67/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_68/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_69/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_70/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_71/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_72/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_73/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_74/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_75/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_76/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_77/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_78/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_79/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_80/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_81/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_82/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_83/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_84/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_85/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_86/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_87/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_88/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_89/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_90/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_91/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_92/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_93/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_94/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_95/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_96/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_97/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_98/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_99/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_100/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_101/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_102/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_103/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_104/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_105/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_106/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_107/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_108/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_109/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_110/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_111/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_112/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_113/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_114/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_115/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_116/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_117/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_118/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_119/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_120/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_121/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_122/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_123/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_124/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_125/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/cores_126/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] 65659 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 1505.106
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog unamed.v
# read_verilog unamed_1.v
# read_verilog unamed_2.v
# read_verilog unamed_3.v
# read_verilog unamed_6.v
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# read_verilog unamed_117.v
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# read_verilog unamed_126.v
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# read_verilog unamed_201.v
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# read_verilog unamed_383.v
# read_verilog unamed_384.v
# read_verilog unamed_385.v
# read_verilog unamed_386.v
# read_verilog unamed_387.v
# read_verilog unamed_388.v
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# read_verilog unamed_390.v
# read_verilog unamed_391.v
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# read_verilog unamed_470.v
# read_verilog unamed_471.v
# read_verilog unamed_472.v
# read_verilog unamed_473.v
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# read_verilog unamed_475.v
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# read_verilog unamed_477.v
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# read_verilog unamed_479.v
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# read_verilog unamed_483.v
# read_verilog unamed_484.v
# read_verilog unamed_485.v
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# read_verilog unamed_488.v
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# read_verilog unamed_503.v
# read_verilog unamed_504.v
# read_verilog unamed_505.v
# read_verilog unamed_506.v
# read_verilog unamed_507.v
# read_verilog synthViterbiFtn.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthViterbiFtn -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthViterbiFtn -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 21481
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5751.352 ; gain = 474.793 ; free physical = 34501 ; free virtual = 70874
---------------------------------------------------------------------------------
WARNING: [Synth 8-6014] Unused sequential element lastForBack_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_2.v:201]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_381 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_381.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_381 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_381.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_381 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_381.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_382 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_382.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_382 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_382.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_382 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_382.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_383 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_383.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_383 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_383.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_383 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_383.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_384 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_384.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_384 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_384.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_384 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_384.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_385 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_385.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_385 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_385.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_385 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_385.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_386 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_386.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_386 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_386.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_386 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_386.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_387 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_387.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_387 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_387.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_387 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_387.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_388 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_388.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_388 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_388.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_388 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_388.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_389 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_389.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_389 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_389.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_389 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_389.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_390 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_390.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_390 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_390.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_390 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_390.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_391 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_391.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_391 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_391.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_391 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_391.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_392 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_392.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_392 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_392.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_392 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_392.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_393 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_393.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_393 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_393.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_393 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_393.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_394 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_394.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_394 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_394.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_394 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_394.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_395 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_395.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_395 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_395.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_395 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_395.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_396 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_396.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_396 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_396.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_396 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_396.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_397 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_397.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_397 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_397.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_397 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_397.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_398 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_398.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_398 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_398.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_398 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_398.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_399 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_399.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_399 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_399.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_399 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_399.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_400 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_400.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_400 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_400.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_400 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_400.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_401 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_401.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_401 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_401.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_401 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_401.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_402 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_402.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_402 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_402.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_402 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_402.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_403 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_403.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_403 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_403.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_403 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_403.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_404 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_404.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_404 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_404.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_404 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_404.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_405 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_405.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_405 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_405.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_405 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_405.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_406 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_406.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_406 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_406.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_406 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_406.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_407 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_407.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_407 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_407.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_407 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_407.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_408 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_408.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_408 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_408.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_408 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_408.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_409 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_409.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_409 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_409.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_409 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_409.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_410 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_410.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_410 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_410.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_410 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_410.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_411 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_411.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_411 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_411.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_411 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_411.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_412 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_412.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_412 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_412.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_412 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_412.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_413 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_413.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_413 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_413.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_413 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_413.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_414 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_414.v:81]
INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-7129] Port validIn in module unamed_2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_378 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_507 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_375 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_506 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_372 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_505 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_369 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_504 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_366 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_503 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_363 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_502 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_360 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_501 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_357 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_500 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_354 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_499 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_351 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_498 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_348 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_497 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_345 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_496 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_342 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_495 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_339 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_494 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_336 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_493 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_333 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_492 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_330 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_491 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_327 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_490 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_324 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_489 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_321 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_488 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_318 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_487 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_315 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_486 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_312 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_485 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_309 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_484 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_306 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_483 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_303 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_482 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_300 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_481 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_297 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_480 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_294 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_479 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_291 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_478 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_288 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_477 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_285 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_476 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_282 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_475 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_279 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_474 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_276 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_473 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_273 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_472 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_270 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_471 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_267 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_470 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_264 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_469 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_261 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_468 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_258 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_467 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_255 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_466 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_252 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_465 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_249 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_464 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_246 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_463 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_243 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_462 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_240 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_461 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_237 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_460 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_234 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_459 is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:34 ; elapsed = 00:00:58 . Memory (MB): peak = 6818.398 ; gain = 1541.840 ; free physical = 24748 ; free virtual = 61141
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:37 ; elapsed = 00:01:02 . Memory (MB): peak = 6821.367 ; gain = 1544.809 ; free physical = 24760 ; free virtual = 61153
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:37 ; elapsed = 00:01:02 . Memory (MB): peak = 6821.367 ; gain = 1544.809 ; free physical = 24760 ; free virtual = 61153
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6821.367 ; gain = 0.000 ; free physical = 24516 ; free virtual = 60908
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 7058.367 ; gain = 0.000 ; free physical = 24279 ; free virtual = 60672
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 7058.367 ; gain = 0.000 ; free physical = 24458 ; free virtual = 60851
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:01:10 ; elapsed = 00:01:30 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 25136 ; free virtual = 61528
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:01:10 ; elapsed = 00:01:30 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 25134 ; free virtual = 61527
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:10 ; elapsed = 00:01:30 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 25134 ; free virtual = 61527
---------------------------------------------------------------------------------
INFO: [Synth 8-6904] The RAM "unamed_2:/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:02:06 ; elapsed = 00:02:28 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23846 ; free virtual = 60260
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 508
2 Input 6 Bit Adders := 254
2 Input 4 Bit Adders := 16256
+---Registers :
256 Bit Registers := 127
7 Bit Registers := 254
6 Bit Registers := 381
4 Bit Registers := 8128
1 Bit Registers := 17018
+---RAMs :
32K Bit (128 X 256 bit) RAMs := 127
128 Bit (128 X 1 bit) RAMs := 127
+---Muxes :
2 Input 7 Bit Muxes := 508
2 Input 6 Bit Muxes := 508
64 Input 5 Bit Muxes := 254
2 Input 4 Bit Muxes := 16256
32 Input 4 Bit Muxes := 254
2 Input 2 Bit Muxes := 127
2 Input 1 Bit Muxes := 254
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_1_reg' into 'cores_51/lastIn_delay_1_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:488]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_2_reg' into 'cores_51/lastIn_delay_2_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:489]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_3_reg' into 'cores_51/lastIn_delay_3_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:490]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_4_reg' into 'cores_51/lastIn_delay_4_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:491]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_5_reg' into 'cores_51/lastIn_delay_5_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:492]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_6_reg' into 'cores_51/lastIn_delay_6_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:493]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_7_reg' into 'cores_51/lastIn_delay_7_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:494]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_8_reg' into 'cores_51/lastIn_delay_8_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:495]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_9_reg' into 'cores_51/lastIn_delay_9_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:496]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_10_reg' into 'cores_51/lastIn_delay_10_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:497]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_11_reg' into 'cores_51/lastIn_delay_11_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:498]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_12_reg' into 'cores_51/lastIn_delay_12_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:499]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_13_reg' into 'cores_51/lastIn_delay_13_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:500]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_14_reg' into 'cores_51/lastIn_delay_14_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:501]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_15_reg' into 'cores_51/lastIn_delay_15_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:502]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_16_reg' into 'cores_51/lastIn_delay_16_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:503]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_17_reg' into 'cores_51/lastIn_delay_17_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:504]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_18_reg' into 'cores_51/lastIn_delay_18_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:505]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_19_reg' into 'cores_51/lastIn_delay_19_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:506]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_20_reg' into 'cores_51/lastIn_delay_20_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:507]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_21_reg' into 'cores_51/lastIn_delay_21_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:508]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_22_reg' into 'cores_51/lastIn_delay_22_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:509]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_23_reg' into 'cores_51/lastIn_delay_23_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:510]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_24_reg' into 'cores_51/lastIn_delay_24_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:511]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_25_reg' into 'cores_51/lastIn_delay_25_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:512]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_26_reg' into 'cores_51/lastIn_delay_26_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:513]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_27_reg' into 'cores_51/lastIn_delay_27_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:514]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_28_reg' into 'cores_51/lastIn_delay_28_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:515]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_29_reg' into 'cores_51/lastIn_delay_29_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:516]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_30_reg' into 'cores_51/lastIn_delay_30_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:517]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_31_reg' into 'cores_51/lastIn_delay_31_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:518]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_32_reg' into 'cores_51/lastIn_delay_32_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:519]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_33_reg' into 'cores_51/lastIn_delay_33_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:520]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_34_reg' into 'cores_51/lastIn_delay_34_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:521]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_35_reg' into 'cores_51/lastIn_delay_35_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:522]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_36_reg' into 'cores_51/lastIn_delay_36_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:523]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_37_reg' into 'cores_51/lastIn_delay_37_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:524]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_38_reg' into 'cores_51/lastIn_delay_38_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:525]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_39_reg' into 'cores_51/lastIn_delay_39_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:526]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_40_reg' into 'cores_51/lastIn_delay_40_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:527]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_41_reg' into 'cores_51/lastIn_delay_41_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:528]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_42_reg' into 'cores_51/lastIn_delay_42_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:529]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_43_reg' into 'cores_51/lastIn_delay_43_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:530]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_44_reg' into 'cores_51/lastIn_delay_44_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:531]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_45_reg' into 'cores_51/lastIn_delay_45_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:532]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_46_reg' into 'cores_51/lastIn_delay_46_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:533]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_47_reg' into 'cores_51/lastIn_delay_47_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:534]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_48_reg' into 'cores_51/lastIn_delay_48_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:535]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_49_reg' into 'cores_51/lastIn_delay_49_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:536]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_50_reg' into 'cores_51/lastIn_delay_50_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:537]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_51_reg' into 'cores_51/lastIn_delay_51_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:538]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_52_reg' into 'cores_51/lastIn_delay_52_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:539]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_53_reg' into 'cores_51/lastIn_delay_53_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:540]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_54_reg' into 'cores_51/lastIn_delay_54_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:541]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_55_reg' into 'cores_51/lastIn_delay_55_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:542]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_56_reg' into 'cores_51/lastIn_delay_56_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:543]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_57_reg' into 'cores_51/lastIn_delay_57_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:544]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_58_reg' into 'cores_51/lastIn_delay_58_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:545]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_59_reg' into 'cores_51/lastIn_delay_59_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:546]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_60_reg' into 'cores_51/lastIn_delay_60_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:547]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_61_reg' into 'cores_51/lastIn_delay_61_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:548]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_62_reg' into 'cores_51/lastIn_delay_62_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:549]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_63_reg' into 'cores_51/lastIn_delay_63_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:550]
INFO: [Synth 8-4471] merging register 'cores_61/lastForRead_reg' into 'cores_51/lastForRead_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:551]
INFO: [Synth 8-4471] merging register 'cores_61/lastForBack_reg' into 'cores_51/lastForBack_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_442.v:389]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_1_reg' into 'cores_51/lastIn_delay_1_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:488]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_2_reg' into 'cores_51/lastIn_delay_2_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:489]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_3_reg' into 'cores_51/lastIn_delay_3_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:490]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_4_reg' into 'cores_51/lastIn_delay_4_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:491]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_5_reg' into 'cores_51/lastIn_delay_5_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:492]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_6_reg' into 'cores_51/lastIn_delay_6_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:493]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_7_reg' into 'cores_51/lastIn_delay_7_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:494]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_8_reg' into 'cores_51/lastIn_delay_8_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:495]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_9_reg' into 'cores_51/lastIn_delay_9_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:496]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_10_reg' into 'cores_51/lastIn_delay_10_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:497]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_11_reg' into 'cores_51/lastIn_delay_11_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:498]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_12_reg' into 'cores_51/lastIn_delay_12_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:499]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_13_reg' into 'cores_51/lastIn_delay_13_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:500]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_14_reg' into 'cores_51/lastIn_delay_14_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:501]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_15_reg' into 'cores_51/lastIn_delay_15_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:502]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_16_reg' into 'cores_51/lastIn_delay_16_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:503]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_17_reg' into 'cores_51/lastIn_delay_17_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:504]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_18_reg' into 'cores_51/lastIn_delay_18_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:505]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_19_reg' into 'cores_51/lastIn_delay_19_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:506]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_20_reg' into 'cores_51/lastIn_delay_20_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:507]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_21_reg' into 'cores_51/lastIn_delay_21_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:508]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_22_reg' into 'cores_51/lastIn_delay_22_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:509]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_23_reg' into 'cores_51/lastIn_delay_23_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:510]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_24_reg' into 'cores_51/lastIn_delay_24_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:511]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_25_reg' into 'cores_51/lastIn_delay_25_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:512]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_26_reg' into 'cores_51/lastIn_delay_26_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:513]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_27_reg' into 'cores_51/lastIn_delay_27_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:514]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_28_reg' into 'cores_51/lastIn_delay_28_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:515]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_29_reg' into 'cores_51/lastIn_delay_29_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:516]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_30_reg' into 'cores_51/lastIn_delay_30_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:517]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_31_reg' into 'cores_51/lastIn_delay_31_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:518]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_32_reg' into 'cores_51/lastIn_delay_32_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:519]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_33_reg' into 'cores_51/lastIn_delay_33_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:520]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_34_reg' into 'cores_51/lastIn_delay_34_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:521]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_35_reg' into 'cores_51/lastIn_delay_35_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/unamed_441.v:522]
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_51/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_61/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_60/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_59/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_58/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_57/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_56/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_52/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_53/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_54/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_55/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_51/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_51/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_61/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_61/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_60/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_60/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_59/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_59/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_58/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_58/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_57/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_57/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_56/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_56/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_52/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_52/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_53/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_53/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_54/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_54/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB0/cores_55/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB0/cores_55/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB1/cores_47/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB1/cores_50/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB1/cores_62/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB1/cores_49/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB1/cores_47/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB1/cores_47/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB1/cores_50/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB1/cores_50/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB1/cores_62/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB1/cores_62/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB1/cores_49/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB1/cores_49/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB2/cores_44/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB2/cores_45/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB2/cores_46/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB2/cores_63/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB2/cores_44/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB2/cores_44/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB2/cores_45/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB2/cores_45/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB2/cores_46/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB2/cores_46/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB2/cores_63/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB2/cores_63/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_40/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_41/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_42/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_43/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_125/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB3/cores_40/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_40/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB3/cores_41/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_41/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB3/cores_42/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_42/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB3/cores_43/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_43/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB3/cores_125/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB3/cores_125/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_39/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_38/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_37/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_36/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_35/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_34/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_126/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB4/cores_39/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_39/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB4/cores_38/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_38/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB4/cores_37/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_37/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB4/cores_36/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_36/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB4/cores_35/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_35/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB4/cores_34/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_34/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB4/cores_126/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB4/cores_126/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_48/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_33/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_32/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_31/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_30/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_29/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_28/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_27/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_25/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_48/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_48/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_33/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_33/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_32/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_32/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_31/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_31/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_30/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_30/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_29/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_29/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_28/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_28/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_27/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_27/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB5/cores_25/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB5/cores_25/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_26/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_24/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_23/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_22/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_21/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_20/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_19/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_18/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_17/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_16/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_15/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB6/cores_26/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_26/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB6/cores_24/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_24/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB6/cores_23/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_23/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB6/cores_22/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_22/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB6/cores_21/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_21/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB6/cores_20/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_20/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB6/cores_19/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_19/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("synthViterbiFtn__GB6/cores_18/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "synthViterbiFtn__GB6/cores_18/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Common 17-14] Message 'Synth 8-6904' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
RAM ("synthViterbiFtn__GB6/cores_17/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB6/cores_16/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB6/cores_15/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("synthViterbiFtn__GB7/cores_14/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB7/cores_13/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB7/cores_12/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB7/cores_11/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB7/cores_10/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB7/cores_9/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB7/cores_8/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB7/cores_7/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB7/cores_6/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("synthViterbiFtn__GB8/cores_2/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB8/cores_3/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB8/cores_5/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("synthViterbiFtn__GB9/cores_0/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB9/cores_1/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB9/cores_4/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
RAM ("synthViterbiFtn__GB10/cores_123/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_121/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_120/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_119/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_118/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_117/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_116/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_115/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_113/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_112/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB10/cores_110/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("synthViterbiFtn__GB11/cores_108/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB11/cores_109/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB11/cores_114/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("synthViterbiFtn__GB12/cores_105/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB12/cores_106/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB12/cores_107/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB12/cores_111/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("synthViterbiFtn__GB13/cores_100/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB13/cores_101/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB13/cores_102/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB13/cores_103/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB13/cores_122/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("synthViterbiFtn__GB14/cores_94/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB14/cores_95/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB14/cores_96/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB14/cores_97/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB14/cores_98/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB14/cores_99/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Common 17-14] Message 'Synth 8-7031' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Common 17-14] Message 'Synth 8-5586' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
RAM ("synthViterbiFtn__GB15/cores_86/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB15/cores_87/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB15/cores_88/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB15/cores_89/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB15/cores_90/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB15/cores_91/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB15/cores_92/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB15/cores_93/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_77/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_78/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_79/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_80/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_81/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_82/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_83/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_84/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_85/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB16/cores_104/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
RAM ("synthViterbiFtn__GB17/cores_66/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_67/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_68/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_64/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_70/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_71/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_72/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_73/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_74/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_75/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB17/cores_76/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB18/cores_124/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB18/cores_65/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("synthViterbiFtn__GB18/cores_69/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:04:38 ; elapsed = 00:05:59 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 24475 ; free virtual = 61080
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+-------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+-------------------+---------------+----------------+
|unamed | updatingROM | 4x6 | LUT |
|unamed_1 | candidateStates_1 | 64x6 | LUT |
|unamed_1 | candidateStates_0 | 64x6 | LUT |
|unamed_3 | updatingROM | 4x6 | LUT |
|unamed_6 | updatingROM | 4x6 | LUT |
|unamed_9 | updatingROM | 4x6 | LUT |
|unamed_12 | updatingROM | 4x6 | LUT |
|unamed_15 | updatingROM | 4x6 | LUT |
|unamed_18 | updatingROM | 4x6 | LUT |
|unamed_21 | updatingROM | 4x6 | LUT |
|unamed_24 | updatingROM | 4x6 | LUT |
|unamed_27 | updatingROM | 4x6 | LUT |
|unamed_30 | updatingROM | 4x6 | LUT |
|unamed_33 | updatingROM | 4x6 | LUT |
|unamed_36 | updatingROM | 4x6 | LUT |
|unamed_39 | updatingROM | 4x6 | LUT |
|unamed_42 | updatingROM | 4x6 | LUT |
|unamed_45 | updatingROM | 4x6 | LUT |
|unamed_48 | updatingROM | 4x6 | LUT |
|unamed_51 | updatingROM | 4x6 | LUT |
|unamed_54 | updatingROM | 4x6 | LUT |
|unamed_57 | updatingROM | 4x6 | LUT |
|unamed_60 | updatingROM | 4x6 | LUT |
|unamed_63 | updatingROM | 4x6 | LUT |
|unamed_66 | updatingROM | 4x6 | LUT |
|unamed_69 | updatingROM | 4x6 | LUT |
|unamed_72 | updatingROM | 4x6 | LUT |
|unamed_75 | updatingROM | 4x6 | LUT |
|unamed_78 | updatingROM | 4x6 | LUT |
|unamed_81 | updatingROM | 4x6 | LUT |
|unamed_84 | updatingROM | 4x6 | LUT |
|unamed_87 | updatingROM | 4x6 | LUT |
|unamed_90 | updatingROM | 4x6 | LUT |
|unamed_93 | updatingROM | 4x6 | LUT |
|unamed_96 | updatingROM | 4x6 | LUT |
|unamed_99 | updatingROM | 4x6 | LUT |
|unamed_102 | updatingROM | 4x6 | LUT |
|unamed_105 | updatingROM | 4x6 | LUT |
|unamed_108 | updatingROM | 4x6 | LUT |
|unamed_111 | updatingROM | 4x6 | LUT |
|unamed_114 | updatingROM | 4x6 | LUT |
|unamed_117 | updatingROM | 4x6 | LUT |
|unamed_120 | updatingROM | 4x6 | LUT |
|unamed_123 | updatingROM | 4x6 | LUT |
|unamed_126 | updatingROM | 4x6 | LUT |
|unamed_129 | updatingROM | 4x6 | LUT |
|unamed_132 | updatingROM | 4x6 | LUT |
|unamed_135 | updatingROM | 4x6 | LUT |
|unamed_138 | updatingROM | 4x6 | LUT |
|unamed_141 | updatingROM | 4x6 | LUT |
|unamed_144 | updatingROM | 4x6 | LUT |
|unamed_147 | updatingROM | 4x6 | LUT |
|unamed_150 | updatingROM | 4x6 | LUT |
|unamed_153 | updatingROM | 4x6 | LUT |
|unamed_156 | updatingROM | 4x6 | LUT |
|unamed_159 | updatingROM | 4x6 | LUT |
|unamed_162 | updatingROM | 4x6 | LUT |
|unamed_165 | updatingROM | 4x6 | LUT |
|unamed_168 | updatingROM | 4x6 | LUT |
|unamed_171 | updatingROM | 4x6 | LUT |
|unamed_174 | updatingROM | 4x6 | LUT |
|unamed_177 | updatingROM | 4x6 | LUT |
|unamed_180 | updatingROM | 4x6 | LUT |
|unamed_183 | updatingROM | 4x6 | LUT |
|unamed_186 | updatingROM | 4x6 | LUT |
|unamed_189 | updatingROM | 4x6 | LUT |
|unamed_192 | updatingROM | 4x6 | LUT |
|unamed_195 | updatingROM | 4x6 | LUT |
|unamed_198 | updatingROM | 4x6 | LUT |
|unamed_201 | updatingROM | 4x6 | LUT |
|unamed_204 | updatingROM | 4x6 | LUT |
|unamed_207 | updatingROM | 4x6 | LUT |
|unamed_210 | updatingROM | 4x6 | LUT |
|unamed_213 | updatingROM | 4x6 | LUT |
|unamed_216 | updatingROM | 4x6 | LUT |
|unamed_219 | updatingROM | 4x6 | LUT |
|unamed_222 | updatingROM | 4x6 | LUT |
|unamed_225 | updatingROM | 4x6 | LUT |
|unamed_228 | updatingROM | 4x6 | LUT |
|unamed_231 | updatingROM | 4x6 | LUT |
|unamed_234 | updatingROM | 4x6 | LUT |
|unamed_237 | updatingROM | 4x6 | LUT |
|unamed_240 | updatingROM | 4x6 | LUT |
|unamed_243 | updatingROM | 4x6 | LUT |
|unamed_246 | updatingROM | 4x6 | LUT |
|unamed_249 | updatingROM | 4x6 | LUT |
|unamed_252 | updatingROM | 4x6 | LUT |
|unamed_255 | updatingROM | 4x6 | LUT |
|unamed_258 | updatingROM | 4x6 | LUT |
|unamed_261 | updatingROM | 4x6 | LUT |
|unamed_264 | updatingROM | 4x6 | LUT |
|unamed_267 | updatingROM | 4x6 | LUT |
|unamed_270 | updatingROM | 4x6 | LUT |
|unamed_273 | updatingROM | 4x6 | LUT |
|unamed_276 | updatingROM | 4x6 | LUT |
|unamed_279 | updatingROM | 4x6 | LUT |
|unamed_282 | updatingROM | 4x6 | LUT |
|unamed_285 | updatingROM | 4x6 | LUT |
|unamed_288 | updatingROM | 4x6 | LUT |
|unamed_291 | updatingROM | 4x6 | LUT |
|unamed_294 | updatingROM | 4x6 | LUT |
|unamed_297 | updatingROM | 4x6 | LUT |
|unamed_300 | updatingROM | 4x6 | LUT |
|unamed_303 | updatingROM | 4x6 | LUT |
|unamed_306 | updatingROM | 4x6 | LUT |
|unamed_309 | updatingROM | 4x6 | LUT |
|unamed_312 | updatingROM | 4x6 | LUT |
|unamed_315 | updatingROM | 4x6 | LUT |
|unamed_318 | updatingROM | 4x6 | LUT |
|unamed_321 | updatingROM | 4x6 | LUT |
|unamed_324 | updatingROM | 4x6 | LUT |
|unamed_327 | updatingROM | 4x6 | LUT |
|unamed_330 | updatingROM | 4x6 | LUT |
|unamed_333 | updatingROM | 4x6 | LUT |
|unamed_336 | updatingROM | 4x6 | LUT |
|unamed_339 | updatingROM | 4x6 | LUT |
|unamed_342 | updatingROM | 4x6 | LUT |
|unamed_345 | updatingROM | 4x6 | LUT |
|unamed_348 | updatingROM | 4x6 | LUT |
|unamed_351 | updatingROM | 4x6 | LUT |
|unamed_354 | updatingROM | 4x6 | LUT |
|unamed_357 | updatingROM | 4x6 | LUT |
|unamed_360 | updatingROM | 4x6 | LUT |
|unamed_363 | updatingROM | 4x6 | LUT |
|unamed_366 | updatingROM | 4x6 | LUT |
|unamed_369 | updatingROM | 4x6 | LUT |
|unamed_372 | updatingROM | 4x6 | LUT |
|unamed_375 | updatingROM | 4x6 | LUT |
|unamed_378 | updatingROM | 4x6 | LUT |
+------------+-------------------+---------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
+----------------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights |
+----------------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|synthViterbiFtn__GB0 | cores_51/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_61/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_60/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_59/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_58/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_57/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_56/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_52/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_53/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_54/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB0 | cores_55/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB1 | cores_47/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB1 | cores_50/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB1 | cores_62/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB1 | cores_49/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB2 | cores_44/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB2 | cores_45/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB2 | cores_46/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB2 | cores_63/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_40/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_41/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_42/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_43/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_125/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_39/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_38/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_37/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_36/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_35/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_34/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_126/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_48/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_33/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_32/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_31/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_30/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_29/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_28/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_27/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_25/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_26/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_24/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_23/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_22/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_21/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_20/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_19/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_18/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_17/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_16/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_15/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_14/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_13/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_12/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_11/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_10/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_9/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_8/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_7/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_6/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB8 | cores_2/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB8 | cores_3/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB8 | cores_5/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB9 | cores_0/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB9 | cores_1/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB9 | cores_4/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_123/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_121/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_120/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_119/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_118/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_117/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_116/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_115/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_113/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_112/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_110/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB11 | cores_108/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB11 | cores_109/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB11 | cores_114/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB12 | cores_105/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB12 | cores_106/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB12 | cores_107/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB12 | cores_111/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_100/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_101/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_102/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_103/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_122/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_94/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_95/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_96/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_97/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_98/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_99/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_86/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_87/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_88/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_89/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_90/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_91/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_92/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_93/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_77/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_78/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_79/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_80/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_81/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_82/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_83/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_84/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_85/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_104/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_66/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_67/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_68/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_64/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_70/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_71/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_72/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_73/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_74/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_75/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_76/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB18 | cores_124/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB18 | cores_65/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB18 | cores_69/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
+----------------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+----------------------+-----------------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------------+-----------------------------+-----------+----------------------+----------------+
|synthViterbiFtn__GB0 | cores_51/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_61/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_60/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_59/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_58/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_57/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_56/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_52/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_53/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_54/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_55/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB1 | cores_47/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB1 | cores_50/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB1 | cores_62/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB1 | cores_49/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB2 | cores_44/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB2 | cores_45/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB2 | cores_46/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB2 | cores_63/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_40/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_41/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_42/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_43/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_125/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_39/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_38/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_37/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_36/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_35/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_34/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_126/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_48/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_33/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_32/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_31/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_30/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_29/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_28/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_27/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_25/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_26/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_24/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_23/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_22/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_21/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_20/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_19/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_18/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_17/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_16/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_15/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_14/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_13/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_12/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_11/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_10/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_9/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_8/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_7/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_6/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB8 | cores_2/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB8 | cores_3/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB8 | cores_5/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB9 | cores_0/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB9 | cores_1/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB9 | cores_4/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_123/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_121/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_120/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_119/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_118/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_117/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_116/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_115/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_113/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_112/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_110/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB11 | cores_108/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB11 | cores_109/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB11 | cores_114/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB12 | cores_105/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB12 | cores_106/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB12 | cores_107/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB12 | cores_111/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_100/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_101/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_102/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_103/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_122/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_94/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_95/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_96/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_97/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_98/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_99/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_86/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_87/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_88/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_89/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_90/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_91/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_92/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_93/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_77/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_78/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_79/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_80/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_81/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_82/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_83/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_84/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_85/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_104/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_66/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_67/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_68/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_64/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_70/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_71/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_72/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_73/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_74/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_75/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_76/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB18 | cores_124/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB18 | cores_65/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB18 | cores_69/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
+----------------------+-----------------------------+-----------+----------------------+----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:04:52 ; elapsed = 00:06:13 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23848 ; free virtual = 60634
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-5584] The signal "synthViterbiFtn/cores_51/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5584] The signal "synthViterbiFtn/cores_61/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5584] The signal "synthViterbiFtn/cores_60/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5584] The signal "synthViterbiFtn/cores_59/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5584] The signal "synthViterbiFtn/cores_58/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5556] The block RAM "synthViterbiFtn/cores_57/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthViterbiFtn/cores_57/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthViterbiFtn/cores_56/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthViterbiFtn/cores_56/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthViterbiFtn/cores_52/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthViterbiFtn/cores_52/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthViterbiFtn/cores_53/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthViterbiFtn/cores_53/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthViterbiFtn/cores_54/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthViterbiFtn/cores_54/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthViterbiFtn/cores_55/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthViterbiFtn/cores_55/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:05:07 ; elapsed = 00:06:28 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 24412 ; free virtual = 61198
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+----------------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights |
+----------------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|synthViterbiFtn | cores_57/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn | cores_56/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn | cores_52/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn | cores_53/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn | cores_54/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn | cores_55/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB1 | cores_47/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB1 | cores_50/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB1 | cores_62/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB1 | cores_49/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB2 | cores_44/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB2 | cores_45/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB2 | cores_46/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB2 | cores_63/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_40/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_41/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_42/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_43/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB3 | cores_125/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_39/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_38/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_37/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_36/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_35/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_34/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB4 | cores_126/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_48/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_33/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_32/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_31/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_30/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_29/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_28/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_27/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB5 | cores_25/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_26/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_24/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_23/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_22/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_21/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_20/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_19/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_18/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_17/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_16/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB6 | cores_15/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_14/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_13/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_12/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_11/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_10/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_9/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_8/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_7/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB7 | cores_6/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB8 | cores_2/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB8 | cores_3/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB8 | cores_5/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB9 | cores_0/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB9 | cores_1/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB9 | cores_4/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_123/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_121/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_120/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_119/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_118/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_117/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_116/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_115/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_113/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_112/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB10 | cores_110/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB11 | cores_108/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB11 | cores_109/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB11 | cores_114/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB12 | cores_105/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB12 | cores_106/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB12 | cores_107/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB12 | cores_111/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_100/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_101/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_102/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_103/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB13 | cores_122/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_94/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_95/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_96/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_97/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_98/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB14 | cores_99/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_86/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_87/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_88/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_89/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_90/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_91/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_92/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB15 | cores_93/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_77/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_78/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_79/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_80/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_81/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_82/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_83/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_84/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_85/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB16 | cores_104/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_66/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_67/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_68/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_64/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_70/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_71/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_72/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_73/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_74/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_75/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB17 | cores_76/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB18 | cores_124/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB18 | cores_65/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthViterbiFtn__GB18 | cores_69/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
+----------------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
Distributed RAM: Final Mapping Report
+----------------------+-----------------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+----------------------+-----------------------------+-----------+----------------------+----------------+
|synthViterbiFtn__GB0 | cores_51/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_61/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_60/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_59/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_58/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_57/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_56/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_52/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_53/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_54/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB0 | cores_55/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB1 | cores_47/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB1 | cores_50/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB1 | cores_62/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB1 | cores_49/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB2 | cores_44/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB2 | cores_45/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB2 | cores_46/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB2 | cores_63/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_40/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_41/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_42/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_43/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB3 | cores_125/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_39/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_38/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_37/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_36/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_35/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_34/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB4 | cores_126/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_48/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_33/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_32/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_31/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_30/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_29/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_28/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_27/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB5 | cores_25/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_26/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_24/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_23/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_22/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_21/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_20/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_19/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_18/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_17/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_16/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB6 | cores_15/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_14/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_13/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_12/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_11/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_10/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_9/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_8/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_7/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB7 | cores_6/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB8 | cores_2/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB8 | cores_3/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB8 | cores_5/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB9 | cores_0/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB9 | cores_1/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB9 | cores_4/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_123/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_121/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_120/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_119/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_118/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_117/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_116/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_115/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_113/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_112/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB10 | cores_110/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB11 | cores_108/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB11 | cores_109/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB11 | cores_114/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB12 | cores_105/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB12 | cores_106/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB12 | cores_107/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB12 | cores_111/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_100/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_101/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_102/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_103/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB13 | cores_122/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_94/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_95/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_96/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_97/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_98/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB14 | cores_99/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_86/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_87/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_88/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_89/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_90/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_91/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_92/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB15 | cores_93/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_77/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_78/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_79/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_80/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_81/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_82/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_83/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_84/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_85/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB16 | cores_104/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_66/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_67/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_68/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_64/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_70/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_71/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_72/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_73/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_74/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_75/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB17 | cores_76/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB18 | cores_124/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB18 | cores_65/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|synthViterbiFtn__GB18 | cores_69/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
+----------------------+-----------------------------+-----------+----------------------+----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB0_tempName`
Numbers of forward move = 0, and backward move = 48
Retimed registers names:
cores_52/backward/currentState_reg[0]_bret__0
cores_52/backward/currentState_reg[0]_bret__1
cores_52/backward/currentState_reg[0]_bret__2
cores_52/backward/currentState_reg[0]_bret__3
cores_52/backward/currentState_reg[0]_bret__4
cores_52/backward/currentState_reg[0]_bret_bret
cores_52/backward/currentState_reg[0]_bret_bret__0
cores_52/backward/currentState_reg[0]_bret_bret__1
cores_52/backward/currentState_reg[0]_bret_bret__2
cores_52/backward/currentState_reg[0]_bret_bret__3
cores_52/backward/currentState_reg[0]_bret_bret__4
cores_52/backward/currentState_reg[1]_bret
cores_52/backward/currentState_reg[1]_bret__1
cores_52/backward/currentState_reg[1]_bret__2
cores_52/backward/currentState_reg[1]_bret__3
cores_52/backward/currentState_reg[2]_bret
cores_52/backward/currentState_reg[2]_bret__1
cores_52/backward/currentState_reg[2]_bret__2
cores_52/backward/currentState_reg[2]_bret__3
cores_52/backward/currentState_reg[3]_bret
cores_52/backward/currentState_reg[3]_bret__1
cores_52/backward/currentState_reg[3]_bret__2
cores_52/backward/currentState_reg[3]_bret__3
cores_52/backward/currentState_reg[4]_bret
cores_52/backward/currentState_reg[4]_bret__1
cores_52/backward/currentState_reg[4]_bret__2
cores_52/backward/currentState_reg[4]_bret__3
cores_52/backward/currentState_reg[5]_bret
cores_52/backward/currentState_reg[5]_bret__0_bret
cores_52/backward/currentState_reg[5]_bret__0_bret__0
cores_52/backward/currentState_reg[5]_bret__0_bret__1
cores_52/backward/currentState_reg[5]_bret__0_bret__2
cores_52/backward/currentState_reg[5]_bret__0_bret__3
cores_52/backward/currentState_reg[5]_bret__0_bret__4
cores_52/backward/currentState_reg[5]_bret__1
cores_52/backward/currentState_reg[5]_bret__2
cores_52/backward/currentState_reg[5]_bret__3
cores_53/backward/currentState_reg[0]_bret__0
cores_53/backward/currentState_reg[0]_bret__1
cores_53/backward/currentState_reg[0]_bret__2
cores_53/backward/currentState_reg[0]_bret__3
cores_53/backward/currentState_reg[0]_bret__4
cores_53/backward/currentState_reg[0]_bret_bret
cores_53/backward/currentState_reg[0]_bret_bret__0
cores_53/backward/currentState_reg[0]_bret_bret__1
cores_53/backward/currentState_reg[0]_bret_bret__2
cores_53/backward/currentState_reg[0]_bret_bret__3
cores_53/backward/currentState_reg[0]_bret_bret__4
cores_53/backward/currentState_reg[1]_bret
cores_53/backward/currentState_reg[1]_bret__1
cores_53/backward/currentState_reg[1]_bret__2
cores_53/backward/currentState_reg[1]_bret__3
cores_53/backward/currentState_reg[2]_bret
cores_53/backward/currentState_reg[2]_bret__1
cores_53/backward/currentState_reg[2]_bret__2
cores_53/backward/currentState_reg[2]_bret__3
cores_53/backward/currentState_reg[3]_bret
cores_53/backward/currentState_reg[3]_bret__1
cores_53/backward/currentState_reg[3]_bret__2
cores_53/backward/currentState_reg[3]_bret__3
cores_53/backward/currentState_reg[4]_bret
cores_53/backward/currentState_reg[4]_bret__1
cores_53/backward/currentState_reg[4]_bret__2
cores_53/backward/currentState_reg[4]_bret__3
cores_53/backward/currentState_reg[5]_bret
cores_53/backward/currentState_reg[5]_bret__0_bret
cores_53/backward/currentState_reg[5]_bret__0_bret__0
cores_53/backward/currentState_reg[5]_bret__0_bret__1
cores_53/backward/currentState_reg[5]_bret__0_bret__2
cores_53/backward/currentState_reg[5]_bret__0_bret__3
cores_53/backward/currentState_reg[5]_bret__0_bret__4
cores_53/backward/currentState_reg[5]_bret__1
cores_53/backward/currentState_reg[5]_bret__2
cores_53/backward/currentState_reg[5]_bret__3
cores_54/backward/currentState_reg[0]_bret__0
cores_54/backward/currentState_reg[0]_bret__1
cores_54/backward/currentState_reg[0]_bret__2
cores_54/backward/currentState_reg[0]_bret__3
cores_54/backward/currentState_reg[0]_bret__4
cores_54/backward/currentState_reg[0]_bret_bret
cores_54/backward/currentState_reg[0]_bret_bret__0
cores_54/backward/currentState_reg[0]_bret_bret__1
cores_54/backward/currentState_reg[0]_bret_bret__2
cores_54/backward/currentState_reg[0]_bret_bret__3
cores_54/backward/currentState_reg[0]_bret_bret__4
cores_54/backward/currentState_reg[1]_bret
cores_54/backward/currentState_reg[1]_bret__1
cores_54/backward/currentState_reg[1]_bret__2
cores_54/backward/currentState_reg[1]_bret__3
cores_54/backward/currentState_reg[2]_bret
cores_54/backward/currentState_reg[2]_bret__1
cores_54/backward/currentState_reg[2]_bret__2
cores_54/backward/currentState_reg[2]_bret__3
cores_54/backward/currentState_reg[3]_bret
cores_54/backward/currentState_reg[3]_bret__1
cores_54/backward/currentState_reg[3]_bret__2
cores_54/backward/currentState_reg[3]_bret__3
cores_54/backward/currentState_reg[4]_bret
cores_54/backward/currentState_reg[4]_bret__1
cores_54/backward/currentState_reg[4]_bret__2
cores_54/backward/currentState_reg[4]_bret__3
cores_54/backward/currentState_reg[5]_bret
cores_54/backward/currentState_reg[5]_bret__0_bret
cores_54/backward/currentState_reg[5]_bret__0_bret__0
cores_54/backward/currentState_reg[5]_bret__0_bret__1
cores_54/backward/currentState_reg[5]_bret__0_bret__2
cores_54/backward/currentState_reg[5]_bret__0_bret__3
cores_54/backward/currentState_reg[5]_bret__0_bret__4
cores_54/backward/currentState_reg[5]_bret__1
cores_54/backward/currentState_reg[5]_bret__2
cores_54/backward/currentState_reg[5]_bret__3
cores_55/backward/currentState_reg[0]_bret__0
cores_55/backward/currentState_reg[0]_bret__1
cores_55/backward/currentState_reg[0]_bret__2
cores_55/backward/currentState_reg[0]_bret__3
cores_55/backward/currentState_reg[0]_bret__4
cores_55/backward/currentState_reg[0]_bret_bret
cores_55/backward/currentState_reg[0]_bret_bret__0
cores_55/backward/currentState_reg[0]_bret_bret__1
cores_55/backward/currentState_reg[0]_bret_bret__2
cores_55/backward/currentState_reg[0]_bret_bret__3
cores_55/backward/currentState_reg[0]_bret_bret__4
cores_55/backward/currentState_reg[1]_bret
cores_55/backward/currentState_reg[1]_bret__1
cores_55/backward/currentState_reg[1]_bret__2
cores_55/backward/currentState_reg[1]_bret__3
cores_55/backward/currentState_reg[2]_bret
cores_55/backward/currentState_reg[2]_bret__1
cores_55/backward/currentState_reg[2]_bret__2
cores_55/backward/currentState_reg[2]_bret__3
cores_55/backward/currentState_reg[3]_bret
cores_55/backward/currentState_reg[3]_bret__1
cores_55/backward/currentState_reg[3]_bret__2
cores_55/backward/currentState_reg[3]_bret__3
cores_55/backward/currentState_reg[4]_bret
cores_55/backward/currentState_reg[4]_bret__1
cores_55/backward/currentState_reg[4]_bret__2
cores_55/backward/currentState_reg[4]_bret__3
cores_55/backward/currentState_reg[5]_bret
cores_55/backward/currentState_reg[5]_bret__0_bret
cores_55/backward/currentState_reg[5]_bret__0_bret__0
cores_55/backward/currentState_reg[5]_bret__0_bret__1
cores_55/backward/currentState_reg[5]_bret__0_bret__2
cores_55/backward/currentState_reg[5]_bret__0_bret__3
cores_55/backward/currentState_reg[5]_bret__0_bret__4
cores_55/backward/currentState_reg[5]_bret__1
cores_55/backward/currentState_reg[5]_bret__2
cores_55/backward/currentState_reg[5]_bret__3
cores_56/backward/currentState_reg[0]_bret__0
cores_56/backward/currentState_reg[0]_bret__1
cores_56/backward/currentState_reg[0]_bret__2
cores_56/backward/currentState_reg[0]_bret__3
cores_56/backward/currentState_reg[0]_bret__4
cores_56/backward/currentState_reg[0]_bret_bret
cores_56/backward/currentState_reg[0]_bret_bret__0
cores_56/backward/currentState_reg[0]_bret_bret__1
cores_56/backward/currentState_reg[0]_bret_bret__2
cores_56/backward/currentState_reg[0]_bret_bret__3
cores_56/backward/currentState_reg[0]_bret_bret__4
cores_56/backward/currentState_reg[1]_bret
cores_56/backward/currentState_reg[1]_bret__1
cores_56/backward/currentState_reg[1]_bret__2
cores_56/backward/currentState_reg[1]_bret__3
cores_56/backward/currentState_reg[2]_bret
cores_56/backward/currentState_reg[2]_bret__1
cores_56/backward/currentState_reg[2]_bret__2
cores_56/backward/currentState_reg[2]_bret__3
cores_56/backward/currentState_reg[3]_bret
cores_56/backward/currentState_reg[3]_bret__1
cores_56/backward/currentState_reg[3]_bret__2
cores_56/backward/currentState_reg[3]_bret__3
cores_56/backward/currentState_reg[4]_bret
cores_56/backward/currentState_reg[4]_bret__1
cores_56/backward/currentState_reg[4]_bret__2
cores_56/backward/currentState_reg[4]_bret__3
cores_56/backward/currentState_reg[5]_bret
cores_56/backward/currentState_reg[5]_bret__0_bret
cores_56/backward/currentState_reg[5]_bret__0_bret__0
cores_56/backward/currentState_reg[5]_bret__0_bret__1
cores_56/backward/currentState_reg[5]_bret__0_bret__2
cores_56/backward/currentState_reg[5]_bret__0_bret__3
cores_56/backward/currentState_reg[5]_bret__0_bret__4
cores_56/backward/currentState_reg[5]_bret__1
cores_56/backward/currentState_reg[5]_bret__2
cores_56/backward/currentState_reg[5]_bret__3
cores_57/backward/currentState_reg[0]_bret__0
cores_57/backward/currentState_reg[0]_bret__1
cores_57/backward/currentState_reg[0]_bret__2
cores_57/backward/currentState_reg[0]_bret__3
cores_57/backward/currentState_reg[0]_bret__4
cores_57/backward/currentState_reg[0]_bret_bret
cores_57/backward/currentState_reg[0]_bret_bret__0
cores_57/backward/currentState_reg[0]_bret_bret__1
cores_57/backward/currentState_reg[0]_bret_bret__2
cores_57/backward/currentState_reg[0]_bret_bret__3
cores_57/backward/currentState_reg[0]_bret_bret__4
cores_57/backward/currentState_reg[1]_bret
cores_57/backward/currentState_reg[1]_bret__1
cores_57/backward/currentState_reg[1]_bret__2
cores_57/backward/currentState_reg[1]_bret__3
cores_57/backward/currentState_reg[2]_bret
cores_57/backward/currentState_reg[2]_bret__1
cores_57/backward/currentState_reg[2]_bret__2
cores_57/backward/currentState_reg[2]_bret__3
cores_57/backward/currentState_reg[3]_bret
cores_57/backward/currentState_reg[3]_bret__1
cores_57/backward/currentState_reg[3]_bret__2
cores_57/backward/currentState_reg[3]_bret__3
cores_57/backward/currentState_reg[4]_bret
cores_57/backward/currentState_reg[4]_bret__1
cores_57/backward/currentState_reg[4]_bret__2
cores_57/backward/currentState_reg[4]_bret__3
cores_57/backward/currentState_reg[5]_bret
cores_57/backward/currentState_reg[5]_bret__0_bret
cores_57/backward/currentState_reg[5]_bret__0_bret__0
cores_57/backward/currentState_reg[5]_bret__0_bret__1
cores_57/backward/currentState_reg[5]_bret__0_bret__2
cores_57/backward/currentState_reg[5]_bret__0_bret__3
cores_57/backward/currentState_reg[5]_bret__0_bret__4
cores_57/backward/currentState_reg[5]_bret__1
cores_57/backward/currentState_reg[5]_bret__2
cores_57/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/reverse/lastIn_delay_1_reg' (FDC) to 'i_0/cores_57/backward/currentState_reg[0]_bret__4'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/readCounter_reg_rep[6]' (FD) to 'i_0/cores_55/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/readCounter_reg_rep[4]' (FD) to 'i_0/cores_55/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/readCounter_reg_rep[2]' (FD) to 'i_0/cores_55/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/readCounter_reg_rep[0]' (FD) to 'i_0/cores_55/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/readCounter_reg_rep[1]' (FD) to 'i_0/cores_55/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/readCounter_reg_rep[3]' (FD) to 'i_0/cores_55/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/readCounter_reg_rep[5]' (FD) to 'i_0/cores_55/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_54/readCounter_reg_rep[6]' (FD) to 'i_0/cores_54/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_54/readCounter_reg_rep[4]' (FD) to 'i_0/cores_54/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_54/readCounter_reg_rep[2]' (FD) to 'i_0/cores_54/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_54/readCounter_reg_rep[0]' (FD) to 'i_0/cores_54/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_54/readCounter_reg_rep[1]' (FD) to 'i_0/cores_54/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_54/readCounter_reg_rep[3]' (FD) to 'i_0/cores_54/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_54/readCounter_reg_rep[5]' (FD) to 'i_0/cores_54/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_53/readCounter_reg_rep[6]' (FD) to 'i_0/cores_53/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_53/readCounter_reg_rep[4]' (FD) to 'i_0/cores_53/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_53/readCounter_reg_rep[2]' (FD) to 'i_0/cores_53/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_53/readCounter_reg_rep[0]' (FD) to 'i_0/cores_53/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_53/readCounter_reg_rep[1]' (FD) to 'i_0/cores_53/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_53/readCounter_reg_rep[3]' (FD) to 'i_0/cores_53/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_53/readCounter_reg_rep[5]' (FD) to 'i_0/cores_53/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_52/readCounter_reg_rep[6]' (FD) to 'i_0/cores_52/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_52/readCounter_reg_rep[4]' (FD) to 'i_0/cores_52/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_52/readCounter_reg_rep[2]' (FD) to 'i_0/cores_52/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_52/readCounter_reg_rep[0]' (FD) to 'i_0/cores_52/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_52/readCounter_reg_rep[1]' (FD) to 'i_0/cores_52/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_52/readCounter_reg_rep[3]' (FD) to 'i_0/cores_52/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_52/readCounter_reg_rep[5]' (FD) to 'i_0/cores_52/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_56/readCounter_reg_rep[6]' (FD) to 'i_0/cores_56/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_56/readCounter_reg_rep[4]' (FD) to 'i_0/cores_56/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_56/readCounter_reg_rep[2]' (FD) to 'i_0/cores_56/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_56/readCounter_reg_rep[0]' (FD) to 'i_0/cores_56/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_56/readCounter_reg_rep[1]' (FD) to 'i_0/cores_56/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_56/readCounter_reg_rep[3]' (FD) to 'i_0/cores_56/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_56/readCounter_reg_rep[5]' (FD) to 'i_0/cores_56/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_57/readCounter_reg_rep[6]' (FD) to 'i_0/cores_57/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_57/readCounter_reg_rep[4]' (FD) to 'i_0/cores_57/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_57/readCounter_reg_rep[2]' (FD) to 'i_0/cores_57/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_57/readCounter_reg_rep[0]' (FD) to 'i_0/cores_57/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_57/readCounter_reg_rep[1]' (FD) to 'i_0/cores_57/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_57/readCounter_reg_rep[3]' (FD) to 'i_0/cores_57/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_57/readCounter_reg_rep[5]' (FD) to 'i_0/cores_57/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_58/readCounter_reg_rep[6]' (FD) to 'i_0/cores_58/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_58/readCounter_reg_rep[4]' (FD) to 'i_0/cores_58/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_58/readCounter_reg_rep[2]' (FD) to 'i_0/cores_58/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_58/readCounter_reg_rep[0]' (FD) to 'i_0/cores_58/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_58/readCounter_reg_rep[1]' (FD) to 'i_0/cores_58/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_58/readCounter_reg_rep[3]' (FD) to 'i_0/cores_58/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_58/readCounter_reg_rep[5]' (FD) to 'i_0/cores_58/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_58/writeLock_reg' (FDPE) to 'i_0/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_59/readCounter_reg_rep[6]' (FD) to 'i_0/cores_59/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_59/readCounter_reg_rep[4]' (FD) to 'i_0/cores_59/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_59/readCounter_reg_rep[2]' (FD) to 'i_0/cores_59/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_59/readCounter_reg_rep[0]' (FD) to 'i_0/cores_59/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_59/readCounter_reg_rep[1]' (FD) to 'i_0/cores_59/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_59/readCounter_reg_rep[3]' (FD) to 'i_0/cores_59/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_59/readCounter_reg_rep[5]' (FD) to 'i_0/cores_59/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_59/writeLock_reg' (FDPE) to 'i_0/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_60/readCounter_reg_rep[6]' (FD) to 'i_0/cores_60/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_60/readCounter_reg_rep[4]' (FD) to 'i_0/cores_60/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_60/readCounter_reg_rep[2]' (FD) to 'i_0/cores_60/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_60/readCounter_reg_rep[0]' (FD) to 'i_0/cores_60/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_60/readCounter_reg_rep[1]' (FD) to 'i_0/cores_60/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_60/readCounter_reg_rep[3]' (FD) to 'i_0/cores_60/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_60/readCounter_reg_rep[5]' (FD) to 'i_0/cores_60/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_60/writeLock_reg' (FDPE) to 'i_0/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_61/readCounter_reg_rep[6]' (FD) to 'i_0/cores_61/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_61/readCounter_reg_rep[4]' (FD) to 'i_0/cores_61/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_61/readCounter_reg_rep[2]' (FD) to 'i_0/cores_61/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_61/readCounter_reg_rep[0]' (FD) to 'i_0/cores_61/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_61/readCounter_reg_rep[1]' (FD) to 'i_0/cores_61/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_61/readCounter_reg_rep[3]' (FD) to 'i_0/cores_61/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_61/readCounter_reg_rep[5]' (FD) to 'i_0/cores_61/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_61/writeLock_reg' (FDPE) to 'i_0/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/readCounter_reg_rep[6]' (FD) to 'i_0/cores_51/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/readCounter_reg_rep[4]' (FD) to 'i_0/cores_51/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/readCounter_reg_rep[2]' (FD) to 'i_0/cores_51/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/readCounter_reg_rep[0]' (FD) to 'i_0/cores_51/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/readCounter_reg_rep[1]' (FD) to 'i_0/cores_51/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/readCounter_reg_rep[3]' (FD) to 'i_0/cores_51/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/readCounter_reg_rep[5]' (FD) to 'i_0/cores_51/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_51/writeLock_reg' (FDPE) to 'i_0/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/writeLock_reg' (FDPE) to 'i_0/cores_54/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_54/writeLock_reg' (FDPE) to 'i_0/cores_53/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_53/writeLock_reg' (FDPE) to 'i_0/cores_52/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_52/writeLock_reg' (FDPE) to 'i_0/cores_56/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_56/writeLock_reg' (FDPE) to 'i_0/cores_57/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/reverse/readCounter_reg_rep[6]' (FD) to 'i_0/cores_55/reverse/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/reverse/readCounter_reg_rep[4]' (FD) to 'i_0/cores_55/reverse/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/reverse/readCounter_reg_rep[2]' (FD) to 'i_0/cores_55/reverse/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/reverse/readCounter_reg_rep[0]' (FD) to 'i_0/cores_55/reverse/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/reverse/readCounter_reg_rep[1]' (FD) to 'i_0/cores_55/reverse/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/reverse/readCounter_reg_rep[3]' (FD) to 'i_0/cores_55/reverse/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/reverse/readCounter_reg_rep[5]' (FD) to 'i_0/cores_55/reverse/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/backward/currentState_reg[3]_bret' (FDC) to 'i_0/cores_57/backward/currentState_reg[0]_bret__4'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/backward/currentState_reg[3]_bret__1' (FDC) to 'i_0/cores_55/backward/currentState_reg[0]_bret__2'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/backward/currentState_reg[3]_bret__2' (FDC) to 'i_0/cores_55/backward/currentState_reg[0]_bret__3'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/backward/currentState_reg[2]_bret' (FDC) to 'i_0/cores_57/backward/currentState_reg[0]_bret__4'
INFO: [Synth 8-3886] merging instance 'i_0/cores_55/backward/currentState_reg[2]_bret__1' (FDC) to 'i_0/cores_55/backward/currentState_reg[0]_bret__2'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_57/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_57/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_57/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_57/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_56/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_56/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_56/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_56/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_52/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_52/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_52/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_52/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_53/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_53/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_53/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_53/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_54/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_54/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_54/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_54/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_55/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_55/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_55/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_0/cores_55/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB1_tempName`
Numbers of forward move = 0, and backward move = 32
Retimed registers names:
cores_47/backward/currentState_reg[0]_bret__0
cores_47/backward/currentState_reg[0]_bret__1
cores_47/backward/currentState_reg[0]_bret__2
cores_47/backward/currentState_reg[0]_bret__3
cores_47/backward/currentState_reg[0]_bret__4
cores_47/backward/currentState_reg[0]_bret_bret
cores_47/backward/currentState_reg[0]_bret_bret__0
cores_47/backward/currentState_reg[0]_bret_bret__1
cores_47/backward/currentState_reg[0]_bret_bret__2
cores_47/backward/currentState_reg[0]_bret_bret__3
cores_47/backward/currentState_reg[0]_bret_bret__4
cores_47/backward/currentState_reg[1]_bret
cores_47/backward/currentState_reg[1]_bret__1
cores_47/backward/currentState_reg[1]_bret__2
cores_47/backward/currentState_reg[1]_bret__3
cores_47/backward/currentState_reg[2]_bret
cores_47/backward/currentState_reg[2]_bret__1
cores_47/backward/currentState_reg[2]_bret__2
cores_47/backward/currentState_reg[2]_bret__3
cores_47/backward/currentState_reg[3]_bret
cores_47/backward/currentState_reg[3]_bret__1
cores_47/backward/currentState_reg[3]_bret__2
cores_47/backward/currentState_reg[3]_bret__3
cores_47/backward/currentState_reg[4]_bret
cores_47/backward/currentState_reg[4]_bret__1
cores_47/backward/currentState_reg[4]_bret__2
cores_47/backward/currentState_reg[4]_bret__3
cores_47/backward/currentState_reg[5]_bret
cores_47/backward/currentState_reg[5]_bret__0_bret
cores_47/backward/currentState_reg[5]_bret__0_bret__0
cores_47/backward/currentState_reg[5]_bret__0_bret__1
cores_47/backward/currentState_reg[5]_bret__0_bret__2
cores_47/backward/currentState_reg[5]_bret__0_bret__3
cores_47/backward/currentState_reg[5]_bret__0_bret__4
cores_47/backward/currentState_reg[5]_bret__1
cores_47/backward/currentState_reg[5]_bret__2
cores_47/backward/currentState_reg[5]_bret__3
cores_49/backward/currentState_reg[0]_bret__0
cores_49/backward/currentState_reg[0]_bret__1
cores_49/backward/currentState_reg[0]_bret__2
cores_49/backward/currentState_reg[0]_bret__3
cores_49/backward/currentState_reg[0]_bret__4
cores_49/backward/currentState_reg[0]_bret_bret
cores_49/backward/currentState_reg[0]_bret_bret__0
cores_49/backward/currentState_reg[0]_bret_bret__1
cores_49/backward/currentState_reg[0]_bret_bret__2
cores_49/backward/currentState_reg[0]_bret_bret__3
cores_49/backward/currentState_reg[0]_bret_bret__4
cores_49/backward/currentState_reg[1]_bret
cores_49/backward/currentState_reg[1]_bret__1
cores_49/backward/currentState_reg[1]_bret__2
cores_49/backward/currentState_reg[1]_bret__3
cores_49/backward/currentState_reg[2]_bret
cores_49/backward/currentState_reg[2]_bret__1
cores_49/backward/currentState_reg[2]_bret__2
cores_49/backward/currentState_reg[2]_bret__3
cores_49/backward/currentState_reg[3]_bret
cores_49/backward/currentState_reg[3]_bret__1
cores_49/backward/currentState_reg[3]_bret__2
cores_49/backward/currentState_reg[3]_bret__3
cores_49/backward/currentState_reg[4]_bret
cores_49/backward/currentState_reg[4]_bret__1
cores_49/backward/currentState_reg[4]_bret__2
cores_49/backward/currentState_reg[4]_bret__3
cores_49/backward/currentState_reg[5]_bret
cores_49/backward/currentState_reg[5]_bret__0_bret
cores_49/backward/currentState_reg[5]_bret__0_bret__0
cores_49/backward/currentState_reg[5]_bret__0_bret__1
cores_49/backward/currentState_reg[5]_bret__0_bret__2
cores_49/backward/currentState_reg[5]_bret__0_bret__3
cores_49/backward/currentState_reg[5]_bret__0_bret__4
cores_49/backward/currentState_reg[5]_bret__1
cores_49/backward/currentState_reg[5]_bret__2
cores_49/backward/currentState_reg[5]_bret__3
cores_50/backward/currentState_reg[0]_bret__0
cores_50/backward/currentState_reg[0]_bret__1
cores_50/backward/currentState_reg[0]_bret__2
cores_50/backward/currentState_reg[0]_bret__3
cores_50/backward/currentState_reg[0]_bret__4
cores_50/backward/currentState_reg[0]_bret_bret
cores_50/backward/currentState_reg[0]_bret_bret__0
cores_50/backward/currentState_reg[0]_bret_bret__1
cores_50/backward/currentState_reg[0]_bret_bret__2
cores_50/backward/currentState_reg[0]_bret_bret__3
cores_50/backward/currentState_reg[0]_bret_bret__4
cores_50/backward/currentState_reg[1]_bret
cores_50/backward/currentState_reg[1]_bret__1
cores_50/backward/currentState_reg[1]_bret__2
cores_50/backward/currentState_reg[1]_bret__3
cores_50/backward/currentState_reg[2]_bret
cores_50/backward/currentState_reg[2]_bret__1
cores_50/backward/currentState_reg[2]_bret__2
cores_50/backward/currentState_reg[2]_bret__3
cores_50/backward/currentState_reg[3]_bret
cores_50/backward/currentState_reg[3]_bret__1
cores_50/backward/currentState_reg[3]_bret__2
cores_50/backward/currentState_reg[3]_bret__3
cores_50/backward/currentState_reg[4]_bret
cores_50/backward/currentState_reg[4]_bret__1
cores_50/backward/currentState_reg[4]_bret__2
cores_50/backward/currentState_reg[4]_bret__3
cores_50/backward/currentState_reg[5]_bret
cores_50/backward/currentState_reg[5]_bret__0_bret
cores_50/backward/currentState_reg[5]_bret__0_bret__0
cores_50/backward/currentState_reg[5]_bret__0_bret__1
cores_50/backward/currentState_reg[5]_bret__0_bret__2
cores_50/backward/currentState_reg[5]_bret__0_bret__3
cores_50/backward/currentState_reg[5]_bret__0_bret__4
cores_50/backward/currentState_reg[5]_bret__1
cores_50/backward/currentState_reg[5]_bret__2
cores_50/backward/currentState_reg[5]_bret__3
cores_62/backward/currentState_reg[0]_bret__0
cores_62/backward/currentState_reg[0]_bret__1
cores_62/backward/currentState_reg[0]_bret__2
cores_62/backward/currentState_reg[0]_bret__3
cores_62/backward/currentState_reg[0]_bret__4
cores_62/backward/currentState_reg[0]_bret_bret
cores_62/backward/currentState_reg[0]_bret_bret__0
cores_62/backward/currentState_reg[0]_bret_bret__1
cores_62/backward/currentState_reg[0]_bret_bret__2
cores_62/backward/currentState_reg[0]_bret_bret__3
cores_62/backward/currentState_reg[0]_bret_bret__4
cores_62/backward/currentState_reg[1]_bret
cores_62/backward/currentState_reg[1]_bret__1
cores_62/backward/currentState_reg[1]_bret__2
cores_62/backward/currentState_reg[1]_bret__3
cores_62/backward/currentState_reg[2]_bret
cores_62/backward/currentState_reg[2]_bret__1
cores_62/backward/currentState_reg[2]_bret__2
cores_62/backward/currentState_reg[2]_bret__3
cores_62/backward/currentState_reg[3]_bret
cores_62/backward/currentState_reg[3]_bret__1
cores_62/backward/currentState_reg[3]_bret__2
cores_62/backward/currentState_reg[3]_bret__3
cores_62/backward/currentState_reg[4]_bret
cores_62/backward/currentState_reg[4]_bret__1
cores_62/backward/currentState_reg[4]_bret__2
cores_62/backward/currentState_reg[4]_bret__3
cores_62/backward/currentState_reg[5]_bret
cores_62/backward/currentState_reg[5]_bret__0_bret
cores_62/backward/currentState_reg[5]_bret__0_bret__0
cores_62/backward/currentState_reg[5]_bret__0_bret__1
cores_62/backward/currentState_reg[5]_bret__0_bret__2
cores_62/backward/currentState_reg[5]_bret__0_bret__3
cores_62/backward/currentState_reg[5]_bret__0_bret__4
cores_62/backward/currentState_reg[5]_bret__1
cores_62/backward/currentState_reg[5]_bret__2
cores_62/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB1_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB2_tempName`
Numbers of forward move = 0, and backward move = 32
Retimed registers names:
cores_44/backward/currentState_reg[0]_bret__0
cores_44/backward/currentState_reg[0]_bret__1
cores_44/backward/currentState_reg[0]_bret__2
cores_44/backward/currentState_reg[0]_bret__3
cores_44/backward/currentState_reg[0]_bret__4
cores_44/backward/currentState_reg[0]_bret_bret
cores_44/backward/currentState_reg[0]_bret_bret__0
cores_44/backward/currentState_reg[0]_bret_bret__1
cores_44/backward/currentState_reg[0]_bret_bret__2
cores_44/backward/currentState_reg[0]_bret_bret__3
cores_44/backward/currentState_reg[0]_bret_bret__4
cores_44/backward/currentState_reg[1]_bret
cores_44/backward/currentState_reg[1]_bret__1
cores_44/backward/currentState_reg[1]_bret__2
cores_44/backward/currentState_reg[1]_bret__3
cores_44/backward/currentState_reg[2]_bret
cores_44/backward/currentState_reg[2]_bret__1
cores_44/backward/currentState_reg[2]_bret__2
cores_44/backward/currentState_reg[2]_bret__3
cores_44/backward/currentState_reg[3]_bret
cores_44/backward/currentState_reg[3]_bret__1
cores_44/backward/currentState_reg[3]_bret__2
cores_44/backward/currentState_reg[3]_bret__3
cores_44/backward/currentState_reg[4]_bret
cores_44/backward/currentState_reg[4]_bret__1
cores_44/backward/currentState_reg[4]_bret__2
cores_44/backward/currentState_reg[4]_bret__3
cores_44/backward/currentState_reg[5]_bret
cores_44/backward/currentState_reg[5]_bret__0_bret
cores_44/backward/currentState_reg[5]_bret__0_bret__0
cores_44/backward/currentState_reg[5]_bret__0_bret__1
cores_44/backward/currentState_reg[5]_bret__0_bret__2
cores_44/backward/currentState_reg[5]_bret__0_bret__3
cores_44/backward/currentState_reg[5]_bret__0_bret__4
cores_44/backward/currentState_reg[5]_bret__1
cores_44/backward/currentState_reg[5]_bret__2
cores_44/backward/currentState_reg[5]_bret__3
cores_45/backward/currentState_reg[0]_bret__0
cores_45/backward/currentState_reg[0]_bret__1
cores_45/backward/currentState_reg[0]_bret__2
cores_45/backward/currentState_reg[0]_bret__3
cores_45/backward/currentState_reg[0]_bret__4
cores_45/backward/currentState_reg[0]_bret_bret
cores_45/backward/currentState_reg[0]_bret_bret__0
cores_45/backward/currentState_reg[0]_bret_bret__1
cores_45/backward/currentState_reg[0]_bret_bret__2
cores_45/backward/currentState_reg[0]_bret_bret__3
cores_45/backward/currentState_reg[0]_bret_bret__4
cores_45/backward/currentState_reg[1]_bret
cores_45/backward/currentState_reg[1]_bret__1
cores_45/backward/currentState_reg[1]_bret__2
cores_45/backward/currentState_reg[1]_bret__3
cores_45/backward/currentState_reg[2]_bret
cores_45/backward/currentState_reg[2]_bret__1
cores_45/backward/currentState_reg[2]_bret__2
cores_45/backward/currentState_reg[2]_bret__3
cores_45/backward/currentState_reg[3]_bret
cores_45/backward/currentState_reg[3]_bret__1
cores_45/backward/currentState_reg[3]_bret__2
cores_45/backward/currentState_reg[3]_bret__3
cores_45/backward/currentState_reg[4]_bret
cores_45/backward/currentState_reg[4]_bret__1
cores_45/backward/currentState_reg[4]_bret__2
cores_45/backward/currentState_reg[4]_bret__3
cores_45/backward/currentState_reg[5]_bret
cores_45/backward/currentState_reg[5]_bret__0_bret
cores_45/backward/currentState_reg[5]_bret__0_bret__0
cores_45/backward/currentState_reg[5]_bret__0_bret__1
cores_45/backward/currentState_reg[5]_bret__0_bret__2
cores_45/backward/currentState_reg[5]_bret__0_bret__3
cores_45/backward/currentState_reg[5]_bret__0_bret__4
cores_45/backward/currentState_reg[5]_bret__1
cores_45/backward/currentState_reg[5]_bret__2
cores_45/backward/currentState_reg[5]_bret__3
cores_46/backward/currentState_reg[0]_bret__0
cores_46/backward/currentState_reg[0]_bret__1
cores_46/backward/currentState_reg[0]_bret__2
cores_46/backward/currentState_reg[0]_bret__3
cores_46/backward/currentState_reg[0]_bret__4
cores_46/backward/currentState_reg[0]_bret_bret
cores_46/backward/currentState_reg[0]_bret_bret__0
cores_46/backward/currentState_reg[0]_bret_bret__1
cores_46/backward/currentState_reg[0]_bret_bret__2
cores_46/backward/currentState_reg[0]_bret_bret__3
cores_46/backward/currentState_reg[0]_bret_bret__4
cores_46/backward/currentState_reg[1]_bret
cores_46/backward/currentState_reg[1]_bret__1
cores_46/backward/currentState_reg[1]_bret__2
cores_46/backward/currentState_reg[1]_bret__3
cores_46/backward/currentState_reg[2]_bret
cores_46/backward/currentState_reg[2]_bret__1
cores_46/backward/currentState_reg[2]_bret__2
cores_46/backward/currentState_reg[2]_bret__3
cores_46/backward/currentState_reg[3]_bret
cores_46/backward/currentState_reg[3]_bret__1
cores_46/backward/currentState_reg[3]_bret__2
cores_46/backward/currentState_reg[3]_bret__3
cores_46/backward/currentState_reg[4]_bret
cores_46/backward/currentState_reg[4]_bret__1
cores_46/backward/currentState_reg[4]_bret__2
cores_46/backward/currentState_reg[4]_bret__3
cores_46/backward/currentState_reg[5]_bret
cores_46/backward/currentState_reg[5]_bret__0_bret
cores_46/backward/currentState_reg[5]_bret__0_bret__0
cores_46/backward/currentState_reg[5]_bret__0_bret__1
cores_46/backward/currentState_reg[5]_bret__0_bret__2
cores_46/backward/currentState_reg[5]_bret__0_bret__3
cores_46/backward/currentState_reg[5]_bret__0_bret__4
cores_46/backward/currentState_reg[5]_bret__1
cores_46/backward/currentState_reg[5]_bret__2
cores_46/backward/currentState_reg[5]_bret__3
cores_63/backward/currentState_reg[0]_bret__0
cores_63/backward/currentState_reg[0]_bret__1
cores_63/backward/currentState_reg[0]_bret__2
cores_63/backward/currentState_reg[0]_bret__3
cores_63/backward/currentState_reg[0]_bret__4
cores_63/backward/currentState_reg[0]_bret_bret
cores_63/backward/currentState_reg[0]_bret_bret__0
cores_63/backward/currentState_reg[0]_bret_bret__1
cores_63/backward/currentState_reg[0]_bret_bret__2
cores_63/backward/currentState_reg[0]_bret_bret__3
cores_63/backward/currentState_reg[0]_bret_bret__4
cores_63/backward/currentState_reg[1]_bret
cores_63/backward/currentState_reg[1]_bret__1
cores_63/backward/currentState_reg[1]_bret__2
cores_63/backward/currentState_reg[1]_bret__3
cores_63/backward/currentState_reg[2]_bret
cores_63/backward/currentState_reg[2]_bret__1
cores_63/backward/currentState_reg[2]_bret__2
cores_63/backward/currentState_reg[2]_bret__3
cores_63/backward/currentState_reg[3]_bret
cores_63/backward/currentState_reg[3]_bret__1
cores_63/backward/currentState_reg[3]_bret__2
cores_63/backward/currentState_reg[3]_bret__3
cores_63/backward/currentState_reg[4]_bret
cores_63/backward/currentState_reg[4]_bret__1
cores_63/backward/currentState_reg[4]_bret__2
cores_63/backward/currentState_reg[4]_bret__3
cores_63/backward/currentState_reg[5]_bret
cores_63/backward/currentState_reg[5]_bret__0_bret
cores_63/backward/currentState_reg[5]_bret__0_bret__0
cores_63/backward/currentState_reg[5]_bret__0_bret__1
cores_63/backward/currentState_reg[5]_bret__0_bret__2
cores_63/backward/currentState_reg[5]_bret__0_bret__3
cores_63/backward/currentState_reg[5]_bret__0_bret__4
cores_63/backward/currentState_reg[5]_bret__1
cores_63/backward/currentState_reg[5]_bret__2
cores_63/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB2_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB3_tempName`
Numbers of forward move = 0, and backward move = 40
Retimed registers names:
cores_125/backward/currentState_reg[0]_bret__0
cores_125/backward/currentState_reg[0]_bret__1
cores_125/backward/currentState_reg[0]_bret__2
cores_125/backward/currentState_reg[0]_bret__3
cores_125/backward/currentState_reg[0]_bret__4
cores_125/backward/currentState_reg[0]_bret_bret
cores_125/backward/currentState_reg[0]_bret_bret__0
cores_125/backward/currentState_reg[0]_bret_bret__1
cores_125/backward/currentState_reg[0]_bret_bret__2
cores_125/backward/currentState_reg[0]_bret_bret__3
cores_125/backward/currentState_reg[0]_bret_bret__4
cores_125/backward/currentState_reg[1]_bret
cores_125/backward/currentState_reg[1]_bret__1
cores_125/backward/currentState_reg[1]_bret__2
cores_125/backward/currentState_reg[1]_bret__3
cores_125/backward/currentState_reg[2]_bret
cores_125/backward/currentState_reg[2]_bret__1
cores_125/backward/currentState_reg[2]_bret__2
cores_125/backward/currentState_reg[2]_bret__3
cores_125/backward/currentState_reg[3]_bret
cores_125/backward/currentState_reg[3]_bret__1
cores_125/backward/currentState_reg[3]_bret__2
cores_125/backward/currentState_reg[3]_bret__3
cores_125/backward/currentState_reg[4]_bret
cores_125/backward/currentState_reg[4]_bret__1
cores_125/backward/currentState_reg[4]_bret__2
cores_125/backward/currentState_reg[4]_bret__3
cores_125/backward/currentState_reg[5]_bret
cores_125/backward/currentState_reg[5]_bret__0_bret
cores_125/backward/currentState_reg[5]_bret__0_bret__0
cores_125/backward/currentState_reg[5]_bret__0_bret__1
cores_125/backward/currentState_reg[5]_bret__0_bret__2
cores_125/backward/currentState_reg[5]_bret__0_bret__3
cores_125/backward/currentState_reg[5]_bret__0_bret__4
cores_125/backward/currentState_reg[5]_bret__1
cores_125/backward/currentState_reg[5]_bret__2
cores_125/backward/currentState_reg[5]_bret__3
cores_40/backward/currentState_reg[0]_bret__0
cores_40/backward/currentState_reg[0]_bret__1
cores_40/backward/currentState_reg[0]_bret__2
cores_40/backward/currentState_reg[0]_bret__3
cores_40/backward/currentState_reg[0]_bret__4
cores_40/backward/currentState_reg[0]_bret_bret
cores_40/backward/currentState_reg[0]_bret_bret__0
cores_40/backward/currentState_reg[0]_bret_bret__1
cores_40/backward/currentState_reg[0]_bret_bret__2
cores_40/backward/currentState_reg[0]_bret_bret__3
cores_40/backward/currentState_reg[0]_bret_bret__4
cores_40/backward/currentState_reg[1]_bret
cores_40/backward/currentState_reg[1]_bret__1
cores_40/backward/currentState_reg[1]_bret__2
cores_40/backward/currentState_reg[1]_bret__3
cores_40/backward/currentState_reg[2]_bret
cores_40/backward/currentState_reg[2]_bret__1
cores_40/backward/currentState_reg[2]_bret__2
cores_40/backward/currentState_reg[2]_bret__3
cores_40/backward/currentState_reg[3]_bret
cores_40/backward/currentState_reg[3]_bret__1
cores_40/backward/currentState_reg[3]_bret__2
cores_40/backward/currentState_reg[3]_bret__3
cores_40/backward/currentState_reg[4]_bret
cores_40/backward/currentState_reg[4]_bret__1
cores_40/backward/currentState_reg[4]_bret__2
cores_40/backward/currentState_reg[4]_bret__3
cores_40/backward/currentState_reg[5]_bret
cores_40/backward/currentState_reg[5]_bret__0_bret
cores_40/backward/currentState_reg[5]_bret__0_bret__0
cores_40/backward/currentState_reg[5]_bret__0_bret__1
cores_40/backward/currentState_reg[5]_bret__0_bret__2
cores_40/backward/currentState_reg[5]_bret__0_bret__3
cores_40/backward/currentState_reg[5]_bret__0_bret__4
cores_40/backward/currentState_reg[5]_bret__1
cores_40/backward/currentState_reg[5]_bret__2
cores_40/backward/currentState_reg[5]_bret__3
cores_41/backward/currentState_reg[0]_bret__0
cores_41/backward/currentState_reg[0]_bret__1
cores_41/backward/currentState_reg[0]_bret__2
cores_41/backward/currentState_reg[0]_bret__3
cores_41/backward/currentState_reg[0]_bret__4
cores_41/backward/currentState_reg[0]_bret_bret
cores_41/backward/currentState_reg[0]_bret_bret__0
cores_41/backward/currentState_reg[0]_bret_bret__1
cores_41/backward/currentState_reg[0]_bret_bret__2
cores_41/backward/currentState_reg[0]_bret_bret__3
cores_41/backward/currentState_reg[0]_bret_bret__4
cores_41/backward/currentState_reg[1]_bret
cores_41/backward/currentState_reg[1]_bret__1
cores_41/backward/currentState_reg[1]_bret__2
cores_41/backward/currentState_reg[1]_bret__3
cores_41/backward/currentState_reg[2]_bret
cores_41/backward/currentState_reg[2]_bret__1
cores_41/backward/currentState_reg[2]_bret__2
cores_41/backward/currentState_reg[2]_bret__3
cores_41/backward/currentState_reg[3]_bret
cores_41/backward/currentState_reg[3]_bret__1
cores_41/backward/currentState_reg[3]_bret__2
cores_41/backward/currentState_reg[3]_bret__3
cores_41/backward/currentState_reg[4]_bret
cores_41/backward/currentState_reg[4]_bret__1
cores_41/backward/currentState_reg[4]_bret__2
cores_41/backward/currentState_reg[4]_bret__3
cores_41/backward/currentState_reg[5]_bret
cores_41/backward/currentState_reg[5]_bret__0_bret
cores_41/backward/currentState_reg[5]_bret__0_bret__0
cores_41/backward/currentState_reg[5]_bret__0_bret__1
cores_41/backward/currentState_reg[5]_bret__0_bret__2
cores_41/backward/currentState_reg[5]_bret__0_bret__3
cores_41/backward/currentState_reg[5]_bret__0_bret__4
cores_41/backward/currentState_reg[5]_bret__1
cores_41/backward/currentState_reg[5]_bret__2
cores_41/backward/currentState_reg[5]_bret__3
cores_42/backward/currentState_reg[0]_bret__0
cores_42/backward/currentState_reg[0]_bret__1
cores_42/backward/currentState_reg[0]_bret__2
cores_42/backward/currentState_reg[0]_bret__3
cores_42/backward/currentState_reg[0]_bret__4
cores_42/backward/currentState_reg[0]_bret_bret
cores_42/backward/currentState_reg[0]_bret_bret__0
cores_42/backward/currentState_reg[0]_bret_bret__1
cores_42/backward/currentState_reg[0]_bret_bret__2
cores_42/backward/currentState_reg[0]_bret_bret__3
cores_42/backward/currentState_reg[0]_bret_bret__4
cores_42/backward/currentState_reg[1]_bret
cores_42/backward/currentState_reg[1]_bret__1
cores_42/backward/currentState_reg[1]_bret__2
cores_42/backward/currentState_reg[1]_bret__3
cores_42/backward/currentState_reg[2]_bret
cores_42/backward/currentState_reg[2]_bret__1
cores_42/backward/currentState_reg[2]_bret__2
cores_42/backward/currentState_reg[2]_bret__3
cores_42/backward/currentState_reg[3]_bret
cores_42/backward/currentState_reg[3]_bret__1
cores_42/backward/currentState_reg[3]_bret__2
cores_42/backward/currentState_reg[3]_bret__3
cores_42/backward/currentState_reg[4]_bret
cores_42/backward/currentState_reg[4]_bret__1
cores_42/backward/currentState_reg[4]_bret__2
cores_42/backward/currentState_reg[4]_bret__3
cores_42/backward/currentState_reg[5]_bret
cores_42/backward/currentState_reg[5]_bret__0_bret
cores_42/backward/currentState_reg[5]_bret__0_bret__0
cores_42/backward/currentState_reg[5]_bret__0_bret__1
cores_42/backward/currentState_reg[5]_bret__0_bret__2
cores_42/backward/currentState_reg[5]_bret__0_bret__3
cores_42/backward/currentState_reg[5]_bret__0_bret__4
cores_42/backward/currentState_reg[5]_bret__1
cores_42/backward/currentState_reg[5]_bret__2
cores_42/backward/currentState_reg[5]_bret__3
cores_43/backward/currentState_reg[0]_bret__0
cores_43/backward/currentState_reg[0]_bret__1
cores_43/backward/currentState_reg[0]_bret__2
cores_43/backward/currentState_reg[0]_bret__3
cores_43/backward/currentState_reg[0]_bret__4
cores_43/backward/currentState_reg[0]_bret_bret
cores_43/backward/currentState_reg[0]_bret_bret__0
cores_43/backward/currentState_reg[0]_bret_bret__1
cores_43/backward/currentState_reg[0]_bret_bret__2
cores_43/backward/currentState_reg[0]_bret_bret__3
cores_43/backward/currentState_reg[0]_bret_bret__4
cores_43/backward/currentState_reg[1]_bret
cores_43/backward/currentState_reg[1]_bret__1
cores_43/backward/currentState_reg[1]_bret__2
cores_43/backward/currentState_reg[1]_bret__3
cores_43/backward/currentState_reg[2]_bret
cores_43/backward/currentState_reg[2]_bret__1
cores_43/backward/currentState_reg[2]_bret__2
cores_43/backward/currentState_reg[2]_bret__3
cores_43/backward/currentState_reg[3]_bret
cores_43/backward/currentState_reg[3]_bret__1
cores_43/backward/currentState_reg[3]_bret__2
cores_43/backward/currentState_reg[3]_bret__3
cores_43/backward/currentState_reg[4]_bret
cores_43/backward/currentState_reg[4]_bret__1
cores_43/backward/currentState_reg[4]_bret__2
cores_43/backward/currentState_reg[4]_bret__3
cores_43/backward/currentState_reg[5]_bret
cores_43/backward/currentState_reg[5]_bret__0_bret
cores_43/backward/currentState_reg[5]_bret__0_bret__0
cores_43/backward/currentState_reg[5]_bret__0_bret__1
cores_43/backward/currentState_reg[5]_bret__0_bret__2
cores_43/backward/currentState_reg[5]_bret__0_bret__3
cores_43/backward/currentState_reg[5]_bret__0_bret__4
cores_43/backward/currentState_reg[5]_bret__1
cores_43/backward/currentState_reg[5]_bret__2
cores_43/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB3_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-7052] The timing for the instance i_3/cores_40/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_40/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_40/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_40/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_41/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_41/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_41/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_41/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_42/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_42/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_42/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_42/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_43/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_43/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_43/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_3/cores_43/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB4_tempName`
Numbers of forward move = 0, and backward move = 56
Retimed registers names:
cores_126/backward/currentState_reg[0]_bret__0
cores_126/backward/currentState_reg[0]_bret__1
cores_126/backward/currentState_reg[0]_bret__2
cores_126/backward/currentState_reg[0]_bret__3
cores_126/backward/currentState_reg[0]_bret__4
cores_126/backward/currentState_reg[0]_bret_bret
cores_126/backward/currentState_reg[0]_bret_bret__0
cores_126/backward/currentState_reg[0]_bret_bret__1
cores_126/backward/currentState_reg[0]_bret_bret__2
cores_126/backward/currentState_reg[0]_bret_bret__3
cores_126/backward/currentState_reg[0]_bret_bret__4
cores_126/backward/currentState_reg[1]_bret
cores_126/backward/currentState_reg[1]_bret__1
cores_126/backward/currentState_reg[1]_bret__2
cores_126/backward/currentState_reg[1]_bret__3
cores_126/backward/currentState_reg[2]_bret
cores_126/backward/currentState_reg[2]_bret__1
cores_126/backward/currentState_reg[2]_bret__2
cores_126/backward/currentState_reg[2]_bret__3
cores_126/backward/currentState_reg[3]_bret
cores_126/backward/currentState_reg[3]_bret__1
cores_126/backward/currentState_reg[3]_bret__2
cores_126/backward/currentState_reg[3]_bret__3
cores_126/backward/currentState_reg[4]_bret
cores_126/backward/currentState_reg[4]_bret__1
cores_126/backward/currentState_reg[4]_bret__2
cores_126/backward/currentState_reg[4]_bret__3
cores_126/backward/currentState_reg[5]_bret
cores_126/backward/currentState_reg[5]_bret__0_bret
cores_126/backward/currentState_reg[5]_bret__0_bret__0
cores_126/backward/currentState_reg[5]_bret__0_bret__1
cores_126/backward/currentState_reg[5]_bret__0_bret__2
cores_126/backward/currentState_reg[5]_bret__0_bret__3
cores_126/backward/currentState_reg[5]_bret__0_bret__4
cores_126/backward/currentState_reg[5]_bret__1
cores_126/backward/currentState_reg[5]_bret__2
cores_126/backward/currentState_reg[5]_bret__3
cores_34/backward/currentState_reg[0]_bret__0
cores_34/backward/currentState_reg[0]_bret__1
cores_34/backward/currentState_reg[0]_bret__2
cores_34/backward/currentState_reg[0]_bret__3
cores_34/backward/currentState_reg[0]_bret__4
cores_34/backward/currentState_reg[0]_bret_bret
cores_34/backward/currentState_reg[0]_bret_bret__0
cores_34/backward/currentState_reg[0]_bret_bret__1
cores_34/backward/currentState_reg[0]_bret_bret__2
cores_34/backward/currentState_reg[0]_bret_bret__3
cores_34/backward/currentState_reg[0]_bret_bret__4
cores_34/backward/currentState_reg[1]_bret
cores_34/backward/currentState_reg[1]_bret__1
cores_34/backward/currentState_reg[1]_bret__2
cores_34/backward/currentState_reg[1]_bret__3
cores_34/backward/currentState_reg[2]_bret
cores_34/backward/currentState_reg[2]_bret__1
cores_34/backward/currentState_reg[2]_bret__2
cores_34/backward/currentState_reg[2]_bret__3
cores_34/backward/currentState_reg[3]_bret
cores_34/backward/currentState_reg[3]_bret__1
cores_34/backward/currentState_reg[3]_bret__2
cores_34/backward/currentState_reg[3]_bret__3
cores_34/backward/currentState_reg[4]_bret
cores_34/backward/currentState_reg[4]_bret__1
cores_34/backward/currentState_reg[4]_bret__2
cores_34/backward/currentState_reg[4]_bret__3
cores_34/backward/currentState_reg[5]_bret
cores_34/backward/currentState_reg[5]_bret__0_bret
cores_34/backward/currentState_reg[5]_bret__0_bret__0
cores_34/backward/currentState_reg[5]_bret__0_bret__1
cores_34/backward/currentState_reg[5]_bret__0_bret__2
cores_34/backward/currentState_reg[5]_bret__0_bret__3
cores_34/backward/currentState_reg[5]_bret__0_bret__4
cores_34/backward/currentState_reg[5]_bret__1
cores_34/backward/currentState_reg[5]_bret__2
cores_34/backward/currentState_reg[5]_bret__3
cores_35/backward/currentState_reg[0]_bret__0
cores_35/backward/currentState_reg[0]_bret__1
cores_35/backward/currentState_reg[0]_bret__2
cores_35/backward/currentState_reg[0]_bret__3
cores_35/backward/currentState_reg[0]_bret__4
cores_35/backward/currentState_reg[0]_bret_bret
cores_35/backward/currentState_reg[0]_bret_bret__0
cores_35/backward/currentState_reg[0]_bret_bret__1
cores_35/backward/currentState_reg[0]_bret_bret__2
cores_35/backward/currentState_reg[0]_bret_bret__3
cores_35/backward/currentState_reg[0]_bret_bret__4
cores_35/backward/currentState_reg[1]_bret
cores_35/backward/currentState_reg[1]_bret__1
cores_35/backward/currentState_reg[1]_bret__2
cores_35/backward/currentState_reg[1]_bret__3
cores_35/backward/currentState_reg[2]_bret
cores_35/backward/currentState_reg[2]_bret__1
cores_35/backward/currentState_reg[2]_bret__2
cores_35/backward/currentState_reg[2]_bret__3
cores_35/backward/currentState_reg[3]_bret
cores_35/backward/currentState_reg[3]_bret__1
cores_35/backward/currentState_reg[3]_bret__2
cores_35/backward/currentState_reg[3]_bret__3
cores_35/backward/currentState_reg[4]_bret
cores_35/backward/currentState_reg[4]_bret__1
cores_35/backward/currentState_reg[4]_bret__2
cores_35/backward/currentState_reg[4]_bret__3
cores_35/backward/currentState_reg[5]_bret
cores_35/backward/currentState_reg[5]_bret__0_bret
cores_35/backward/currentState_reg[5]_bret__0_bret__0
cores_35/backward/currentState_reg[5]_bret__0_bret__1
cores_35/backward/currentState_reg[5]_bret__0_bret__2
cores_35/backward/currentState_reg[5]_bret__0_bret__3
cores_35/backward/currentState_reg[5]_bret__0_bret__4
cores_35/backward/currentState_reg[5]_bret__1
cores_35/backward/currentState_reg[5]_bret__2
cores_35/backward/currentState_reg[5]_bret__3
cores_36/backward/currentState_reg[0]_bret__0
cores_36/backward/currentState_reg[0]_bret__1
cores_36/backward/currentState_reg[0]_bret__2
cores_36/backward/currentState_reg[0]_bret__3
cores_36/backward/currentState_reg[0]_bret__4
cores_36/backward/currentState_reg[0]_bret_bret
cores_36/backward/currentState_reg[0]_bret_bret__0
cores_36/backward/currentState_reg[0]_bret_bret__1
cores_36/backward/currentState_reg[0]_bret_bret__2
cores_36/backward/currentState_reg[0]_bret_bret__3
cores_36/backward/currentState_reg[0]_bret_bret__4
cores_36/backward/currentState_reg[1]_bret
cores_36/backward/currentState_reg[1]_bret__1
cores_36/backward/currentState_reg[1]_bret__2
cores_36/backward/currentState_reg[1]_bret__3
cores_36/backward/currentState_reg[2]_bret
cores_36/backward/currentState_reg[2]_bret__1
cores_36/backward/currentState_reg[2]_bret__2
cores_36/backward/currentState_reg[2]_bret__3
cores_36/backward/currentState_reg[3]_bret
cores_36/backward/currentState_reg[3]_bret__1
cores_36/backward/currentState_reg[3]_bret__2
cores_36/backward/currentState_reg[3]_bret__3
cores_36/backward/currentState_reg[4]_bret
cores_36/backward/currentState_reg[4]_bret__1
cores_36/backward/currentState_reg[4]_bret__2
cores_36/backward/currentState_reg[4]_bret__3
cores_36/backward/currentState_reg[5]_bret
cores_36/backward/currentState_reg[5]_bret__0_bret
cores_36/backward/currentState_reg[5]_bret__0_bret__0
cores_36/backward/currentState_reg[5]_bret__0_bret__1
cores_36/backward/currentState_reg[5]_bret__0_bret__2
cores_36/backward/currentState_reg[5]_bret__0_bret__3
cores_36/backward/currentState_reg[5]_bret__0_bret__4
cores_36/backward/currentState_reg[5]_bret__1
cores_36/backward/currentState_reg[5]_bret__2
cores_36/backward/currentState_reg[5]_bret__3
cores_37/backward/currentState_reg[0]_bret__0
cores_37/backward/currentState_reg[0]_bret__1
cores_37/backward/currentState_reg[0]_bret__2
cores_37/backward/currentState_reg[0]_bret__3
cores_37/backward/currentState_reg[0]_bret__4
cores_37/backward/currentState_reg[0]_bret_bret
cores_37/backward/currentState_reg[0]_bret_bret__0
cores_37/backward/currentState_reg[0]_bret_bret__1
cores_37/backward/currentState_reg[0]_bret_bret__2
cores_37/backward/currentState_reg[0]_bret_bret__3
cores_37/backward/currentState_reg[0]_bret_bret__4
cores_37/backward/currentState_reg[1]_bret
cores_37/backward/currentState_reg[1]_bret__1
cores_37/backward/currentState_reg[1]_bret__2
cores_37/backward/currentState_reg[1]_bret__3
cores_37/backward/currentState_reg[2]_bret
cores_37/backward/currentState_reg[2]_bret__1
cores_37/backward/currentState_reg[2]_bret__2
cores_37/backward/currentState_reg[2]_bret__3
cores_37/backward/currentState_reg[3]_bret
cores_37/backward/currentState_reg[3]_bret__1
cores_37/backward/currentState_reg[3]_bret__2
cores_37/backward/currentState_reg[3]_bret__3
cores_37/backward/currentState_reg[4]_bret
cores_37/backward/currentState_reg[4]_bret__1
cores_37/backward/currentState_reg[4]_bret__2
cores_37/backward/currentState_reg[4]_bret__3
cores_37/backward/currentState_reg[5]_bret
cores_37/backward/currentState_reg[5]_bret__0_bret
cores_37/backward/currentState_reg[5]_bret__0_bret__0
cores_37/backward/currentState_reg[5]_bret__0_bret__1
cores_37/backward/currentState_reg[5]_bret__0_bret__2
cores_37/backward/currentState_reg[5]_bret__0_bret__3
cores_37/backward/currentState_reg[5]_bret__0_bret__4
cores_37/backward/currentState_reg[5]_bret__1
cores_37/backward/currentState_reg[5]_bret__2
cores_37/backward/currentState_reg[5]_bret__3
cores_38/backward/currentState_reg[0]_bret__0
cores_38/backward/currentState_reg[0]_bret__1
cores_38/backward/currentState_reg[0]_bret__2
cores_38/backward/currentState_reg[0]_bret__3
cores_38/backward/currentState_reg[0]_bret__4
cores_38/backward/currentState_reg[0]_bret_bret
cores_38/backward/currentState_reg[0]_bret_bret__0
cores_38/backward/currentState_reg[0]_bret_bret__1
cores_38/backward/currentState_reg[0]_bret_bret__2
cores_38/backward/currentState_reg[0]_bret_bret__3
cores_38/backward/currentState_reg[0]_bret_bret__4
cores_38/backward/currentState_reg[1]_bret
cores_38/backward/currentState_reg[1]_bret__1
cores_38/backward/currentState_reg[1]_bret__2
cores_38/backward/currentState_reg[1]_bret__3
cores_38/backward/currentState_reg[2]_bret
cores_38/backward/currentState_reg[2]_bret__1
cores_38/backward/currentState_reg[2]_bret__2
cores_38/backward/currentState_reg[2]_bret__3
cores_38/backward/currentState_reg[3]_bret
cores_38/backward/currentState_reg[3]_bret__1
cores_38/backward/currentState_reg[3]_bret__2
cores_38/backward/currentState_reg[3]_bret__3
cores_38/backward/currentState_reg[4]_bret
cores_38/backward/currentState_reg[4]_bret__1
cores_38/backward/currentState_reg[4]_bret__2
cores_38/backward/currentState_reg[4]_bret__3
cores_38/backward/currentState_reg[5]_bret
cores_38/backward/currentState_reg[5]_bret__0_bret
cores_38/backward/currentState_reg[5]_bret__0_bret__0
cores_38/backward/currentState_reg[5]_bret__0_bret__1
cores_38/backward/currentState_reg[5]_bret__0_bret__2
cores_38/backward/currentState_reg[5]_bret__0_bret__3
cores_38/backward/currentState_reg[5]_bret__0_bret__4
cores_38/backward/currentState_reg[5]_bret__1
cores_38/backward/currentState_reg[5]_bret__2
cores_38/backward/currentState_reg[5]_bret__3
cores_39/backward/currentState_reg[0]_bret__0
cores_39/backward/currentState_reg[0]_bret__1
cores_39/backward/currentState_reg[0]_bret__2
cores_39/backward/currentState_reg[0]_bret__3
cores_39/backward/currentState_reg[0]_bret__4
cores_39/backward/currentState_reg[0]_bret_bret
cores_39/backward/currentState_reg[0]_bret_bret__0
cores_39/backward/currentState_reg[0]_bret_bret__1
cores_39/backward/currentState_reg[0]_bret_bret__2
cores_39/backward/currentState_reg[0]_bret_bret__3
cores_39/backward/currentState_reg[0]_bret_bret__4
cores_39/backward/currentState_reg[1]_bret
cores_39/backward/currentState_reg[1]_bret__1
cores_39/backward/currentState_reg[1]_bret__2
cores_39/backward/currentState_reg[1]_bret__3
cores_39/backward/currentState_reg[2]_bret
cores_39/backward/currentState_reg[2]_bret__1
cores_39/backward/currentState_reg[2]_bret__2
cores_39/backward/currentState_reg[2]_bret__3
cores_39/backward/currentState_reg[3]_bret
cores_39/backward/currentState_reg[3]_bret__1
cores_39/backward/currentState_reg[3]_bret__2
cores_39/backward/currentState_reg[3]_bret__3
cores_39/backward/currentState_reg[4]_bret
cores_39/backward/currentState_reg[4]_bret__1
cores_39/backward/currentState_reg[4]_bret__2
cores_39/backward/currentState_reg[4]_bret__3
cores_39/backward/currentState_reg[5]_bret
cores_39/backward/currentState_reg[5]_bret__0_bret
cores_39/backward/currentState_reg[5]_bret__0_bret__0
cores_39/backward/currentState_reg[5]_bret__0_bret__1
cores_39/backward/currentState_reg[5]_bret__0_bret__2
cores_39/backward/currentState_reg[5]_bret__0_bret__3
cores_39/backward/currentState_reg[5]_bret__0_bret__4
cores_39/backward/currentState_reg[5]_bret__1
cores_39/backward/currentState_reg[5]_bret__2
cores_39/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB4_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-7052] The timing for the instance i_4/cores_39/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_39/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_39/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_39/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_38/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_38/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_38/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_38/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_37/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_37/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_37/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_37/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_36/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_36/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_36/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_36/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_35/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_35/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_35/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_4/cores_35/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB5_tempName`
Numbers of forward move = 0, and backward move = 72
Retimed registers names:
cores_25/backward/currentState_reg[0]_bret__0
cores_25/backward/currentState_reg[0]_bret__1
cores_25/backward/currentState_reg[0]_bret__2
cores_25/backward/currentState_reg[0]_bret__3
cores_25/backward/currentState_reg[0]_bret__4
cores_25/backward/currentState_reg[0]_bret_bret
cores_25/backward/currentState_reg[0]_bret_bret__0
cores_25/backward/currentState_reg[0]_bret_bret__1
cores_25/backward/currentState_reg[0]_bret_bret__2
cores_25/backward/currentState_reg[0]_bret_bret__3
cores_25/backward/currentState_reg[0]_bret_bret__4
cores_25/backward/currentState_reg[1]_bret
cores_25/backward/currentState_reg[1]_bret__1
cores_25/backward/currentState_reg[1]_bret__2
cores_25/backward/currentState_reg[1]_bret__3
cores_25/backward/currentState_reg[2]_bret
cores_25/backward/currentState_reg[2]_bret__1
cores_25/backward/currentState_reg[2]_bret__2
cores_25/backward/currentState_reg[2]_bret__3
cores_25/backward/currentState_reg[3]_bret
cores_25/backward/currentState_reg[3]_bret__1
cores_25/backward/currentState_reg[3]_bret__2
cores_25/backward/currentState_reg[3]_bret__3
cores_25/backward/currentState_reg[4]_bret
cores_25/backward/currentState_reg[4]_bret__1
cores_25/backward/currentState_reg[4]_bret__2
cores_25/backward/currentState_reg[4]_bret__3
cores_25/backward/currentState_reg[5]_bret
cores_25/backward/currentState_reg[5]_bret__0_bret
cores_25/backward/currentState_reg[5]_bret__0_bret__0
cores_25/backward/currentState_reg[5]_bret__0_bret__1
cores_25/backward/currentState_reg[5]_bret__0_bret__2
cores_25/backward/currentState_reg[5]_bret__0_bret__3
cores_25/backward/currentState_reg[5]_bret__0_bret__4
cores_25/backward/currentState_reg[5]_bret__1
cores_25/backward/currentState_reg[5]_bret__2
cores_25/backward/currentState_reg[5]_bret__3
cores_27/backward/currentState_reg[0]_bret__0
cores_27/backward/currentState_reg[0]_bret__1
cores_27/backward/currentState_reg[0]_bret__2
cores_27/backward/currentState_reg[0]_bret__3
cores_27/backward/currentState_reg[0]_bret__4
cores_27/backward/currentState_reg[0]_bret_bret
cores_27/backward/currentState_reg[0]_bret_bret__0
cores_27/backward/currentState_reg[0]_bret_bret__1
cores_27/backward/currentState_reg[0]_bret_bret__2
cores_27/backward/currentState_reg[0]_bret_bret__3
cores_27/backward/currentState_reg[0]_bret_bret__4
cores_27/backward/currentState_reg[1]_bret
cores_27/backward/currentState_reg[1]_bret__1
cores_27/backward/currentState_reg[1]_bret__2
cores_27/backward/currentState_reg[1]_bret__3
cores_27/backward/currentState_reg[2]_bret
cores_27/backward/currentState_reg[2]_bret__1
cores_27/backward/currentState_reg[2]_bret__2
cores_27/backward/currentState_reg[2]_bret__3
cores_27/backward/currentState_reg[3]_bret
cores_27/backward/currentState_reg[3]_bret__1
cores_27/backward/currentState_reg[3]_bret__2
cores_27/backward/currentState_reg[3]_bret__3
cores_27/backward/currentState_reg[4]_bret
cores_27/backward/currentState_reg[4]_bret__1
cores_27/backward/currentState_reg[4]_bret__2
cores_27/backward/currentState_reg[4]_bret__3
cores_27/backward/currentState_reg[5]_bret
cores_27/backward/currentState_reg[5]_bret__0_bret
cores_27/backward/currentState_reg[5]_bret__0_bret__0
cores_27/backward/currentState_reg[5]_bret__0_bret__1
cores_27/backward/currentState_reg[5]_bret__0_bret__2
cores_27/backward/currentState_reg[5]_bret__0_bret__3
cores_27/backward/currentState_reg[5]_bret__0_bret__4
cores_27/backward/currentState_reg[5]_bret__1
cores_27/backward/currentState_reg[5]_bret__2
cores_27/backward/currentState_reg[5]_bret__3
cores_28/backward/currentState_reg[0]_bret__0
cores_28/backward/currentState_reg[0]_bret__1
cores_28/backward/currentState_reg[0]_bret__2
cores_28/backward/currentState_reg[0]_bret__3
cores_28/backward/currentState_reg[0]_bret__4
cores_28/backward/currentState_reg[0]_bret_bret
cores_28/backward/currentState_reg[0]_bret_bret__0
cores_28/backward/currentState_reg[0]_bret_bret__1
cores_28/backward/currentState_reg[0]_bret_bret__2
cores_28/backward/currentState_reg[0]_bret_bret__3
cores_28/backward/currentState_reg[0]_bret_bret__4
cores_28/backward/currentState_reg[1]_bret
cores_28/backward/currentState_reg[1]_bret__1
cores_28/backward/currentState_reg[1]_bret__2
cores_28/backward/currentState_reg[1]_bret__3
cores_28/backward/currentState_reg[2]_bret
cores_28/backward/currentState_reg[2]_bret__1
cores_28/backward/currentState_reg[2]_bret__2
cores_28/backward/currentState_reg[2]_bret__3
cores_28/backward/currentState_reg[3]_bret
cores_28/backward/currentState_reg[3]_bret__1
cores_28/backward/currentState_reg[3]_bret__2
cores_28/backward/currentState_reg[3]_bret__3
cores_28/backward/currentState_reg[4]_bret
cores_28/backward/currentState_reg[4]_bret__1
cores_28/backward/currentState_reg[4]_bret__2
cores_28/backward/currentState_reg[4]_bret__3
cores_28/backward/currentState_reg[5]_bret
cores_28/backward/currentState_reg[5]_bret__0_bret
cores_28/backward/currentState_reg[5]_bret__0_bret__0
cores_28/backward/currentState_reg[5]_bret__0_bret__1
cores_28/backward/currentState_reg[5]_bret__0_bret__2
cores_28/backward/currentState_reg[5]_bret__0_bret__3
cores_28/backward/currentState_reg[5]_bret__0_bret__4
cores_28/backward/currentState_reg[5]_bret__1
cores_28/backward/currentState_reg[5]_bret__2
cores_28/backward/currentState_reg[5]_bret__3
cores_29/backward/currentState_reg[0]_bret__0
cores_29/backward/currentState_reg[0]_bret__1
cores_29/backward/currentState_reg[0]_bret__2
cores_29/backward/currentState_reg[0]_bret__3
cores_29/backward/currentState_reg[0]_bret__4
cores_29/backward/currentState_reg[0]_bret_bret
cores_29/backward/currentState_reg[0]_bret_bret__0
cores_29/backward/currentState_reg[0]_bret_bret__1
cores_29/backward/currentState_reg[0]_bret_bret__2
cores_29/backward/currentState_reg[0]_bret_bret__3
cores_29/backward/currentState_reg[0]_bret_bret__4
cores_29/backward/currentState_reg[1]_bret
cores_29/backward/currentState_reg[1]_bret__1
cores_29/backward/currentState_reg[1]_bret__2
cores_29/backward/currentState_reg[1]_bret__3
cores_29/backward/currentState_reg[2]_bret
cores_29/backward/currentState_reg[2]_bret__1
cores_29/backward/currentState_reg[2]_bret__2
cores_29/backward/currentState_reg[2]_bret__3
cores_29/backward/currentState_reg[3]_bret
cores_29/backward/currentState_reg[3]_bret__1
cores_29/backward/currentState_reg[3]_bret__2
cores_29/backward/currentState_reg[3]_bret__3
cores_29/backward/currentState_reg[4]_bret
cores_29/backward/currentState_reg[4]_bret__1
cores_29/backward/currentState_reg[4]_bret__2
cores_29/backward/currentState_reg[4]_bret__3
cores_29/backward/currentState_reg[5]_bret
cores_29/backward/currentState_reg[5]_bret__0_bret
cores_29/backward/currentState_reg[5]_bret__0_bret__0
cores_29/backward/currentState_reg[5]_bret__0_bret__1
cores_29/backward/currentState_reg[5]_bret__0_bret__2
cores_29/backward/currentState_reg[5]_bret__0_bret__3
cores_29/backward/currentState_reg[5]_bret__0_bret__4
cores_29/backward/currentState_reg[5]_bret__1
cores_29/backward/currentState_reg[5]_bret__2
cores_29/backward/currentState_reg[5]_bret__3
cores_30/backward/currentState_reg[0]_bret__0
cores_30/backward/currentState_reg[0]_bret__1
cores_30/backward/currentState_reg[0]_bret__2
cores_30/backward/currentState_reg[0]_bret__3
cores_30/backward/currentState_reg[0]_bret__4
cores_30/backward/currentState_reg[0]_bret_bret
cores_30/backward/currentState_reg[0]_bret_bret__0
cores_30/backward/currentState_reg[0]_bret_bret__1
cores_30/backward/currentState_reg[0]_bret_bret__2
cores_30/backward/currentState_reg[0]_bret_bret__3
cores_30/backward/currentState_reg[0]_bret_bret__4
cores_30/backward/currentState_reg[1]_bret
cores_30/backward/currentState_reg[1]_bret__1
cores_30/backward/currentState_reg[1]_bret__2
cores_30/backward/currentState_reg[1]_bret__3
cores_30/backward/currentState_reg[2]_bret
cores_30/backward/currentState_reg[2]_bret__1
cores_30/backward/currentState_reg[2]_bret__2
cores_30/backward/currentState_reg[2]_bret__3
cores_30/backward/currentState_reg[3]_bret
cores_30/backward/currentState_reg[3]_bret__1
cores_30/backward/currentState_reg[3]_bret__2
cores_30/backward/currentState_reg[3]_bret__3
cores_30/backward/currentState_reg[4]_bret
cores_30/backward/currentState_reg[4]_bret__1
cores_30/backward/currentState_reg[4]_bret__2
cores_30/backward/currentState_reg[4]_bret__3
cores_30/backward/currentState_reg[5]_bret
cores_30/backward/currentState_reg[5]_bret__0_bret
cores_30/backward/currentState_reg[5]_bret__0_bret__0
cores_30/backward/currentState_reg[5]_bret__0_bret__1
cores_30/backward/currentState_reg[5]_bret__0_bret__2
cores_30/backward/currentState_reg[5]_bret__0_bret__3
cores_30/backward/currentState_reg[5]_bret__0_bret__4
cores_30/backward/currentState_reg[5]_bret__1
cores_30/backward/currentState_reg[5]_bret__2
cores_30/backward/currentState_reg[5]_bret__3
cores_31/backward/currentState_reg[0]_bret__0
cores_31/backward/currentState_reg[0]_bret__1
cores_31/backward/currentState_reg[0]_bret__2
cores_31/backward/currentState_reg[0]_bret__3
cores_31/backward/currentState_reg[0]_bret__4
cores_31/backward/currentState_reg[0]_bret_bret
cores_31/backward/currentState_reg[0]_bret_bret__0
cores_31/backward/currentState_reg[0]_bret_bret__1
cores_31/backward/currentState_reg[0]_bret_bret__2
cores_31/backward/currentState_reg[0]_bret_bret__3
cores_31/backward/currentState_reg[0]_bret_bret__4
cores_31/backward/currentState_reg[1]_bret
cores_31/backward/currentState_reg[1]_bret__1
cores_31/backward/currentState_reg[1]_bret__2
cores_31/backward/currentState_reg[1]_bret__3
cores_31/backward/currentState_reg[2]_bret
cores_31/backward/currentState_reg[2]_bret__1
cores_31/backward/currentState_reg[2]_bret__2
cores_31/backward/currentState_reg[2]_bret__3
cores_31/backward/currentState_reg[3]_bret
cores_31/backward/currentState_reg[3]_bret__1
cores_31/backward/currentState_reg[3]_bret__2
cores_31/backward/currentState_reg[3]_bret__3
cores_31/backward/currentState_reg[4]_bret
cores_31/backward/currentState_reg[4]_bret__1
cores_31/backward/currentState_reg[4]_bret__2
cores_31/backward/currentState_reg[4]_bret__3
cores_31/backward/currentState_reg[5]_bret
cores_31/backward/currentState_reg[5]_bret__0_bret
cores_31/backward/currentState_reg[5]_bret__0_bret__0
cores_31/backward/currentState_reg[5]_bret__0_bret__1
cores_31/backward/currentState_reg[5]_bret__0_bret__2
cores_31/backward/currentState_reg[5]_bret__0_bret__3
cores_31/backward/currentState_reg[5]_bret__0_bret__4
cores_31/backward/currentState_reg[5]_bret__1
cores_31/backward/currentState_reg[5]_bret__2
cores_31/backward/currentState_reg[5]_bret__3
cores_32/backward/currentState_reg[0]_bret__0
cores_32/backward/currentState_reg[0]_bret__1
cores_32/backward/currentState_reg[0]_bret__2
cores_32/backward/currentState_reg[0]_bret__3
cores_32/backward/currentState_reg[0]_bret__4
cores_32/backward/currentState_reg[0]_bret_bret
cores_32/backward/currentState_reg[0]_bret_bret__0
cores_32/backward/currentState_reg[0]_bret_bret__1
cores_32/backward/currentState_reg[0]_bret_bret__2
cores_32/backward/currentState_reg[0]_bret_bret__3
cores_32/backward/currentState_reg[0]_bret_bret__4
cores_32/backward/currentState_reg[1]_bret
cores_32/backward/currentState_reg[1]_bret__1
cores_32/backward/currentState_reg[1]_bret__2
cores_32/backward/currentState_reg[1]_bret__3
cores_32/backward/currentState_reg[2]_bret
cores_32/backward/currentState_reg[2]_bret__1
cores_32/backward/currentState_reg[2]_bret__2
cores_32/backward/currentState_reg[2]_bret__3
cores_32/backward/currentState_reg[3]_bret
cores_32/backward/currentState_reg[3]_bret__1
cores_32/backward/currentState_reg[3]_bret__2
cores_32/backward/currentState_reg[3]_bret__3
cores_32/backward/currentState_reg[4]_bret
cores_32/backward/currentState_reg[4]_bret__1
cores_32/backward/currentState_reg[4]_bret__2
cores_32/backward/currentState_reg[4]_bret__3
cores_32/backward/currentState_reg[5]_bret
cores_32/backward/currentState_reg[5]_bret__0_bret
cores_32/backward/currentState_reg[5]_bret__0_bret__0
cores_32/backward/currentState_reg[5]_bret__0_bret__1
cores_32/backward/currentState_reg[5]_bret__0_bret__2
cores_32/backward/currentState_reg[5]_bret__0_bret__3
cores_32/backward/currentState_reg[5]_bret__0_bret__4
cores_32/backward/currentState_reg[5]_bret__1
cores_32/backward/currentState_reg[5]_bret__2
cores_32/backward/currentState_reg[5]_bret__3
cores_33/backward/currentState_reg[0]_bret__0
cores_33/backward/currentState_reg[0]_bret__1
cores_33/backward/currentState_reg[0]_bret__2
cores_33/backward/currentState_reg[0]_bret__3
cores_33/backward/currentState_reg[0]_bret__4
cores_33/backward/currentState_reg[0]_bret_bret
cores_33/backward/currentState_reg[0]_bret_bret__0
cores_33/backward/currentState_reg[0]_bret_bret__1
cores_33/backward/currentState_reg[0]_bret_bret__2
cores_33/backward/currentState_reg[0]_bret_bret__3
cores_33/backward/currentState_reg[0]_bret_bret__4
cores_33/backward/currentState_reg[1]_bret
cores_33/backward/currentState_reg[1]_bret__1
cores_33/backward/currentState_reg[1]_bret__2
cores_33/backward/currentState_reg[1]_bret__3
cores_33/backward/currentState_reg[2]_bret
cores_33/backward/currentState_reg[2]_bret__1
cores_33/backward/currentState_reg[2]_bret__2
cores_33/backward/currentState_reg[2]_bret__3
cores_33/backward/currentState_reg[3]_bret
cores_33/backward/currentState_reg[3]_bret__1
cores_33/backward/currentState_reg[3]_bret__2
cores_33/backward/currentState_reg[3]_bret__3
cores_33/backward/currentState_reg[4]_bret
cores_33/backward/currentState_reg[4]_bret__1
cores_33/backward/currentState_reg[4]_bret__2
cores_33/backward/currentState_reg[4]_bret__3
cores_33/backward/currentState_reg[5]_bret
cores_33/backward/currentState_reg[5]_bret__0_bret
cores_33/backward/currentState_reg[5]_bret__0_bret__0
cores_33/backward/currentState_reg[5]_bret__0_bret__1
cores_33/backward/currentState_reg[5]_bret__0_bret__2
cores_33/backward/currentState_reg[5]_bret__0_bret__3
cores_33/backward/currentState_reg[5]_bret__0_bret__4
cores_33/backward/currentState_reg[5]_bret__1
cores_33/backward/currentState_reg[5]_bret__2
cores_33/backward/currentState_reg[5]_bret__3
cores_48/backward/currentState_reg[0]_bret__0
cores_48/backward/currentState_reg[0]_bret__1
cores_48/backward/currentState_reg[0]_bret__2
cores_48/backward/currentState_reg[0]_bret__3
cores_48/backward/currentState_reg[0]_bret__4
cores_48/backward/currentState_reg[0]_bret_bret
cores_48/backward/currentState_reg[0]_bret_bret__0
cores_48/backward/currentState_reg[0]_bret_bret__1
cores_48/backward/currentState_reg[0]_bret_bret__2
cores_48/backward/currentState_reg[0]_bret_bret__3
cores_48/backward/currentState_reg[0]_bret_bret__4
cores_48/backward/currentState_reg[1]_bret
cores_48/backward/currentState_reg[1]_bret__1
cores_48/backward/currentState_reg[1]_bret__2
cores_48/backward/currentState_reg[1]_bret__3
cores_48/backward/currentState_reg[2]_bret
cores_48/backward/currentState_reg[2]_bret__1
cores_48/backward/currentState_reg[2]_bret__2
cores_48/backward/currentState_reg[2]_bret__3
cores_48/backward/currentState_reg[3]_bret
cores_48/backward/currentState_reg[3]_bret__1
cores_48/backward/currentState_reg[3]_bret__2
cores_48/backward/currentState_reg[3]_bret__3
cores_48/backward/currentState_reg[4]_bret
cores_48/backward/currentState_reg[4]_bret__1
cores_48/backward/currentState_reg[4]_bret__2
cores_48/backward/currentState_reg[4]_bret__3
cores_48/backward/currentState_reg[5]_bret
cores_48/backward/currentState_reg[5]_bret__0_bret
cores_48/backward/currentState_reg[5]_bret__0_bret__0
cores_48/backward/currentState_reg[5]_bret__0_bret__1
cores_48/backward/currentState_reg[5]_bret__0_bret__2
cores_48/backward/currentState_reg[5]_bret__0_bret__3
cores_48/backward/currentState_reg[5]_bret__0_bret__4
cores_48/backward/currentState_reg[5]_bret__1
cores_48/backward/currentState_reg[5]_bret__2
cores_48/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB5_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-7052] The timing for the instance i_5/cores_48/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_48/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_48/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_48/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_33/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_33/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_33/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_33/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_32/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_32/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_32/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_32/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_31/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_31/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_31/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_31/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_30/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_30/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_30/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_30/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_29/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_29/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_29/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_29/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_28/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_28/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_28/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_28/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_27/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_27/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_27/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_27/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_25/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_25/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_25/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_5/cores_25/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB6_tempName`
Numbers of forward move = 0, and backward move = 88
Retimed registers names:
cores_15/backward/currentState_reg[0]_bret__0
cores_15/backward/currentState_reg[0]_bret__1
cores_15/backward/currentState_reg[0]_bret__2
cores_15/backward/currentState_reg[0]_bret__3
cores_15/backward/currentState_reg[0]_bret__4
cores_15/backward/currentState_reg[0]_bret_bret
cores_15/backward/currentState_reg[0]_bret_bret__0
cores_15/backward/currentState_reg[0]_bret_bret__1
cores_15/backward/currentState_reg[0]_bret_bret__2
cores_15/backward/currentState_reg[0]_bret_bret__3
cores_15/backward/currentState_reg[0]_bret_bret__4
cores_15/backward/currentState_reg[1]_bret
cores_15/backward/currentState_reg[1]_bret__1
cores_15/backward/currentState_reg[1]_bret__2
cores_15/backward/currentState_reg[1]_bret__3
cores_15/backward/currentState_reg[2]_bret
cores_15/backward/currentState_reg[2]_bret__1
cores_15/backward/currentState_reg[2]_bret__2
cores_15/backward/currentState_reg[2]_bret__3
cores_15/backward/currentState_reg[3]_bret
cores_15/backward/currentState_reg[3]_bret__1
cores_15/backward/currentState_reg[3]_bret__2
cores_15/backward/currentState_reg[3]_bret__3
cores_15/backward/currentState_reg[4]_bret
cores_15/backward/currentState_reg[4]_bret__1
cores_15/backward/currentState_reg[4]_bret__2
cores_15/backward/currentState_reg[4]_bret__3
cores_15/backward/currentState_reg[5]_bret
cores_15/backward/currentState_reg[5]_bret__0_bret
cores_15/backward/currentState_reg[5]_bret__0_bret__0
cores_15/backward/currentState_reg[5]_bret__0_bret__1
cores_15/backward/currentState_reg[5]_bret__0_bret__2
cores_15/backward/currentState_reg[5]_bret__0_bret__3
cores_15/backward/currentState_reg[5]_bret__0_bret__4
cores_15/backward/currentState_reg[5]_bret__1
cores_15/backward/currentState_reg[5]_bret__2
cores_15/backward/currentState_reg[5]_bret__3
cores_16/backward/currentState_reg[0]_bret__0
cores_16/backward/currentState_reg[0]_bret__1
cores_16/backward/currentState_reg[0]_bret__2
cores_16/backward/currentState_reg[0]_bret__3
cores_16/backward/currentState_reg[0]_bret__4
cores_16/backward/currentState_reg[0]_bret_bret
cores_16/backward/currentState_reg[0]_bret_bret__0
cores_16/backward/currentState_reg[0]_bret_bret__1
cores_16/backward/currentState_reg[0]_bret_bret__2
cores_16/backward/currentState_reg[0]_bret_bret__3
cores_16/backward/currentState_reg[0]_bret_bret__4
cores_16/backward/currentState_reg[1]_bret
cores_16/backward/currentState_reg[1]_bret__1
cores_16/backward/currentState_reg[1]_bret__2
cores_16/backward/currentState_reg[1]_bret__3
cores_16/backward/currentState_reg[2]_bret
cores_16/backward/currentState_reg[2]_bret__1
cores_16/backward/currentState_reg[2]_bret__2
cores_16/backward/currentState_reg[2]_bret__3
cores_16/backward/currentState_reg[3]_bret
cores_16/backward/currentState_reg[3]_bret__1
cores_16/backward/currentState_reg[3]_bret__2
cores_16/backward/currentState_reg[3]_bret__3
cores_16/backward/currentState_reg[4]_bret
cores_16/backward/currentState_reg[4]_bret__1
cores_16/backward/currentState_reg[4]_bret__2
cores_16/backward/currentState_reg[4]_bret__3
cores_16/backward/currentState_reg[5]_bret
cores_16/backward/currentState_reg[5]_bret__0_bret
cores_16/backward/currentState_reg[5]_bret__0_bret__0
cores_16/backward/currentState_reg[5]_bret__0_bret__1
cores_16/backward/currentState_reg[5]_bret__0_bret__2
cores_16/backward/currentState_reg[5]_bret__0_bret__3
cores_16/backward/currentState_reg[5]_bret__0_bret__4
cores_16/backward/currentState_reg[5]_bret__1
cores_16/backward/currentState_reg[5]_bret__2
cores_16/backward/currentState_reg[5]_bret__3
cores_17/backward/currentState_reg[0]_bret__0
cores_17/backward/currentState_reg[0]_bret__1
cores_17/backward/currentState_reg[0]_bret__2
cores_17/backward/currentState_reg[0]_bret__3
cores_17/backward/currentState_reg[0]_bret__4
cores_17/backward/currentState_reg[0]_bret_bret
cores_17/backward/currentState_reg[0]_bret_bret__0
cores_17/backward/currentState_reg[0]_bret_bret__1
cores_17/backward/currentState_reg[0]_bret_bret__2
cores_17/backward/currentState_reg[0]_bret_bret__3
cores_17/backward/currentState_reg[0]_bret_bret__4
cores_17/backward/currentState_reg[1]_bret
cores_17/backward/currentState_reg[1]_bret__1
cores_17/backward/currentState_reg[1]_bret__2
cores_17/backward/currentState_reg[1]_bret__3
cores_17/backward/currentState_reg[2]_bret
cores_17/backward/currentState_reg[2]_bret__1
cores_17/backward/currentState_reg[2]_bret__2
cores_17/backward/currentState_reg[2]_bret__3
cores_17/backward/currentState_reg[3]_bret
cores_17/backward/currentState_reg[3]_bret__1
cores_17/backward/currentState_reg[3]_bret__2
cores_17/backward/currentState_reg[3]_bret__3
cores_17/backward/currentState_reg[4]_bret
cores_17/backward/currentState_reg[4]_bret__1
cores_17/backward/currentState_reg[4]_bret__2
cores_17/backward/currentState_reg[4]_bret__3
cores_17/backward/currentState_reg[5]_bret
cores_17/backward/currentState_reg[5]_bret__0_bret
cores_17/backward/currentState_reg[5]_bret__0_bret__0
cores_17/backward/currentState_reg[5]_bret__0_bret__1
cores_17/backward/currentState_reg[5]_bret__0_bret__2
cores_17/backward/currentState_reg[5]_bret__0_bret__3
cores_17/backward/currentState_reg[5]_bret__0_bret__4
cores_17/backward/currentState_reg[5]_bret__1
cores_17/backward/currentState_reg[5]_bret__2
cores_17/backward/currentState_reg[5]_bret__3
cores_18/backward/currentState_reg[0]_bret__0
cores_18/backward/currentState_reg[0]_bret__1
cores_18/backward/currentState_reg[0]_bret__2
cores_18/backward/currentState_reg[0]_bret__3
cores_18/backward/currentState_reg[0]_bret__4
cores_18/backward/currentState_reg[0]_bret_bret
cores_18/backward/currentState_reg[0]_bret_bret__0
cores_18/backward/currentState_reg[0]_bret_bret__1
cores_18/backward/currentState_reg[0]_bret_bret__2
cores_18/backward/currentState_reg[0]_bret_bret__3
cores_18/backward/currentState_reg[0]_bret_bret__4
cores_18/backward/currentState_reg[1]_bret
cores_18/backward/currentState_reg[1]_bret__1
cores_18/backward/currentState_reg[1]_bret__2
cores_18/backward/currentState_reg[1]_bret__3
cores_18/backward/currentState_reg[2]_bret
cores_18/backward/currentState_reg[2]_bret__1
cores_18/backward/currentState_reg[2]_bret__2
cores_18/backward/currentState_reg[2]_bret__3
cores_18/backward/currentState_reg[3]_bret
cores_18/backward/currentState_reg[3]_bret__1
cores_18/backward/currentState_reg[3]_bret__2
cores_18/backward/currentState_reg[3]_bret__3
cores_18/backward/currentState_reg[4]_bret
cores_18/backward/currentState_reg[4]_bret__1
cores_18/backward/currentState_reg[4]_bret__2
cores_18/backward/currentState_reg[4]_bret__3
cores_18/backward/currentState_reg[5]_bret
cores_18/backward/currentState_reg[5]_bret__0_bret
cores_18/backward/currentState_reg[5]_bret__0_bret__0
cores_18/backward/currentState_reg[5]_bret__0_bret__1
cores_18/backward/currentState_reg[5]_bret__0_bret__2
cores_18/backward/currentState_reg[5]_bret__0_bret__3
cores_18/backward/currentState_reg[5]_bret__0_bret__4
cores_18/backward/currentState_reg[5]_bret__1
cores_18/backward/currentState_reg[5]_bret__2
cores_18/backward/currentState_reg[5]_bret__3
cores_19/backward/currentState_reg[0]_bret__0
cores_19/backward/currentState_reg[0]_bret__1
cores_19/backward/currentState_reg[0]_bret__2
cores_19/backward/currentState_reg[0]_bret__3
cores_19/backward/currentState_reg[0]_bret__4
cores_19/backward/currentState_reg[0]_bret_bret
cores_19/backward/currentState_reg[0]_bret_bret__0
cores_19/backward/currentState_reg[0]_bret_bret__1
cores_19/backward/currentState_reg[0]_bret_bret__2
cores_19/backward/currentState_reg[0]_bret_bret__3
cores_19/backward/currentState_reg[0]_bret_bret__4
cores_19/backward/currentState_reg[1]_bret
cores_19/backward/currentState_reg[1]_bret__1
cores_19/backward/currentState_reg[1]_bret__2
cores_19/backward/currentState_reg[1]_bret__3
cores_19/backward/currentState_reg[2]_bret
cores_19/backward/currentState_reg[2]_bret__1
cores_19/backward/currentState_reg[2]_bret__2
cores_19/backward/currentState_reg[2]_bret__3
cores_19/backward/currentState_reg[3]_bret
cores_19/backward/currentState_reg[3]_bret__1
cores_19/backward/currentState_reg[3]_bret__2
cores_19/backward/currentState_reg[3]_bret__3
cores_19/backward/currentState_reg[4]_bret
cores_19/backward/currentState_reg[4]_bret__1
cores_19/backward/currentState_reg[4]_bret__2
cores_19/backward/currentState_reg[4]_bret__3
cores_19/backward/currentState_reg[5]_bret
cores_19/backward/currentState_reg[5]_bret__0_bret
cores_19/backward/currentState_reg[5]_bret__0_bret__0
cores_19/backward/currentState_reg[5]_bret__0_bret__1
cores_19/backward/currentState_reg[5]_bret__0_bret__2
cores_19/backward/currentState_reg[5]_bret__0_bret__3
cores_19/backward/currentState_reg[5]_bret__0_bret__4
cores_19/backward/currentState_reg[5]_bret__1
cores_19/backward/currentState_reg[5]_bret__2
cores_19/backward/currentState_reg[5]_bret__3
cores_20/backward/currentState_reg[0]_bret__0
cores_20/backward/currentState_reg[0]_bret__1
cores_20/backward/currentState_reg[0]_bret__2
cores_20/backward/currentState_reg[0]_bret__3
cores_20/backward/currentState_reg[0]_bret__4
cores_20/backward/currentState_reg[0]_bret_bret
cores_20/backward/currentState_reg[0]_bret_bret__0
cores_20/backward/currentState_reg[0]_bret_bret__1
cores_20/backward/currentState_reg[0]_bret_bret__2
cores_20/backward/currentState_reg[0]_bret_bret__3
cores_20/backward/currentState_reg[0]_bret_bret__4
cores_20/backward/currentState_reg[1]_bret
cores_20/backward/currentState_reg[1]_bret__1
cores_20/backward/currentState_reg[1]_bret__2
cores_20/backward/currentState_reg[1]_bret__3
cores_20/backward/currentState_reg[2]_bret
cores_20/backward/currentState_reg[2]_bret__1
cores_20/backward/currentState_reg[2]_bret__2
cores_20/backward/currentState_reg[2]_bret__3
cores_20/backward/currentState_reg[3]_bret
cores_20/backward/currentState_reg[3]_bret__1
cores_20/backward/currentState_reg[3]_bret__2
cores_20/backward/currentState_reg[3]_bret__3
cores_20/backward/currentState_reg[4]_bret
cores_20/backward/currentState_reg[4]_bret__1
cores_20/backward/currentState_reg[4]_bret__2
cores_20/backward/currentState_reg[4]_bret__3
cores_20/backward/currentState_reg[5]_bret
cores_20/backward/currentState_reg[5]_bret__0_bret
cores_20/backward/currentState_reg[5]_bret__0_bret__0
cores_20/backward/currentState_reg[5]_bret__0_bret__1
cores_20/backward/currentState_reg[5]_bret__0_bret__2
cores_20/backward/currentState_reg[5]_bret__0_bret__3
cores_20/backward/currentState_reg[5]_bret__0_bret__4
cores_20/backward/currentState_reg[5]_bret__1
cores_20/backward/currentState_reg[5]_bret__2
cores_20/backward/currentState_reg[5]_bret__3
cores_21/backward/currentState_reg[0]_bret__0
cores_21/backward/currentState_reg[0]_bret__1
cores_21/backward/currentState_reg[0]_bret__2
cores_21/backward/currentState_reg[0]_bret__3
cores_21/backward/currentState_reg[0]_bret__4
cores_21/backward/currentState_reg[0]_bret_bret
cores_21/backward/currentState_reg[0]_bret_bret__0
cores_21/backward/currentState_reg[0]_bret_bret__1
cores_21/backward/currentState_reg[0]_bret_bret__2
cores_21/backward/currentState_reg[0]_bret_bret__3
cores_21/backward/currentState_reg[0]_bret_bret__4
cores_21/backward/currentState_reg[1]_bret
cores_21/backward/currentState_reg[1]_bret__1
cores_21/backward/currentState_reg[1]_bret__2
cores_21/backward/currentState_reg[1]_bret__3
cores_21/backward/currentState_reg[2]_bret
cores_21/backward/currentState_reg[2]_bret__1
cores_21/backward/currentState_reg[2]_bret__2
cores_21/backward/currentState_reg[2]_bret__3
cores_21/backward/currentState_reg[3]_bret
cores_21/backward/currentState_reg[3]_bret__1
cores_21/backward/currentState_reg[3]_bret__2
cores_21/backward/currentState_reg[3]_bret__3
cores_21/backward/currentState_reg[4]_bret
cores_21/backward/currentState_reg[4]_bret__1
cores_21/backward/currentState_reg[4]_bret__2
cores_21/backward/currentState_reg[4]_bret__3
cores_21/backward/currentState_reg[5]_bret
cores_21/backward/currentState_reg[5]_bret__0_bret
cores_21/backward/currentState_reg[5]_bret__0_bret__0
cores_21/backward/currentState_reg[5]_bret__0_bret__1
cores_21/backward/currentState_reg[5]_bret__0_bret__2
cores_21/backward/currentState_reg[5]_bret__0_bret__3
cores_21/backward/currentState_reg[5]_bret__0_bret__4
cores_21/backward/currentState_reg[5]_bret__1
cores_21/backward/currentState_reg[5]_bret__2
cores_21/backward/currentState_reg[5]_bret__3
cores_22/backward/currentState_reg[0]_bret__0
cores_22/backward/currentState_reg[0]_bret__1
cores_22/backward/currentState_reg[0]_bret__2
cores_22/backward/currentState_reg[0]_bret__3
cores_22/backward/currentState_reg[0]_bret__4
cores_22/backward/currentState_reg[0]_bret_bret
cores_22/backward/currentState_reg[0]_bret_bret__0
cores_22/backward/currentState_reg[0]_bret_bret__1
cores_22/backward/currentState_reg[0]_bret_bret__2
cores_22/backward/currentState_reg[0]_bret_bret__3
cores_22/backward/currentState_reg[0]_bret_bret__4
cores_22/backward/currentState_reg[1]_bret
cores_22/backward/currentState_reg[1]_bret__1
cores_22/backward/currentState_reg[1]_bret__2
cores_22/backward/currentState_reg[1]_bret__3
cores_22/backward/currentState_reg[2]_bret
cores_22/backward/currentState_reg[2]_bret__1
cores_22/backward/currentState_reg[2]_bret__2
cores_22/backward/currentState_reg[2]_bret__3
cores_22/backward/currentState_reg[3]_bret
cores_22/backward/currentState_reg[3]_bret__1
cores_22/backward/currentState_reg[3]_bret__2
cores_22/backward/currentState_reg[3]_bret__3
cores_22/backward/currentState_reg[4]_bret
cores_22/backward/currentState_reg[4]_bret__1
cores_22/backward/currentState_reg[4]_bret__2
cores_22/backward/currentState_reg[4]_bret__3
cores_22/backward/currentState_reg[5]_bret
cores_22/backward/currentState_reg[5]_bret__0_bret
cores_22/backward/currentState_reg[5]_bret__0_bret__0
cores_22/backward/currentState_reg[5]_bret__0_bret__1
cores_22/backward/currentState_reg[5]_bret__0_bret__2
cores_22/backward/currentState_reg[5]_bret__0_bret__3
cores_22/backward/currentState_reg[5]_bret__0_bret__4
cores_22/backward/currentState_reg[5]_bret__1
cores_22/backward/currentState_reg[5]_bret__2
cores_22/backward/currentState_reg[5]_bret__3
cores_23/backward/currentState_reg[0]_bret__0
cores_23/backward/currentState_reg[0]_bret__1
cores_23/backward/currentState_reg[0]_bret__2
cores_23/backward/currentState_reg[0]_bret__3
cores_23/backward/currentState_reg[0]_bret__4
cores_23/backward/currentState_reg[0]_bret_bret
cores_23/backward/currentState_reg[0]_bret_bret__0
cores_23/backward/currentState_reg[0]_bret_bret__1
cores_23/backward/currentState_reg[0]_bret_bret__2
cores_23/backward/currentState_reg[0]_bret_bret__3
cores_23/backward/currentState_reg[0]_bret_bret__4
cores_23/backward/currentState_reg[1]_bret
cores_23/backward/currentState_reg[1]_bret__1
cores_23/backward/currentState_reg[1]_bret__2
cores_23/backward/currentState_reg[1]_bret__3
cores_23/backward/currentState_reg[2]_bret
cores_23/backward/currentState_reg[2]_bret__1
cores_23/backward/currentState_reg[2]_bret__2
cores_23/backward/currentState_reg[2]_bret__3
cores_23/backward/currentState_reg[3]_bret
cores_23/backward/currentState_reg[3]_bret__1
cores_23/backward/currentState_reg[3]_bret__2
cores_23/backward/currentState_reg[3]_bret__3
cores_23/backward/currentState_reg[4]_bret
cores_23/backward/currentState_reg[4]_bret__1
cores_23/backward/currentState_reg[4]_bret__2
cores_23/backward/currentState_reg[4]_bret__3
cores_23/backward/currentState_reg[5]_bret
cores_23/backward/currentState_reg[5]_bret__0_bret
cores_23/backward/currentState_reg[5]_bret__0_bret__0
cores_23/backward/currentState_reg[5]_bret__0_bret__1
cores_23/backward/currentState_reg[5]_bret__0_bret__2
cores_23/backward/currentState_reg[5]_bret__0_bret__3
cores_23/backward/currentState_reg[5]_bret__0_bret__4
cores_23/backward/currentState_reg[5]_bret__1
cores_23/backward/currentState_reg[5]_bret__2
cores_23/backward/currentState_reg[5]_bret__3
cores_24/backward/currentState_reg[0]_bret__0
cores_24/backward/currentState_reg[0]_bret__1
cores_24/backward/currentState_reg[0]_bret__2
cores_24/backward/currentState_reg[0]_bret__3
cores_24/backward/currentState_reg[0]_bret__4
cores_24/backward/currentState_reg[0]_bret_bret
cores_24/backward/currentState_reg[0]_bret_bret__0
cores_24/backward/currentState_reg[0]_bret_bret__1
cores_24/backward/currentState_reg[0]_bret_bret__2
cores_24/backward/currentState_reg[0]_bret_bret__3
cores_24/backward/currentState_reg[0]_bret_bret__4
cores_24/backward/currentState_reg[1]_bret
cores_24/backward/currentState_reg[1]_bret__1
cores_24/backward/currentState_reg[1]_bret__2
cores_24/backward/currentState_reg[1]_bret__3
cores_24/backward/currentState_reg[2]_bret
cores_24/backward/currentState_reg[2]_bret__1
cores_24/backward/currentState_reg[2]_bret__2
cores_24/backward/currentState_reg[2]_bret__3
cores_24/backward/currentState_reg[3]_bret
cores_24/backward/currentState_reg[3]_bret__1
cores_24/backward/currentState_reg[3]_bret__2
cores_24/backward/currentState_reg[3]_bret__3
cores_24/backward/currentState_reg[4]_bret
cores_24/backward/currentState_reg[4]_bret__1
cores_24/backward/currentState_reg[4]_bret__2
cores_24/backward/currentState_reg[4]_bret__3
cores_24/backward/currentState_reg[5]_bret
cores_24/backward/currentState_reg[5]_bret__0_bret
cores_24/backward/currentState_reg[5]_bret__0_bret__0
cores_24/backward/currentState_reg[5]_bret__0_bret__1
cores_24/backward/currentState_reg[5]_bret__0_bret__2
cores_24/backward/currentState_reg[5]_bret__0_bret__3
cores_24/backward/currentState_reg[5]_bret__0_bret__4
cores_24/backward/currentState_reg[5]_bret__1
cores_24/backward/currentState_reg[5]_bret__2
cores_24/backward/currentState_reg[5]_bret__3
cores_26/backward/currentState_reg[0]_bret__0
cores_26/backward/currentState_reg[0]_bret__1
cores_26/backward/currentState_reg[0]_bret__2
cores_26/backward/currentState_reg[0]_bret__3
cores_26/backward/currentState_reg[0]_bret__4
cores_26/backward/currentState_reg[0]_bret_bret
cores_26/backward/currentState_reg[0]_bret_bret__0
cores_26/backward/currentState_reg[0]_bret_bret__1
cores_26/backward/currentState_reg[0]_bret_bret__2
cores_26/backward/currentState_reg[0]_bret_bret__3
cores_26/backward/currentState_reg[0]_bret_bret__4
cores_26/backward/currentState_reg[1]_bret
cores_26/backward/currentState_reg[1]_bret__1
cores_26/backward/currentState_reg[1]_bret__2
cores_26/backward/currentState_reg[1]_bret__3
cores_26/backward/currentState_reg[2]_bret
cores_26/backward/currentState_reg[2]_bret__1
cores_26/backward/currentState_reg[2]_bret__2
cores_26/backward/currentState_reg[2]_bret__3
cores_26/backward/currentState_reg[3]_bret
cores_26/backward/currentState_reg[3]_bret__1
cores_26/backward/currentState_reg[3]_bret__2
cores_26/backward/currentState_reg[3]_bret__3
cores_26/backward/currentState_reg[4]_bret
cores_26/backward/currentState_reg[4]_bret__1
cores_26/backward/currentState_reg[4]_bret__2
cores_26/backward/currentState_reg[4]_bret__3
cores_26/backward/currentState_reg[5]_bret
cores_26/backward/currentState_reg[5]_bret__0_bret
cores_26/backward/currentState_reg[5]_bret__0_bret__0
cores_26/backward/currentState_reg[5]_bret__0_bret__1
cores_26/backward/currentState_reg[5]_bret__0_bret__2
cores_26/backward/currentState_reg[5]_bret__0_bret__3
cores_26/backward/currentState_reg[5]_bret__0_bret__4
cores_26/backward/currentState_reg[5]_bret__1
cores_26/backward/currentState_reg[5]_bret__2
cores_26/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB6_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-7052] The timing for the instance i_6/cores_26/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_6/cores_26/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_6/cores_26/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance i_6/cores_26/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB7_tempName`
Numbers of forward move = 0, and backward move = 72
Retimed registers names:
cores_10/backward/currentState_reg[0]_bret__0
cores_10/backward/currentState_reg[0]_bret__1
cores_10/backward/currentState_reg[0]_bret__2
cores_10/backward/currentState_reg[0]_bret__3
cores_10/backward/currentState_reg[0]_bret__4
cores_10/backward/currentState_reg[0]_bret_bret
cores_10/backward/currentState_reg[0]_bret_bret__0
cores_10/backward/currentState_reg[0]_bret_bret__1
cores_10/backward/currentState_reg[0]_bret_bret__2
cores_10/backward/currentState_reg[0]_bret_bret__3
cores_10/backward/currentState_reg[0]_bret_bret__4
cores_10/backward/currentState_reg[1]_bret
cores_10/backward/currentState_reg[1]_bret__1
cores_10/backward/currentState_reg[1]_bret__2
cores_10/backward/currentState_reg[1]_bret__3
cores_10/backward/currentState_reg[2]_bret
cores_10/backward/currentState_reg[2]_bret__1
cores_10/backward/currentState_reg[2]_bret__2
cores_10/backward/currentState_reg[2]_bret__3
cores_10/backward/currentState_reg[3]_bret
cores_10/backward/currentState_reg[3]_bret__1
cores_10/backward/currentState_reg[3]_bret__2
cores_10/backward/currentState_reg[3]_bret__3
cores_10/backward/currentState_reg[4]_bret
cores_10/backward/currentState_reg[4]_bret__1
cores_10/backward/currentState_reg[4]_bret__2
cores_10/backward/currentState_reg[4]_bret__3
cores_10/backward/currentState_reg[5]_bret
cores_10/backward/currentState_reg[5]_bret__0_bret
cores_10/backward/currentState_reg[5]_bret__0_bret__0
cores_10/backward/currentState_reg[5]_bret__0_bret__1
cores_10/backward/currentState_reg[5]_bret__0_bret__2
cores_10/backward/currentState_reg[5]_bret__0_bret__3
cores_10/backward/currentState_reg[5]_bret__0_bret__4
cores_10/backward/currentState_reg[5]_bret__1
cores_10/backward/currentState_reg[5]_bret__2
cores_10/backward/currentState_reg[5]_bret__3
cores_11/backward/currentState_reg[0]_bret__0
cores_11/backward/currentState_reg[0]_bret__1
cores_11/backward/currentState_reg[0]_bret__2
cores_11/backward/currentState_reg[0]_bret__3
cores_11/backward/currentState_reg[0]_bret__4
cores_11/backward/currentState_reg[0]_bret_bret
cores_11/backward/currentState_reg[0]_bret_bret__0
cores_11/backward/currentState_reg[0]_bret_bret__1
cores_11/backward/currentState_reg[0]_bret_bret__2
cores_11/backward/currentState_reg[0]_bret_bret__3
cores_11/backward/currentState_reg[0]_bret_bret__4
cores_11/backward/currentState_reg[1]_bret
cores_11/backward/currentState_reg[1]_bret__1
cores_11/backward/currentState_reg[1]_bret__2
cores_11/backward/currentState_reg[1]_bret__3
cores_11/backward/currentState_reg[2]_bret
cores_11/backward/currentState_reg[2]_bret__1
cores_11/backward/currentState_reg[2]_bret__2
cores_11/backward/currentState_reg[2]_bret__3
cores_11/backward/currentState_reg[3]_bret
cores_11/backward/currentState_reg[3]_bret__1
cores_11/backward/currentState_reg[3]_bret__2
cores_11/backward/currentState_reg[3]_bret__3
cores_11/backward/currentState_reg[4]_bret
cores_11/backward/currentState_reg[4]_bret__1
cores_11/backward/currentState_reg[4]_bret__2
cores_11/backward/currentState_reg[4]_bret__3
cores_11/backward/currentState_reg[5]_bret
cores_11/backward/currentState_reg[5]_bret__0_bret
cores_11/backward/currentState_reg[5]_bret__0_bret__0
cores_11/backward/currentState_reg[5]_bret__0_bret__1
cores_11/backward/currentState_reg[5]_bret__0_bret__2
cores_11/backward/currentState_reg[5]_bret__0_bret__3
cores_11/backward/currentState_reg[5]_bret__0_bret__4
cores_11/backward/currentState_reg[5]_bret__1
cores_11/backward/currentState_reg[5]_bret__2
cores_11/backward/currentState_reg[5]_bret__3
cores_12/backward/currentState_reg[0]_bret__0
cores_12/backward/currentState_reg[0]_bret__1
cores_12/backward/currentState_reg[0]_bret__2
cores_12/backward/currentState_reg[0]_bret__3
cores_12/backward/currentState_reg[0]_bret__4
cores_12/backward/currentState_reg[0]_bret_bret
cores_12/backward/currentState_reg[0]_bret_bret__0
cores_12/backward/currentState_reg[0]_bret_bret__1
cores_12/backward/currentState_reg[0]_bret_bret__2
cores_12/backward/currentState_reg[0]_bret_bret__3
cores_12/backward/currentState_reg[0]_bret_bret__4
cores_12/backward/currentState_reg[1]_bret
cores_12/backward/currentState_reg[1]_bret__1
cores_12/backward/currentState_reg[1]_bret__2
cores_12/backward/currentState_reg[1]_bret__3
cores_12/backward/currentState_reg[2]_bret
cores_12/backward/currentState_reg[2]_bret__1
cores_12/backward/currentState_reg[2]_bret__2
cores_12/backward/currentState_reg[2]_bret__3
cores_12/backward/currentState_reg[3]_bret
cores_12/backward/currentState_reg[3]_bret__1
cores_12/backward/currentState_reg[3]_bret__2
cores_12/backward/currentState_reg[3]_bret__3
cores_12/backward/currentState_reg[4]_bret
cores_12/backward/currentState_reg[4]_bret__1
cores_12/backward/currentState_reg[4]_bret__2
cores_12/backward/currentState_reg[4]_bret__3
cores_12/backward/currentState_reg[5]_bret
cores_12/backward/currentState_reg[5]_bret__0_bret
cores_12/backward/currentState_reg[5]_bret__0_bret__0
cores_12/backward/currentState_reg[5]_bret__0_bret__1
cores_12/backward/currentState_reg[5]_bret__0_bret__2
cores_12/backward/currentState_reg[5]_bret__0_bret__3
cores_12/backward/currentState_reg[5]_bret__0_bret__4
cores_12/backward/currentState_reg[5]_bret__1
cores_12/backward/currentState_reg[5]_bret__2
cores_12/backward/currentState_reg[5]_bret__3
cores_13/backward/currentState_reg[0]_bret__0
cores_13/backward/currentState_reg[0]_bret__1
cores_13/backward/currentState_reg[0]_bret__2
cores_13/backward/currentState_reg[0]_bret__3
cores_13/backward/currentState_reg[0]_bret__4
cores_13/backward/currentState_reg[0]_bret_bret
cores_13/backward/currentState_reg[0]_bret_bret__0
cores_13/backward/currentState_reg[0]_bret_bret__1
cores_13/backward/currentState_reg[0]_bret_bret__2
cores_13/backward/currentState_reg[0]_bret_bret__3
cores_13/backward/currentState_reg[0]_bret_bret__4
cores_13/backward/currentState_reg[1]_bret
cores_13/backward/currentState_reg[1]_bret__1
cores_13/backward/currentState_reg[1]_bret__2
cores_13/backward/currentState_reg[1]_bret__3
cores_13/backward/currentState_reg[2]_bret
cores_13/backward/currentState_reg[2]_bret__1
cores_13/backward/currentState_reg[2]_bret__2
cores_13/backward/currentState_reg[2]_bret__3
cores_13/backward/currentState_reg[3]_bret
cores_13/backward/currentState_reg[3]_bret__1
cores_13/backward/currentState_reg[3]_bret__2
cores_13/backward/currentState_reg[3]_bret__3
cores_13/backward/currentState_reg[4]_bret
cores_13/backward/currentState_reg[4]_bret__1
cores_13/backward/currentState_reg[4]_bret__2
cores_13/backward/currentState_reg[4]_bret__3
cores_13/backward/currentState_reg[5]_bret
cores_13/backward/currentState_reg[5]_bret__0_bret
cores_13/backward/currentState_reg[5]_bret__0_bret__0
cores_13/backward/currentState_reg[5]_bret__0_bret__1
cores_13/backward/currentState_reg[5]_bret__0_bret__2
cores_13/backward/currentState_reg[5]_bret__0_bret__3
cores_13/backward/currentState_reg[5]_bret__0_bret__4
cores_13/backward/currentState_reg[5]_bret__1
cores_13/backward/currentState_reg[5]_bret__2
cores_13/backward/currentState_reg[5]_bret__3
cores_14/backward/currentState_reg[0]_bret__0
cores_14/backward/currentState_reg[0]_bret__1
cores_14/backward/currentState_reg[0]_bret__2
cores_14/backward/currentState_reg[0]_bret__3
cores_14/backward/currentState_reg[0]_bret__4
cores_14/backward/currentState_reg[0]_bret_bret
cores_14/backward/currentState_reg[0]_bret_bret__0
cores_14/backward/currentState_reg[0]_bret_bret__1
cores_14/backward/currentState_reg[0]_bret_bret__2
cores_14/backward/currentState_reg[0]_bret_bret__3
cores_14/backward/currentState_reg[0]_bret_bret__4
cores_14/backward/currentState_reg[1]_bret
cores_14/backward/currentState_reg[1]_bret__1
cores_14/backward/currentState_reg[1]_bret__2
cores_14/backward/currentState_reg[1]_bret__3
cores_14/backward/currentState_reg[2]_bret
cores_14/backward/currentState_reg[2]_bret__1
cores_14/backward/currentState_reg[2]_bret__2
cores_14/backward/currentState_reg[2]_bret__3
cores_14/backward/currentState_reg[3]_bret
cores_14/backward/currentState_reg[3]_bret__1
cores_14/backward/currentState_reg[3]_bret__2
cores_14/backward/currentState_reg[3]_bret__3
cores_14/backward/currentState_reg[4]_bret
cores_14/backward/currentState_reg[4]_bret__1
cores_14/backward/currentState_reg[4]_bret__2
cores_14/backward/currentState_reg[4]_bret__3
cores_14/backward/currentState_reg[5]_bret
cores_14/backward/currentState_reg[5]_bret__0_bret
cores_14/backward/currentState_reg[5]_bret__0_bret__0
cores_14/backward/currentState_reg[5]_bret__0_bret__1
cores_14/backward/currentState_reg[5]_bret__0_bret__2
cores_14/backward/currentState_reg[5]_bret__0_bret__3
cores_14/backward/currentState_reg[5]_bret__0_bret__4
cores_14/backward/currentState_reg[5]_bret__1
cores_14/backward/currentState_reg[5]_bret__2
cores_14/backward/currentState_reg[5]_bret__3
cores_6/backward/currentState_reg[0]_bret__0
cores_6/backward/currentState_reg[0]_bret__1
cores_6/backward/currentState_reg[0]_bret__2
cores_6/backward/currentState_reg[0]_bret__3
cores_6/backward/currentState_reg[0]_bret__4
cores_6/backward/currentState_reg[0]_bret_bret
cores_6/backward/currentState_reg[0]_bret_bret__0
cores_6/backward/currentState_reg[0]_bret_bret__1
cores_6/backward/currentState_reg[0]_bret_bret__2
cores_6/backward/currentState_reg[0]_bret_bret__3
cores_6/backward/currentState_reg[0]_bret_bret__4
cores_6/backward/currentState_reg[1]_bret
cores_6/backward/currentState_reg[1]_bret__1
cores_6/backward/currentState_reg[1]_bret__2
cores_6/backward/currentState_reg[1]_bret__3
cores_6/backward/currentState_reg[2]_bret
cores_6/backward/currentState_reg[2]_bret__1
cores_6/backward/currentState_reg[2]_bret__2
cores_6/backward/currentState_reg[2]_bret__3
cores_6/backward/currentState_reg[3]_bret
cores_6/backward/currentState_reg[3]_bret__1
cores_6/backward/currentState_reg[3]_bret__2
cores_6/backward/currentState_reg[3]_bret__3
cores_6/backward/currentState_reg[4]_bret
cores_6/backward/currentState_reg[4]_bret__1
cores_6/backward/currentState_reg[4]_bret__2
cores_6/backward/currentState_reg[4]_bret__3
cores_6/backward/currentState_reg[5]_bret
cores_6/backward/currentState_reg[5]_bret__0_bret
cores_6/backward/currentState_reg[5]_bret__0_bret__0
cores_6/backward/currentState_reg[5]_bret__0_bret__1
cores_6/backward/currentState_reg[5]_bret__0_bret__2
cores_6/backward/currentState_reg[5]_bret__0_bret__3
cores_6/backward/currentState_reg[5]_bret__0_bret__4
cores_6/backward/currentState_reg[5]_bret__1
cores_6/backward/currentState_reg[5]_bret__2
cores_6/backward/currentState_reg[5]_bret__3
cores_7/backward/currentState_reg[0]_bret__0
cores_7/backward/currentState_reg[0]_bret__1
cores_7/backward/currentState_reg[0]_bret__2
cores_7/backward/currentState_reg[0]_bret__3
cores_7/backward/currentState_reg[0]_bret__4
cores_7/backward/currentState_reg[0]_bret_bret
cores_7/backward/currentState_reg[0]_bret_bret__0
cores_7/backward/currentState_reg[0]_bret_bret__1
cores_7/backward/currentState_reg[0]_bret_bret__2
cores_7/backward/currentState_reg[0]_bret_bret__3
cores_7/backward/currentState_reg[0]_bret_bret__4
cores_7/backward/currentState_reg[1]_bret
cores_7/backward/currentState_reg[1]_bret__1
cores_7/backward/currentState_reg[1]_bret__2
cores_7/backward/currentState_reg[1]_bret__3
cores_7/backward/currentState_reg[2]_bret
cores_7/backward/currentState_reg[2]_bret__1
cores_7/backward/currentState_reg[2]_bret__2
cores_7/backward/currentState_reg[2]_bret__3
cores_7/backward/currentState_reg[3]_bret
cores_7/backward/currentState_reg[3]_bret__1
cores_7/backward/currentState_reg[3]_bret__2
cores_7/backward/currentState_reg[3]_bret__3
cores_7/backward/currentState_reg[4]_bret
cores_7/backward/currentState_reg[4]_bret__1
cores_7/backward/currentState_reg[4]_bret__2
cores_7/backward/currentState_reg[4]_bret__3
cores_7/backward/currentState_reg[5]_bret
cores_7/backward/currentState_reg[5]_bret__0_bret
cores_7/backward/currentState_reg[5]_bret__0_bret__0
cores_7/backward/currentState_reg[5]_bret__0_bret__1
cores_7/backward/currentState_reg[5]_bret__0_bret__2
cores_7/backward/currentState_reg[5]_bret__0_bret__3
cores_7/backward/currentState_reg[5]_bret__0_bret__4
cores_7/backward/currentState_reg[5]_bret__1
cores_7/backward/currentState_reg[5]_bret__2
cores_7/backward/currentState_reg[5]_bret__3
cores_8/backward/currentState_reg[0]_bret__0
cores_8/backward/currentState_reg[0]_bret__1
cores_8/backward/currentState_reg[0]_bret__2
cores_8/backward/currentState_reg[0]_bret__3
cores_8/backward/currentState_reg[0]_bret__4
cores_8/backward/currentState_reg[0]_bret_bret
cores_8/backward/currentState_reg[0]_bret_bret__0
cores_8/backward/currentState_reg[0]_bret_bret__1
cores_8/backward/currentState_reg[0]_bret_bret__2
cores_8/backward/currentState_reg[0]_bret_bret__3
cores_8/backward/currentState_reg[0]_bret_bret__4
cores_8/backward/currentState_reg[1]_bret
cores_8/backward/currentState_reg[1]_bret__1
cores_8/backward/currentState_reg[1]_bret__2
cores_8/backward/currentState_reg[1]_bret__3
cores_8/backward/currentState_reg[2]_bret
cores_8/backward/currentState_reg[2]_bret__1
cores_8/backward/currentState_reg[2]_bret__2
cores_8/backward/currentState_reg[2]_bret__3
cores_8/backward/currentState_reg[3]_bret
cores_8/backward/currentState_reg[3]_bret__1
cores_8/backward/currentState_reg[3]_bret__2
cores_8/backward/currentState_reg[3]_bret__3
cores_8/backward/currentState_reg[4]_bret
cores_8/backward/currentState_reg[4]_bret__1
cores_8/backward/currentState_reg[4]_bret__2
cores_8/backward/currentState_reg[4]_bret__3
cores_8/backward/currentState_reg[5]_bret
cores_8/backward/currentState_reg[5]_bret__0_bret
cores_8/backward/currentState_reg[5]_bret__0_bret__0
cores_8/backward/currentState_reg[5]_bret__0_bret__1
cores_8/backward/currentState_reg[5]_bret__0_bret__2
cores_8/backward/currentState_reg[5]_bret__0_bret__3
cores_8/backward/currentState_reg[5]_bret__0_bret__4
cores_8/backward/currentState_reg[5]_bret__1
cores_8/backward/currentState_reg[5]_bret__2
cores_8/backward/currentState_reg[5]_bret__3
cores_9/backward/currentState_reg[0]_bret__0
cores_9/backward/currentState_reg[0]_bret__1
cores_9/backward/currentState_reg[0]_bret__2
cores_9/backward/currentState_reg[0]_bret__3
cores_9/backward/currentState_reg[0]_bret__4
cores_9/backward/currentState_reg[0]_bret_bret
cores_9/backward/currentState_reg[0]_bret_bret__0
cores_9/backward/currentState_reg[0]_bret_bret__1
cores_9/backward/currentState_reg[0]_bret_bret__2
cores_9/backward/currentState_reg[0]_bret_bret__3
cores_9/backward/currentState_reg[0]_bret_bret__4
cores_9/backward/currentState_reg[1]_bret
cores_9/backward/currentState_reg[1]_bret__1
cores_9/backward/currentState_reg[1]_bret__2
cores_9/backward/currentState_reg[1]_bret__3
cores_9/backward/currentState_reg[2]_bret
cores_9/backward/currentState_reg[2]_bret__1
cores_9/backward/currentState_reg[2]_bret__2
cores_9/backward/currentState_reg[2]_bret__3
cores_9/backward/currentState_reg[3]_bret
cores_9/backward/currentState_reg[3]_bret__1
cores_9/backward/currentState_reg[3]_bret__2
cores_9/backward/currentState_reg[3]_bret__3
cores_9/backward/currentState_reg[4]_bret
cores_9/backward/currentState_reg[4]_bret__1
cores_9/backward/currentState_reg[4]_bret__2
cores_9/backward/currentState_reg[4]_bret__3
cores_9/backward/currentState_reg[5]_bret
cores_9/backward/currentState_reg[5]_bret__0_bret
cores_9/backward/currentState_reg[5]_bret__0_bret__0
cores_9/backward/currentState_reg[5]_bret__0_bret__1
cores_9/backward/currentState_reg[5]_bret__0_bret__2
cores_9/backward/currentState_reg[5]_bret__0_bret__3
cores_9/backward/currentState_reg[5]_bret__0_bret__4
cores_9/backward/currentState_reg[5]_bret__1
cores_9/backward/currentState_reg[5]_bret__2
cores_9/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB7_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB8_tempName`
Numbers of forward move = 0, and backward move = 24
Retimed registers names:
cores_2/backward/currentState_reg[0]_bret__0
cores_2/backward/currentState_reg[0]_bret__1
cores_2/backward/currentState_reg[0]_bret__2
cores_2/backward/currentState_reg[0]_bret__3
cores_2/backward/currentState_reg[0]_bret__4
cores_2/backward/currentState_reg[0]_bret_bret
cores_2/backward/currentState_reg[0]_bret_bret__0
cores_2/backward/currentState_reg[0]_bret_bret__1
cores_2/backward/currentState_reg[0]_bret_bret__2
cores_2/backward/currentState_reg[0]_bret_bret__3
cores_2/backward/currentState_reg[0]_bret_bret__4
cores_2/backward/currentState_reg[1]_bret
cores_2/backward/currentState_reg[1]_bret__1
cores_2/backward/currentState_reg[1]_bret__2
cores_2/backward/currentState_reg[1]_bret__3
cores_2/backward/currentState_reg[2]_bret
cores_2/backward/currentState_reg[2]_bret__1
cores_2/backward/currentState_reg[2]_bret__2
cores_2/backward/currentState_reg[2]_bret__3
cores_2/backward/currentState_reg[3]_bret
cores_2/backward/currentState_reg[3]_bret__1
cores_2/backward/currentState_reg[3]_bret__2
cores_2/backward/currentState_reg[3]_bret__3
cores_2/backward/currentState_reg[4]_bret
cores_2/backward/currentState_reg[4]_bret__1
cores_2/backward/currentState_reg[4]_bret__2
cores_2/backward/currentState_reg[4]_bret__3
cores_2/backward/currentState_reg[5]_bret
cores_2/backward/currentState_reg[5]_bret__0_bret
cores_2/backward/currentState_reg[5]_bret__0_bret__0
cores_2/backward/currentState_reg[5]_bret__0_bret__1
cores_2/backward/currentState_reg[5]_bret__0_bret__2
cores_2/backward/currentState_reg[5]_bret__0_bret__3
cores_2/backward/currentState_reg[5]_bret__0_bret__4
cores_2/backward/currentState_reg[5]_bret__1
cores_2/backward/currentState_reg[5]_bret__2
cores_2/backward/currentState_reg[5]_bret__3
cores_3/backward/currentState_reg[0]_bret__0
cores_3/backward/currentState_reg[0]_bret__1
cores_3/backward/currentState_reg[0]_bret__2
cores_3/backward/currentState_reg[0]_bret__3
cores_3/backward/currentState_reg[0]_bret__4
cores_3/backward/currentState_reg[0]_bret_bret
cores_3/backward/currentState_reg[0]_bret_bret__0
cores_3/backward/currentState_reg[0]_bret_bret__1
cores_3/backward/currentState_reg[0]_bret_bret__2
cores_3/backward/currentState_reg[0]_bret_bret__3
cores_3/backward/currentState_reg[0]_bret_bret__4
cores_3/backward/currentState_reg[1]_bret
cores_3/backward/currentState_reg[1]_bret__1
cores_3/backward/currentState_reg[1]_bret__2
cores_3/backward/currentState_reg[1]_bret__3
cores_3/backward/currentState_reg[2]_bret
cores_3/backward/currentState_reg[2]_bret__1
cores_3/backward/currentState_reg[2]_bret__2
cores_3/backward/currentState_reg[2]_bret__3
cores_3/backward/currentState_reg[3]_bret
cores_3/backward/currentState_reg[3]_bret__1
cores_3/backward/currentState_reg[3]_bret__2
cores_3/backward/currentState_reg[3]_bret__3
cores_3/backward/currentState_reg[4]_bret
cores_3/backward/currentState_reg[4]_bret__1
cores_3/backward/currentState_reg[4]_bret__2
cores_3/backward/currentState_reg[4]_bret__3
cores_3/backward/currentState_reg[5]_bret
cores_3/backward/currentState_reg[5]_bret__0_bret
cores_3/backward/currentState_reg[5]_bret__0_bret__0
cores_3/backward/currentState_reg[5]_bret__0_bret__1
cores_3/backward/currentState_reg[5]_bret__0_bret__2
cores_3/backward/currentState_reg[5]_bret__0_bret__3
cores_3/backward/currentState_reg[5]_bret__0_bret__4
cores_3/backward/currentState_reg[5]_bret__1
cores_3/backward/currentState_reg[5]_bret__2
cores_3/backward/currentState_reg[5]_bret__3
cores_5/backward/currentState_reg[0]_bret__0
cores_5/backward/currentState_reg[0]_bret__1
cores_5/backward/currentState_reg[0]_bret__2
cores_5/backward/currentState_reg[0]_bret__3
cores_5/backward/currentState_reg[0]_bret__4
cores_5/backward/currentState_reg[0]_bret_bret
cores_5/backward/currentState_reg[0]_bret_bret__0
cores_5/backward/currentState_reg[0]_bret_bret__1
cores_5/backward/currentState_reg[0]_bret_bret__2
cores_5/backward/currentState_reg[0]_bret_bret__3
cores_5/backward/currentState_reg[0]_bret_bret__4
cores_5/backward/currentState_reg[1]_bret
cores_5/backward/currentState_reg[1]_bret__1
cores_5/backward/currentState_reg[1]_bret__2
cores_5/backward/currentState_reg[1]_bret__3
cores_5/backward/currentState_reg[2]_bret
cores_5/backward/currentState_reg[2]_bret__1
cores_5/backward/currentState_reg[2]_bret__2
cores_5/backward/currentState_reg[2]_bret__3
cores_5/backward/currentState_reg[3]_bret
cores_5/backward/currentState_reg[3]_bret__1
cores_5/backward/currentState_reg[3]_bret__2
cores_5/backward/currentState_reg[3]_bret__3
cores_5/backward/currentState_reg[4]_bret
cores_5/backward/currentState_reg[4]_bret__1
cores_5/backward/currentState_reg[4]_bret__2
cores_5/backward/currentState_reg[4]_bret__3
cores_5/backward/currentState_reg[5]_bret
cores_5/backward/currentState_reg[5]_bret__0_bret
cores_5/backward/currentState_reg[5]_bret__0_bret__0
cores_5/backward/currentState_reg[5]_bret__0_bret__1
cores_5/backward/currentState_reg[5]_bret__0_bret__2
cores_5/backward/currentState_reg[5]_bret__0_bret__3
cores_5/backward/currentState_reg[5]_bret__0_bret__4
cores_5/backward/currentState_reg[5]_bret__1
cores_5/backward/currentState_reg[5]_bret__2
cores_5/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB8_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB9_tempName`
Numbers of forward move = 0, and backward move = 24
Retimed registers names:
cores_0/backward/currentState_reg[0]_bret__0
cores_0/backward/currentState_reg[0]_bret__1
cores_0/backward/currentState_reg[0]_bret__2
cores_0/backward/currentState_reg[0]_bret__3
cores_0/backward/currentState_reg[0]_bret__4
cores_0/backward/currentState_reg[0]_bret_bret
cores_0/backward/currentState_reg[0]_bret_bret__0
cores_0/backward/currentState_reg[0]_bret_bret__1
cores_0/backward/currentState_reg[0]_bret_bret__2
cores_0/backward/currentState_reg[0]_bret_bret__3
cores_0/backward/currentState_reg[0]_bret_bret__4
cores_0/backward/currentState_reg[1]_bret
cores_0/backward/currentState_reg[1]_bret__1
cores_0/backward/currentState_reg[1]_bret__2
cores_0/backward/currentState_reg[1]_bret__3
cores_0/backward/currentState_reg[2]_bret
cores_0/backward/currentState_reg[2]_bret__1
cores_0/backward/currentState_reg[2]_bret__2
cores_0/backward/currentState_reg[2]_bret__3
cores_0/backward/currentState_reg[3]_bret
cores_0/backward/currentState_reg[3]_bret__1
cores_0/backward/currentState_reg[3]_bret__2
cores_0/backward/currentState_reg[3]_bret__3
cores_0/backward/currentState_reg[4]_bret
cores_0/backward/currentState_reg[4]_bret__1
cores_0/backward/currentState_reg[4]_bret__2
cores_0/backward/currentState_reg[4]_bret__3
cores_0/backward/currentState_reg[5]_bret
cores_0/backward/currentState_reg[5]_bret__0_bret
cores_0/backward/currentState_reg[5]_bret__0_bret__0
cores_0/backward/currentState_reg[5]_bret__0_bret__1
cores_0/backward/currentState_reg[5]_bret__0_bret__2
cores_0/backward/currentState_reg[5]_bret__0_bret__3
cores_0/backward/currentState_reg[5]_bret__0_bret__4
cores_0/backward/currentState_reg[5]_bret__1
cores_0/backward/currentState_reg[5]_bret__2
cores_0/backward/currentState_reg[5]_bret__3
cores_1/backward/currentState_reg[0]_bret__0
cores_1/backward/currentState_reg[0]_bret__1
cores_1/backward/currentState_reg[0]_bret__2
cores_1/backward/currentState_reg[0]_bret__3
cores_1/backward/currentState_reg[0]_bret__4
cores_1/backward/currentState_reg[0]_bret_bret
cores_1/backward/currentState_reg[0]_bret_bret__0
cores_1/backward/currentState_reg[0]_bret_bret__1
cores_1/backward/currentState_reg[0]_bret_bret__2
cores_1/backward/currentState_reg[0]_bret_bret__3
cores_1/backward/currentState_reg[0]_bret_bret__4
cores_1/backward/currentState_reg[1]_bret
cores_1/backward/currentState_reg[1]_bret__1
cores_1/backward/currentState_reg[1]_bret__2
cores_1/backward/currentState_reg[1]_bret__3
cores_1/backward/currentState_reg[2]_bret
cores_1/backward/currentState_reg[2]_bret__1
cores_1/backward/currentState_reg[2]_bret__2
cores_1/backward/currentState_reg[2]_bret__3
cores_1/backward/currentState_reg[3]_bret
cores_1/backward/currentState_reg[3]_bret__1
cores_1/backward/currentState_reg[3]_bret__2
cores_1/backward/currentState_reg[3]_bret__3
cores_1/backward/currentState_reg[4]_bret
cores_1/backward/currentState_reg[4]_bret__1
cores_1/backward/currentState_reg[4]_bret__2
cores_1/backward/currentState_reg[4]_bret__3
cores_1/backward/currentState_reg[5]_bret
cores_1/backward/currentState_reg[5]_bret__0_bret
cores_1/backward/currentState_reg[5]_bret__0_bret__0
cores_1/backward/currentState_reg[5]_bret__0_bret__1
cores_1/backward/currentState_reg[5]_bret__0_bret__2
cores_1/backward/currentState_reg[5]_bret__0_bret__3
cores_1/backward/currentState_reg[5]_bret__0_bret__4
cores_1/backward/currentState_reg[5]_bret__1
cores_1/backward/currentState_reg[5]_bret__2
cores_1/backward/currentState_reg[5]_bret__3
cores_4/backward/currentState_reg[0]_bret__0
cores_4/backward/currentState_reg[0]_bret__1
cores_4/backward/currentState_reg[0]_bret__2
cores_4/backward/currentState_reg[0]_bret__3
cores_4/backward/currentState_reg[0]_bret__4
cores_4/backward/currentState_reg[0]_bret_bret
cores_4/backward/currentState_reg[0]_bret_bret__0
cores_4/backward/currentState_reg[0]_bret_bret__1
cores_4/backward/currentState_reg[0]_bret_bret__2
cores_4/backward/currentState_reg[0]_bret_bret__3
cores_4/backward/currentState_reg[0]_bret_bret__4
cores_4/backward/currentState_reg[1]_bret
cores_4/backward/currentState_reg[1]_bret__1
cores_4/backward/currentState_reg[1]_bret__2
cores_4/backward/currentState_reg[1]_bret__3
cores_4/backward/currentState_reg[2]_bret
cores_4/backward/currentState_reg[2]_bret__1
cores_4/backward/currentState_reg[2]_bret__2
cores_4/backward/currentState_reg[2]_bret__3
cores_4/backward/currentState_reg[3]_bret
cores_4/backward/currentState_reg[3]_bret__1
cores_4/backward/currentState_reg[3]_bret__2
cores_4/backward/currentState_reg[3]_bret__3
cores_4/backward/currentState_reg[4]_bret
cores_4/backward/currentState_reg[4]_bret__1
cores_4/backward/currentState_reg[4]_bret__2
cores_4/backward/currentState_reg[4]_bret__3
cores_4/backward/currentState_reg[5]_bret
cores_4/backward/currentState_reg[5]_bret__0_bret
cores_4/backward/currentState_reg[5]_bret__0_bret__0
cores_4/backward/currentState_reg[5]_bret__0_bret__1
cores_4/backward/currentState_reg[5]_bret__0_bret__2
cores_4/backward/currentState_reg[5]_bret__0_bret__3
cores_4/backward/currentState_reg[5]_bret__0_bret__4
cores_4/backward/currentState_reg[5]_bret__1
cores_4/backward/currentState_reg[5]_bret__2
cores_4/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB9_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB10_tempName`
Numbers of forward move = 0, and backward move = 88
Retimed registers names:
cores_110/backward/currentState_reg[0]_bret__0
cores_110/backward/currentState_reg[0]_bret__1
cores_110/backward/currentState_reg[0]_bret__2
cores_110/backward/currentState_reg[0]_bret__3
cores_110/backward/currentState_reg[0]_bret__4
cores_110/backward/currentState_reg[0]_bret_bret
cores_110/backward/currentState_reg[0]_bret_bret__0
cores_110/backward/currentState_reg[0]_bret_bret__1
cores_110/backward/currentState_reg[0]_bret_bret__2
cores_110/backward/currentState_reg[0]_bret_bret__3
cores_110/backward/currentState_reg[0]_bret_bret__4
cores_110/backward/currentState_reg[1]_bret
cores_110/backward/currentState_reg[1]_bret__1
cores_110/backward/currentState_reg[1]_bret__2
cores_110/backward/currentState_reg[1]_bret__3
cores_110/backward/currentState_reg[2]_bret
cores_110/backward/currentState_reg[2]_bret__1
cores_110/backward/currentState_reg[2]_bret__2
cores_110/backward/currentState_reg[2]_bret__3
cores_110/backward/currentState_reg[3]_bret
cores_110/backward/currentState_reg[3]_bret__1
cores_110/backward/currentState_reg[3]_bret__2
cores_110/backward/currentState_reg[3]_bret__3
cores_110/backward/currentState_reg[4]_bret
cores_110/backward/currentState_reg[4]_bret__1
cores_110/backward/currentState_reg[4]_bret__2
cores_110/backward/currentState_reg[4]_bret__3
cores_110/backward/currentState_reg[5]_bret
cores_110/backward/currentState_reg[5]_bret__0_bret
cores_110/backward/currentState_reg[5]_bret__0_bret__0
cores_110/backward/currentState_reg[5]_bret__0_bret__1
cores_110/backward/currentState_reg[5]_bret__0_bret__2
cores_110/backward/currentState_reg[5]_bret__0_bret__3
cores_110/backward/currentState_reg[5]_bret__0_bret__4
cores_110/backward/currentState_reg[5]_bret__1
cores_110/backward/currentState_reg[5]_bret__2
cores_110/backward/currentState_reg[5]_bret__3
cores_112/backward/currentState_reg[0]_bret__0
cores_112/backward/currentState_reg[0]_bret__1
cores_112/backward/currentState_reg[0]_bret__2
cores_112/backward/currentState_reg[0]_bret__3
cores_112/backward/currentState_reg[0]_bret__4
cores_112/backward/currentState_reg[0]_bret_bret
cores_112/backward/currentState_reg[0]_bret_bret__0
cores_112/backward/currentState_reg[0]_bret_bret__1
cores_112/backward/currentState_reg[0]_bret_bret__2
cores_112/backward/currentState_reg[0]_bret_bret__3
cores_112/backward/currentState_reg[0]_bret_bret__4
cores_112/backward/currentState_reg[1]_bret
cores_112/backward/currentState_reg[1]_bret__1
cores_112/backward/currentState_reg[1]_bret__2
cores_112/backward/currentState_reg[1]_bret__3
cores_112/backward/currentState_reg[2]_bret
cores_112/backward/currentState_reg[2]_bret__1
cores_112/backward/currentState_reg[2]_bret__2
cores_112/backward/currentState_reg[2]_bret__3
cores_112/backward/currentState_reg[3]_bret
cores_112/backward/currentState_reg[3]_bret__1
cores_112/backward/currentState_reg[3]_bret__2
cores_112/backward/currentState_reg[3]_bret__3
cores_112/backward/currentState_reg[4]_bret
cores_112/backward/currentState_reg[4]_bret__1
cores_112/backward/currentState_reg[4]_bret__2
cores_112/backward/currentState_reg[4]_bret__3
cores_112/backward/currentState_reg[5]_bret
cores_112/backward/currentState_reg[5]_bret__0_bret
cores_112/backward/currentState_reg[5]_bret__0_bret__0
cores_112/backward/currentState_reg[5]_bret__0_bret__1
cores_112/backward/currentState_reg[5]_bret__0_bret__2
cores_112/backward/currentState_reg[5]_bret__0_bret__3
cores_112/backward/currentState_reg[5]_bret__0_bret__4
cores_112/backward/currentState_reg[5]_bret__1
cores_112/backward/currentState_reg[5]_bret__2
cores_112/backward/currentState_reg[5]_bret__3
cores_113/backward/currentState_reg[0]_bret__0
cores_113/backward/currentState_reg[0]_bret__1
cores_113/backward/currentState_reg[0]_bret__2
cores_113/backward/currentState_reg[0]_bret__3
cores_113/backward/currentState_reg[0]_bret__4
cores_113/backward/currentState_reg[0]_bret_bret
cores_113/backward/currentState_reg[0]_bret_bret__0
cores_113/backward/currentState_reg[0]_bret_bret__1
cores_113/backward/currentState_reg[0]_bret_bret__2
cores_113/backward/currentState_reg[0]_bret_bret__3
cores_113/backward/currentState_reg[0]_bret_bret__4
cores_113/backward/currentState_reg[1]_bret
cores_113/backward/currentState_reg[1]_bret__1
cores_113/backward/currentState_reg[1]_bret__2
cores_113/backward/currentState_reg[1]_bret__3
cores_113/backward/currentState_reg[2]_bret
cores_113/backward/currentState_reg[2]_bret__1
cores_113/backward/currentState_reg[2]_bret__2
cores_113/backward/currentState_reg[2]_bret__3
cores_113/backward/currentState_reg[3]_bret
cores_113/backward/currentState_reg[3]_bret__1
cores_113/backward/currentState_reg[3]_bret__2
cores_113/backward/currentState_reg[3]_bret__3
cores_113/backward/currentState_reg[4]_bret
cores_113/backward/currentState_reg[4]_bret__1
cores_113/backward/currentState_reg[4]_bret__2
cores_113/backward/currentState_reg[4]_bret__3
cores_113/backward/currentState_reg[5]_bret
cores_113/backward/currentState_reg[5]_bret__0_bret
cores_113/backward/currentState_reg[5]_bret__0_bret__0
cores_113/backward/currentState_reg[5]_bret__0_bret__1
cores_113/backward/currentState_reg[5]_bret__0_bret__2
cores_113/backward/currentState_reg[5]_bret__0_bret__3
cores_113/backward/currentState_reg[5]_bret__0_bret__4
cores_113/backward/currentState_reg[5]_bret__1
cores_113/backward/currentState_reg[5]_bret__2
cores_113/backward/currentState_reg[5]_bret__3
cores_115/backward/currentState_reg[0]_bret__0
cores_115/backward/currentState_reg[0]_bret__1
cores_115/backward/currentState_reg[0]_bret__2
cores_115/backward/currentState_reg[0]_bret__3
cores_115/backward/currentState_reg[0]_bret__4
cores_115/backward/currentState_reg[0]_bret_bret
cores_115/backward/currentState_reg[0]_bret_bret__0
cores_115/backward/currentState_reg[0]_bret_bret__1
cores_115/backward/currentState_reg[0]_bret_bret__2
cores_115/backward/currentState_reg[0]_bret_bret__3
cores_115/backward/currentState_reg[0]_bret_bret__4
cores_115/backward/currentState_reg[1]_bret
cores_115/backward/currentState_reg[1]_bret__1
cores_115/backward/currentState_reg[1]_bret__2
cores_115/backward/currentState_reg[1]_bret__3
cores_115/backward/currentState_reg[2]_bret
cores_115/backward/currentState_reg[2]_bret__1
cores_115/backward/currentState_reg[2]_bret__2
cores_115/backward/currentState_reg[2]_bret__3
cores_115/backward/currentState_reg[3]_bret
cores_115/backward/currentState_reg[3]_bret__1
cores_115/backward/currentState_reg[3]_bret__2
cores_115/backward/currentState_reg[3]_bret__3
cores_115/backward/currentState_reg[4]_bret
cores_115/backward/currentState_reg[4]_bret__1
cores_115/backward/currentState_reg[4]_bret__2
cores_115/backward/currentState_reg[4]_bret__3
cores_115/backward/currentState_reg[5]_bret
cores_115/backward/currentState_reg[5]_bret__0_bret
cores_115/backward/currentState_reg[5]_bret__0_bret__0
cores_115/backward/currentState_reg[5]_bret__0_bret__1
cores_115/backward/currentState_reg[5]_bret__0_bret__2
cores_115/backward/currentState_reg[5]_bret__0_bret__3
cores_115/backward/currentState_reg[5]_bret__0_bret__4
cores_115/backward/currentState_reg[5]_bret__1
cores_115/backward/currentState_reg[5]_bret__2
cores_115/backward/currentState_reg[5]_bret__3
cores_116/backward/currentState_reg[0]_bret__0
cores_116/backward/currentState_reg[0]_bret__1
cores_116/backward/currentState_reg[0]_bret__2
cores_116/backward/currentState_reg[0]_bret__3
cores_116/backward/currentState_reg[0]_bret__4
cores_116/backward/currentState_reg[0]_bret_bret
cores_116/backward/currentState_reg[0]_bret_bret__0
cores_116/backward/currentState_reg[0]_bret_bret__1
cores_116/backward/currentState_reg[0]_bret_bret__2
cores_116/backward/currentState_reg[0]_bret_bret__3
cores_116/backward/currentState_reg[0]_bret_bret__4
cores_116/backward/currentState_reg[1]_bret
cores_116/backward/currentState_reg[1]_bret__1
cores_116/backward/currentState_reg[1]_bret__2
cores_116/backward/currentState_reg[1]_bret__3
cores_116/backward/currentState_reg[2]_bret
cores_116/backward/currentState_reg[2]_bret__1
cores_116/backward/currentState_reg[2]_bret__2
cores_116/backward/currentState_reg[2]_bret__3
cores_116/backward/currentState_reg[3]_bret
cores_116/backward/currentState_reg[3]_bret__1
cores_116/backward/currentState_reg[3]_bret__2
cores_116/backward/currentState_reg[3]_bret__3
cores_116/backward/currentState_reg[4]_bret
cores_116/backward/currentState_reg[4]_bret__1
cores_116/backward/currentState_reg[4]_bret__2
cores_116/backward/currentState_reg[4]_bret__3
cores_116/backward/currentState_reg[5]_bret
cores_116/backward/currentState_reg[5]_bret__0_bret
cores_116/backward/currentState_reg[5]_bret__0_bret__0
cores_116/backward/currentState_reg[5]_bret__0_bret__1
cores_116/backward/currentState_reg[5]_bret__0_bret__2
cores_116/backward/currentState_reg[5]_bret__0_bret__3
cores_116/backward/currentState_reg[5]_bret__0_bret__4
cores_116/backward/currentState_reg[5]_bret__1
cores_116/backward/currentState_reg[5]_bret__2
cores_116/backward/currentState_reg[5]_bret__3
cores_117/backward/currentState_reg[0]_bret__0
cores_117/backward/currentState_reg[0]_bret__1
cores_117/backward/currentState_reg[0]_bret__2
cores_117/backward/currentState_reg[0]_bret__3
cores_117/backward/currentState_reg[0]_bret__4
cores_117/backward/currentState_reg[0]_bret_bret
cores_117/backward/currentState_reg[0]_bret_bret__0
cores_117/backward/currentState_reg[0]_bret_bret__1
cores_117/backward/currentState_reg[0]_bret_bret__2
cores_117/backward/currentState_reg[0]_bret_bret__3
cores_117/backward/currentState_reg[0]_bret_bret__4
cores_117/backward/currentState_reg[1]_bret
cores_117/backward/currentState_reg[1]_bret__1
cores_117/backward/currentState_reg[1]_bret__2
cores_117/backward/currentState_reg[1]_bret__3
cores_117/backward/currentState_reg[2]_bret
cores_117/backward/currentState_reg[2]_bret__1
cores_117/backward/currentState_reg[2]_bret__2
cores_117/backward/currentState_reg[2]_bret__3
cores_117/backward/currentState_reg[3]_bret
cores_117/backward/currentState_reg[3]_bret__1
cores_117/backward/currentState_reg[3]_bret__2
cores_117/backward/currentState_reg[3]_bret__3
cores_117/backward/currentState_reg[4]_bret
cores_117/backward/currentState_reg[4]_bret__1
cores_117/backward/currentState_reg[4]_bret__2
cores_117/backward/currentState_reg[4]_bret__3
cores_117/backward/currentState_reg[5]_bret
cores_117/backward/currentState_reg[5]_bret__0_bret
cores_117/backward/currentState_reg[5]_bret__0_bret__0
cores_117/backward/currentState_reg[5]_bret__0_bret__1
cores_117/backward/currentState_reg[5]_bret__0_bret__2
cores_117/backward/currentState_reg[5]_bret__0_bret__3
cores_117/backward/currentState_reg[5]_bret__0_bret__4
cores_117/backward/currentState_reg[5]_bret__1
cores_117/backward/currentState_reg[5]_bret__2
cores_117/backward/currentState_reg[5]_bret__3
cores_118/backward/currentState_reg[0]_bret__0
cores_118/backward/currentState_reg[0]_bret__1
cores_118/backward/currentState_reg[0]_bret__2
cores_118/backward/currentState_reg[0]_bret__3
cores_118/backward/currentState_reg[0]_bret__4
cores_118/backward/currentState_reg[0]_bret_bret
cores_118/backward/currentState_reg[0]_bret_bret__0
cores_118/backward/currentState_reg[0]_bret_bret__1
cores_118/backward/currentState_reg[0]_bret_bret__2
cores_118/backward/currentState_reg[0]_bret_bret__3
cores_118/backward/currentState_reg[0]_bret_bret__4
cores_118/backward/currentState_reg[1]_bret
cores_118/backward/currentState_reg[1]_bret__1
cores_118/backward/currentState_reg[1]_bret__2
cores_118/backward/currentState_reg[1]_bret__3
cores_118/backward/currentState_reg[2]_bret
cores_118/backward/currentState_reg[2]_bret__1
cores_118/backward/currentState_reg[2]_bret__2
cores_118/backward/currentState_reg[2]_bret__3
cores_118/backward/currentState_reg[3]_bret
cores_118/backward/currentState_reg[3]_bret__1
cores_118/backward/currentState_reg[3]_bret__2
cores_118/backward/currentState_reg[3]_bret__3
cores_118/backward/currentState_reg[4]_bret
cores_118/backward/currentState_reg[4]_bret__1
cores_118/backward/currentState_reg[4]_bret__2
cores_118/backward/currentState_reg[4]_bret__3
cores_118/backward/currentState_reg[5]_bret
cores_118/backward/currentState_reg[5]_bret__0_bret
cores_118/backward/currentState_reg[5]_bret__0_bret__0
cores_118/backward/currentState_reg[5]_bret__0_bret__1
cores_118/backward/currentState_reg[5]_bret__0_bret__2
cores_118/backward/currentState_reg[5]_bret__0_bret__3
cores_118/backward/currentState_reg[5]_bret__0_bret__4
cores_118/backward/currentState_reg[5]_bret__1
cores_118/backward/currentState_reg[5]_bret__2
cores_118/backward/currentState_reg[5]_bret__3
cores_119/backward/currentState_reg[0]_bret__0
cores_119/backward/currentState_reg[0]_bret__1
cores_119/backward/currentState_reg[0]_bret__2
cores_119/backward/currentState_reg[0]_bret__3
cores_119/backward/currentState_reg[0]_bret__4
cores_119/backward/currentState_reg[0]_bret_bret
cores_119/backward/currentState_reg[0]_bret_bret__0
cores_119/backward/currentState_reg[0]_bret_bret__1
cores_119/backward/currentState_reg[0]_bret_bret__2
cores_119/backward/currentState_reg[0]_bret_bret__3
cores_119/backward/currentState_reg[0]_bret_bret__4
cores_119/backward/currentState_reg[1]_bret
cores_119/backward/currentState_reg[1]_bret__1
cores_119/backward/currentState_reg[1]_bret__2
cores_119/backward/currentState_reg[1]_bret__3
cores_119/backward/currentState_reg[2]_bret
cores_119/backward/currentState_reg[2]_bret__1
cores_119/backward/currentState_reg[2]_bret__2
cores_119/backward/currentState_reg[2]_bret__3
cores_119/backward/currentState_reg[3]_bret
cores_119/backward/currentState_reg[3]_bret__1
cores_119/backward/currentState_reg[3]_bret__2
cores_119/backward/currentState_reg[3]_bret__3
cores_119/backward/currentState_reg[4]_bret
cores_119/backward/currentState_reg[4]_bret__1
cores_119/backward/currentState_reg[4]_bret__2
cores_119/backward/currentState_reg[4]_bret__3
cores_119/backward/currentState_reg[5]_bret
cores_119/backward/currentState_reg[5]_bret__0_bret
cores_119/backward/currentState_reg[5]_bret__0_bret__0
cores_119/backward/currentState_reg[5]_bret__0_bret__1
cores_119/backward/currentState_reg[5]_bret__0_bret__2
cores_119/backward/currentState_reg[5]_bret__0_bret__3
cores_119/backward/currentState_reg[5]_bret__0_bret__4
cores_119/backward/currentState_reg[5]_bret__1
cores_119/backward/currentState_reg[5]_bret__2
cores_119/backward/currentState_reg[5]_bret__3
cores_120/backward/currentState_reg[0]_bret__0
cores_120/backward/currentState_reg[0]_bret__1
cores_120/backward/currentState_reg[0]_bret__2
cores_120/backward/currentState_reg[0]_bret__3
cores_120/backward/currentState_reg[0]_bret__4
cores_120/backward/currentState_reg[0]_bret_bret
cores_120/backward/currentState_reg[0]_bret_bret__0
cores_120/backward/currentState_reg[0]_bret_bret__1
cores_120/backward/currentState_reg[0]_bret_bret__2
cores_120/backward/currentState_reg[0]_bret_bret__3
cores_120/backward/currentState_reg[0]_bret_bret__4
cores_120/backward/currentState_reg[1]_bret
cores_120/backward/currentState_reg[1]_bret__1
cores_120/backward/currentState_reg[1]_bret__2
cores_120/backward/currentState_reg[1]_bret__3
cores_120/backward/currentState_reg[2]_bret
cores_120/backward/currentState_reg[2]_bret__1
cores_120/backward/currentState_reg[2]_bret__2
cores_120/backward/currentState_reg[2]_bret__3
cores_120/backward/currentState_reg[3]_bret
cores_120/backward/currentState_reg[3]_bret__1
cores_120/backward/currentState_reg[3]_bret__2
cores_120/backward/currentState_reg[3]_bret__3
cores_120/backward/currentState_reg[4]_bret
cores_120/backward/currentState_reg[4]_bret__1
cores_120/backward/currentState_reg[4]_bret__2
cores_120/backward/currentState_reg[4]_bret__3
cores_120/backward/currentState_reg[5]_bret
cores_120/backward/currentState_reg[5]_bret__0_bret
cores_120/backward/currentState_reg[5]_bret__0_bret__0
cores_120/backward/currentState_reg[5]_bret__0_bret__1
cores_120/backward/currentState_reg[5]_bret__0_bret__2
cores_120/backward/currentState_reg[5]_bret__0_bret__3
cores_120/backward/currentState_reg[5]_bret__0_bret__4
cores_120/backward/currentState_reg[5]_bret__1
cores_120/backward/currentState_reg[5]_bret__2
cores_120/backward/currentState_reg[5]_bret__3
cores_121/backward/currentState_reg[0]_bret__0
cores_121/backward/currentState_reg[0]_bret__1
cores_121/backward/currentState_reg[0]_bret__2
cores_121/backward/currentState_reg[0]_bret__3
cores_121/backward/currentState_reg[0]_bret__4
cores_121/backward/currentState_reg[0]_bret_bret
cores_121/backward/currentState_reg[0]_bret_bret__0
cores_121/backward/currentState_reg[0]_bret_bret__1
cores_121/backward/currentState_reg[0]_bret_bret__2
cores_121/backward/currentState_reg[0]_bret_bret__3
cores_121/backward/currentState_reg[0]_bret_bret__4
cores_121/backward/currentState_reg[1]_bret
cores_121/backward/currentState_reg[1]_bret__1
cores_121/backward/currentState_reg[1]_bret__2
cores_121/backward/currentState_reg[1]_bret__3
cores_121/backward/currentState_reg[2]_bret
cores_121/backward/currentState_reg[2]_bret__1
cores_121/backward/currentState_reg[2]_bret__2
cores_121/backward/currentState_reg[2]_bret__3
cores_121/backward/currentState_reg[3]_bret
cores_121/backward/currentState_reg[3]_bret__1
cores_121/backward/currentState_reg[3]_bret__2
cores_121/backward/currentState_reg[3]_bret__3
cores_121/backward/currentState_reg[4]_bret
cores_121/backward/currentState_reg[4]_bret__1
cores_121/backward/currentState_reg[4]_bret__2
cores_121/backward/currentState_reg[4]_bret__3
cores_121/backward/currentState_reg[5]_bret
cores_121/backward/currentState_reg[5]_bret__0_bret
cores_121/backward/currentState_reg[5]_bret__0_bret__0
cores_121/backward/currentState_reg[5]_bret__0_bret__1
cores_121/backward/currentState_reg[5]_bret__0_bret__2
cores_121/backward/currentState_reg[5]_bret__0_bret__3
cores_121/backward/currentState_reg[5]_bret__0_bret__4
cores_121/backward/currentState_reg[5]_bret__1
cores_121/backward/currentState_reg[5]_bret__2
cores_121/backward/currentState_reg[5]_bret__3
cores_123/backward/currentState_reg[0]_bret__0
cores_123/backward/currentState_reg[0]_bret__1
cores_123/backward/currentState_reg[0]_bret__2
cores_123/backward/currentState_reg[0]_bret__3
cores_123/backward/currentState_reg[0]_bret__4
cores_123/backward/currentState_reg[0]_bret_bret
cores_123/backward/currentState_reg[0]_bret_bret__0
cores_123/backward/currentState_reg[0]_bret_bret__1
cores_123/backward/currentState_reg[0]_bret_bret__2
cores_123/backward/currentState_reg[0]_bret_bret__3
cores_123/backward/currentState_reg[0]_bret_bret__4
cores_123/backward/currentState_reg[1]_bret
cores_123/backward/currentState_reg[1]_bret__1
cores_123/backward/currentState_reg[1]_bret__2
cores_123/backward/currentState_reg[1]_bret__3
cores_123/backward/currentState_reg[2]_bret
cores_123/backward/currentState_reg[2]_bret__1
cores_123/backward/currentState_reg[2]_bret__2
cores_123/backward/currentState_reg[2]_bret__3
cores_123/backward/currentState_reg[3]_bret
cores_123/backward/currentState_reg[3]_bret__1
cores_123/backward/currentState_reg[3]_bret__2
cores_123/backward/currentState_reg[3]_bret__3
cores_123/backward/currentState_reg[4]_bret
cores_123/backward/currentState_reg[4]_bret__1
cores_123/backward/currentState_reg[4]_bret__2
cores_123/backward/currentState_reg[4]_bret__3
cores_123/backward/currentState_reg[5]_bret
cores_123/backward/currentState_reg[5]_bret__0_bret
cores_123/backward/currentState_reg[5]_bret__0_bret__0
cores_123/backward/currentState_reg[5]_bret__0_bret__1
cores_123/backward/currentState_reg[5]_bret__0_bret__2
cores_123/backward/currentState_reg[5]_bret__0_bret__3
cores_123/backward/currentState_reg[5]_bret__0_bret__4
cores_123/backward/currentState_reg[5]_bret__1
cores_123/backward/currentState_reg[5]_bret__2
cores_123/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB10_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB11_tempName`
Numbers of forward move = 0, and backward move = 24
Retimed registers names:
cores_108/backward/currentState_reg[0]_bret__0
cores_108/backward/currentState_reg[0]_bret__1
cores_108/backward/currentState_reg[0]_bret__2
cores_108/backward/currentState_reg[0]_bret__3
cores_108/backward/currentState_reg[0]_bret__4
cores_108/backward/currentState_reg[0]_bret_bret
cores_108/backward/currentState_reg[0]_bret_bret__0
cores_108/backward/currentState_reg[0]_bret_bret__1
cores_108/backward/currentState_reg[0]_bret_bret__2
cores_108/backward/currentState_reg[0]_bret_bret__3
cores_108/backward/currentState_reg[0]_bret_bret__4
cores_108/backward/currentState_reg[1]_bret
cores_108/backward/currentState_reg[1]_bret__1
cores_108/backward/currentState_reg[1]_bret__2
cores_108/backward/currentState_reg[1]_bret__3
cores_108/backward/currentState_reg[2]_bret
cores_108/backward/currentState_reg[2]_bret__1
cores_108/backward/currentState_reg[2]_bret__2
cores_108/backward/currentState_reg[2]_bret__3
cores_108/backward/currentState_reg[3]_bret
cores_108/backward/currentState_reg[3]_bret__1
cores_108/backward/currentState_reg[3]_bret__2
cores_108/backward/currentState_reg[3]_bret__3
cores_108/backward/currentState_reg[4]_bret
cores_108/backward/currentState_reg[4]_bret__1
cores_108/backward/currentState_reg[4]_bret__2
cores_108/backward/currentState_reg[4]_bret__3
cores_108/backward/currentState_reg[5]_bret
cores_108/backward/currentState_reg[5]_bret__0_bret
cores_108/backward/currentState_reg[5]_bret__0_bret__0
cores_108/backward/currentState_reg[5]_bret__0_bret__1
cores_108/backward/currentState_reg[5]_bret__0_bret__2
cores_108/backward/currentState_reg[5]_bret__0_bret__3
cores_108/backward/currentState_reg[5]_bret__0_bret__4
cores_108/backward/currentState_reg[5]_bret__1
cores_108/backward/currentState_reg[5]_bret__2
cores_108/backward/currentState_reg[5]_bret__3
cores_109/backward/currentState_reg[0]_bret__0
cores_109/backward/currentState_reg[0]_bret__1
cores_109/backward/currentState_reg[0]_bret__2
cores_109/backward/currentState_reg[0]_bret__3
cores_109/backward/currentState_reg[0]_bret__4
cores_109/backward/currentState_reg[0]_bret_bret
cores_109/backward/currentState_reg[0]_bret_bret__0
cores_109/backward/currentState_reg[0]_bret_bret__1
cores_109/backward/currentState_reg[0]_bret_bret__2
cores_109/backward/currentState_reg[0]_bret_bret__3
cores_109/backward/currentState_reg[0]_bret_bret__4
cores_109/backward/currentState_reg[1]_bret
cores_109/backward/currentState_reg[1]_bret__1
cores_109/backward/currentState_reg[1]_bret__2
cores_109/backward/currentState_reg[1]_bret__3
cores_109/backward/currentState_reg[2]_bret
cores_109/backward/currentState_reg[2]_bret__1
cores_109/backward/currentState_reg[2]_bret__2
cores_109/backward/currentState_reg[2]_bret__3
cores_109/backward/currentState_reg[3]_bret
cores_109/backward/currentState_reg[3]_bret__1
cores_109/backward/currentState_reg[3]_bret__2
cores_109/backward/currentState_reg[3]_bret__3
cores_109/backward/currentState_reg[4]_bret
cores_109/backward/currentState_reg[4]_bret__1
cores_109/backward/currentState_reg[4]_bret__2
cores_109/backward/currentState_reg[4]_bret__3
cores_109/backward/currentState_reg[5]_bret
cores_109/backward/currentState_reg[5]_bret__0_bret
cores_109/backward/currentState_reg[5]_bret__0_bret__0
cores_109/backward/currentState_reg[5]_bret__0_bret__1
cores_109/backward/currentState_reg[5]_bret__0_bret__2
cores_109/backward/currentState_reg[5]_bret__0_bret__3
cores_109/backward/currentState_reg[5]_bret__0_bret__4
cores_109/backward/currentState_reg[5]_bret__1
cores_109/backward/currentState_reg[5]_bret__2
cores_109/backward/currentState_reg[5]_bret__3
cores_114/backward/currentState_reg[0]_bret__0
cores_114/backward/currentState_reg[0]_bret__1
cores_114/backward/currentState_reg[0]_bret__2
cores_114/backward/currentState_reg[0]_bret__3
cores_114/backward/currentState_reg[0]_bret__4
cores_114/backward/currentState_reg[0]_bret_bret
cores_114/backward/currentState_reg[0]_bret_bret__0
cores_114/backward/currentState_reg[0]_bret_bret__1
cores_114/backward/currentState_reg[0]_bret_bret__2
cores_114/backward/currentState_reg[0]_bret_bret__3
cores_114/backward/currentState_reg[0]_bret_bret__4
cores_114/backward/currentState_reg[1]_bret
cores_114/backward/currentState_reg[1]_bret__1
cores_114/backward/currentState_reg[1]_bret__2
cores_114/backward/currentState_reg[1]_bret__3
cores_114/backward/currentState_reg[2]_bret
cores_114/backward/currentState_reg[2]_bret__1
cores_114/backward/currentState_reg[2]_bret__2
cores_114/backward/currentState_reg[2]_bret__3
cores_114/backward/currentState_reg[3]_bret
cores_114/backward/currentState_reg[3]_bret__1
cores_114/backward/currentState_reg[3]_bret__2
cores_114/backward/currentState_reg[3]_bret__3
cores_114/backward/currentState_reg[4]_bret
cores_114/backward/currentState_reg[4]_bret__1
cores_114/backward/currentState_reg[4]_bret__2
cores_114/backward/currentState_reg[4]_bret__3
cores_114/backward/currentState_reg[5]_bret
cores_114/backward/currentState_reg[5]_bret__0_bret
cores_114/backward/currentState_reg[5]_bret__0_bret__0
cores_114/backward/currentState_reg[5]_bret__0_bret__1
cores_114/backward/currentState_reg[5]_bret__0_bret__2
cores_114/backward/currentState_reg[5]_bret__0_bret__3
cores_114/backward/currentState_reg[5]_bret__0_bret__4
cores_114/backward/currentState_reg[5]_bret__1
cores_114/backward/currentState_reg[5]_bret__2
cores_114/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB11_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB12_tempName`
Numbers of forward move = 0, and backward move = 32
Retimed registers names:
cores_105/backward/currentState_reg[0]_bret__0
cores_105/backward/currentState_reg[0]_bret__1
cores_105/backward/currentState_reg[0]_bret__2
cores_105/backward/currentState_reg[0]_bret__3
cores_105/backward/currentState_reg[0]_bret__4
cores_105/backward/currentState_reg[0]_bret_bret
cores_105/backward/currentState_reg[0]_bret_bret__0
cores_105/backward/currentState_reg[0]_bret_bret__1
cores_105/backward/currentState_reg[0]_bret_bret__2
cores_105/backward/currentState_reg[0]_bret_bret__3
cores_105/backward/currentState_reg[0]_bret_bret__4
cores_105/backward/currentState_reg[1]_bret
cores_105/backward/currentState_reg[1]_bret__1
cores_105/backward/currentState_reg[1]_bret__2
cores_105/backward/currentState_reg[1]_bret__3
cores_105/backward/currentState_reg[2]_bret
cores_105/backward/currentState_reg[2]_bret__1
cores_105/backward/currentState_reg[2]_bret__2
cores_105/backward/currentState_reg[2]_bret__3
cores_105/backward/currentState_reg[3]_bret
cores_105/backward/currentState_reg[3]_bret__1
cores_105/backward/currentState_reg[3]_bret__2
cores_105/backward/currentState_reg[3]_bret__3
cores_105/backward/currentState_reg[4]_bret
cores_105/backward/currentState_reg[4]_bret__1
cores_105/backward/currentState_reg[4]_bret__2
cores_105/backward/currentState_reg[4]_bret__3
cores_105/backward/currentState_reg[5]_bret
cores_105/backward/currentState_reg[5]_bret__0_bret
cores_105/backward/currentState_reg[5]_bret__0_bret__0
cores_105/backward/currentState_reg[5]_bret__0_bret__1
cores_105/backward/currentState_reg[5]_bret__0_bret__2
cores_105/backward/currentState_reg[5]_bret__0_bret__3
cores_105/backward/currentState_reg[5]_bret__0_bret__4
cores_105/backward/currentState_reg[5]_bret__1
cores_105/backward/currentState_reg[5]_bret__2
cores_105/backward/currentState_reg[5]_bret__3
cores_106/backward/currentState_reg[0]_bret__0
cores_106/backward/currentState_reg[0]_bret__1
cores_106/backward/currentState_reg[0]_bret__2
cores_106/backward/currentState_reg[0]_bret__3
cores_106/backward/currentState_reg[0]_bret__4
cores_106/backward/currentState_reg[0]_bret_bret
cores_106/backward/currentState_reg[0]_bret_bret__0
cores_106/backward/currentState_reg[0]_bret_bret__1
cores_106/backward/currentState_reg[0]_bret_bret__2
cores_106/backward/currentState_reg[0]_bret_bret__3
cores_106/backward/currentState_reg[0]_bret_bret__4
cores_106/backward/currentState_reg[1]_bret
cores_106/backward/currentState_reg[1]_bret__1
cores_106/backward/currentState_reg[1]_bret__2
cores_106/backward/currentState_reg[1]_bret__3
cores_106/backward/currentState_reg[2]_bret
cores_106/backward/currentState_reg[2]_bret__1
cores_106/backward/currentState_reg[2]_bret__2
cores_106/backward/currentState_reg[2]_bret__3
cores_106/backward/currentState_reg[3]_bret
cores_106/backward/currentState_reg[3]_bret__1
cores_106/backward/currentState_reg[3]_bret__2
cores_106/backward/currentState_reg[3]_bret__3
cores_106/backward/currentState_reg[4]_bret
cores_106/backward/currentState_reg[4]_bret__1
cores_106/backward/currentState_reg[4]_bret__2
cores_106/backward/currentState_reg[4]_bret__3
cores_106/backward/currentState_reg[5]_bret
cores_106/backward/currentState_reg[5]_bret__0_bret
cores_106/backward/currentState_reg[5]_bret__0_bret__0
cores_106/backward/currentState_reg[5]_bret__0_bret__1
cores_106/backward/currentState_reg[5]_bret__0_bret__2
cores_106/backward/currentState_reg[5]_bret__0_bret__3
cores_106/backward/currentState_reg[5]_bret__0_bret__4
cores_106/backward/currentState_reg[5]_bret__1
cores_106/backward/currentState_reg[5]_bret__2
cores_106/backward/currentState_reg[5]_bret__3
cores_107/backward/currentState_reg[0]_bret__0
cores_107/backward/currentState_reg[0]_bret__1
cores_107/backward/currentState_reg[0]_bret__2
cores_107/backward/currentState_reg[0]_bret__3
cores_107/backward/currentState_reg[0]_bret__4
cores_107/backward/currentState_reg[0]_bret_bret
cores_107/backward/currentState_reg[0]_bret_bret__0
cores_107/backward/currentState_reg[0]_bret_bret__1
cores_107/backward/currentState_reg[0]_bret_bret__2
cores_107/backward/currentState_reg[0]_bret_bret__3
cores_107/backward/currentState_reg[0]_bret_bret__4
cores_107/backward/currentState_reg[1]_bret
cores_107/backward/currentState_reg[1]_bret__1
cores_107/backward/currentState_reg[1]_bret__2
cores_107/backward/currentState_reg[1]_bret__3
cores_107/backward/currentState_reg[2]_bret
cores_107/backward/currentState_reg[2]_bret__1
cores_107/backward/currentState_reg[2]_bret__2
cores_107/backward/currentState_reg[2]_bret__3
cores_107/backward/currentState_reg[3]_bret
cores_107/backward/currentState_reg[3]_bret__1
cores_107/backward/currentState_reg[3]_bret__2
cores_107/backward/currentState_reg[3]_bret__3
cores_107/backward/currentState_reg[4]_bret
cores_107/backward/currentState_reg[4]_bret__1
cores_107/backward/currentState_reg[4]_bret__2
cores_107/backward/currentState_reg[4]_bret__3
cores_107/backward/currentState_reg[5]_bret
cores_107/backward/currentState_reg[5]_bret__0_bret
cores_107/backward/currentState_reg[5]_bret__0_bret__0
cores_107/backward/currentState_reg[5]_bret__0_bret__1
cores_107/backward/currentState_reg[5]_bret__0_bret__2
cores_107/backward/currentState_reg[5]_bret__0_bret__3
cores_107/backward/currentState_reg[5]_bret__0_bret__4
cores_107/backward/currentState_reg[5]_bret__1
cores_107/backward/currentState_reg[5]_bret__2
cores_107/backward/currentState_reg[5]_bret__3
cores_111/backward/currentState_reg[0]_bret__0
cores_111/backward/currentState_reg[0]_bret__1
cores_111/backward/currentState_reg[0]_bret__2
cores_111/backward/currentState_reg[0]_bret__3
cores_111/backward/currentState_reg[0]_bret__4
cores_111/backward/currentState_reg[0]_bret_bret
cores_111/backward/currentState_reg[0]_bret_bret__0
cores_111/backward/currentState_reg[0]_bret_bret__1
cores_111/backward/currentState_reg[0]_bret_bret__2
cores_111/backward/currentState_reg[0]_bret_bret__3
cores_111/backward/currentState_reg[0]_bret_bret__4
cores_111/backward/currentState_reg[1]_bret
cores_111/backward/currentState_reg[1]_bret__1
cores_111/backward/currentState_reg[1]_bret__2
cores_111/backward/currentState_reg[1]_bret__3
cores_111/backward/currentState_reg[2]_bret
cores_111/backward/currentState_reg[2]_bret__1
cores_111/backward/currentState_reg[2]_bret__2
cores_111/backward/currentState_reg[2]_bret__3
cores_111/backward/currentState_reg[3]_bret
cores_111/backward/currentState_reg[3]_bret__1
cores_111/backward/currentState_reg[3]_bret__2
cores_111/backward/currentState_reg[3]_bret__3
cores_111/backward/currentState_reg[4]_bret
cores_111/backward/currentState_reg[4]_bret__1
cores_111/backward/currentState_reg[4]_bret__2
cores_111/backward/currentState_reg[4]_bret__3
cores_111/backward/currentState_reg[5]_bret
cores_111/backward/currentState_reg[5]_bret__0_bret
cores_111/backward/currentState_reg[5]_bret__0_bret__0
cores_111/backward/currentState_reg[5]_bret__0_bret__1
cores_111/backward/currentState_reg[5]_bret__0_bret__2
cores_111/backward/currentState_reg[5]_bret__0_bret__3
cores_111/backward/currentState_reg[5]_bret__0_bret__4
cores_111/backward/currentState_reg[5]_bret__1
cores_111/backward/currentState_reg[5]_bret__2
cores_111/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB12_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB13_tempName`
Numbers of forward move = 0, and backward move = 40
Retimed registers names:
cores_100/backward/currentState_reg[0]_bret__0
cores_100/backward/currentState_reg[0]_bret__1
cores_100/backward/currentState_reg[0]_bret__2
cores_100/backward/currentState_reg[0]_bret__3
cores_100/backward/currentState_reg[0]_bret__4
cores_100/backward/currentState_reg[0]_bret_bret
cores_100/backward/currentState_reg[0]_bret_bret__0
cores_100/backward/currentState_reg[0]_bret_bret__1
cores_100/backward/currentState_reg[0]_bret_bret__2
cores_100/backward/currentState_reg[0]_bret_bret__3
cores_100/backward/currentState_reg[0]_bret_bret__4
cores_100/backward/currentState_reg[1]_bret
cores_100/backward/currentState_reg[1]_bret__1
cores_100/backward/currentState_reg[1]_bret__2
cores_100/backward/currentState_reg[1]_bret__3
cores_100/backward/currentState_reg[2]_bret
cores_100/backward/currentState_reg[2]_bret__1
cores_100/backward/currentState_reg[2]_bret__2
cores_100/backward/currentState_reg[2]_bret__3
cores_100/backward/currentState_reg[3]_bret
cores_100/backward/currentState_reg[3]_bret__1
cores_100/backward/currentState_reg[3]_bret__2
cores_100/backward/currentState_reg[3]_bret__3
cores_100/backward/currentState_reg[4]_bret
cores_100/backward/currentState_reg[4]_bret__1
cores_100/backward/currentState_reg[4]_bret__2
cores_100/backward/currentState_reg[4]_bret__3
cores_100/backward/currentState_reg[5]_bret
cores_100/backward/currentState_reg[5]_bret__0_bret
cores_100/backward/currentState_reg[5]_bret__0_bret__0
cores_100/backward/currentState_reg[5]_bret__0_bret__1
cores_100/backward/currentState_reg[5]_bret__0_bret__2
cores_100/backward/currentState_reg[5]_bret__0_bret__3
cores_100/backward/currentState_reg[5]_bret__0_bret__4
cores_100/backward/currentState_reg[5]_bret__1
cores_100/backward/currentState_reg[5]_bret__2
cores_100/backward/currentState_reg[5]_bret__3
cores_101/backward/currentState_reg[0]_bret__0
cores_101/backward/currentState_reg[0]_bret__1
cores_101/backward/currentState_reg[0]_bret__2
cores_101/backward/currentState_reg[0]_bret__3
cores_101/backward/currentState_reg[0]_bret__4
cores_101/backward/currentState_reg[0]_bret_bret
cores_101/backward/currentState_reg[0]_bret_bret__0
cores_101/backward/currentState_reg[0]_bret_bret__1
cores_101/backward/currentState_reg[0]_bret_bret__2
cores_101/backward/currentState_reg[0]_bret_bret__3
cores_101/backward/currentState_reg[0]_bret_bret__4
cores_101/backward/currentState_reg[1]_bret
cores_101/backward/currentState_reg[1]_bret__1
cores_101/backward/currentState_reg[1]_bret__2
cores_101/backward/currentState_reg[1]_bret__3
cores_101/backward/currentState_reg[2]_bret
cores_101/backward/currentState_reg[2]_bret__1
cores_101/backward/currentState_reg[2]_bret__2
cores_101/backward/currentState_reg[2]_bret__3
cores_101/backward/currentState_reg[3]_bret
cores_101/backward/currentState_reg[3]_bret__1
cores_101/backward/currentState_reg[3]_bret__2
cores_101/backward/currentState_reg[3]_bret__3
cores_101/backward/currentState_reg[4]_bret
cores_101/backward/currentState_reg[4]_bret__1
cores_101/backward/currentState_reg[4]_bret__2
cores_101/backward/currentState_reg[4]_bret__3
cores_101/backward/currentState_reg[5]_bret
cores_101/backward/currentState_reg[5]_bret__0_bret
cores_101/backward/currentState_reg[5]_bret__0_bret__0
cores_101/backward/currentState_reg[5]_bret__0_bret__1
cores_101/backward/currentState_reg[5]_bret__0_bret__2
cores_101/backward/currentState_reg[5]_bret__0_bret__3
cores_101/backward/currentState_reg[5]_bret__0_bret__4
cores_101/backward/currentState_reg[5]_bret__1
cores_101/backward/currentState_reg[5]_bret__2
cores_101/backward/currentState_reg[5]_bret__3
cores_102/backward/currentState_reg[0]_bret__0
cores_102/backward/currentState_reg[0]_bret__1
cores_102/backward/currentState_reg[0]_bret__2
cores_102/backward/currentState_reg[0]_bret__3
cores_102/backward/currentState_reg[0]_bret__4
cores_102/backward/currentState_reg[0]_bret_bret
cores_102/backward/currentState_reg[0]_bret_bret__0
cores_102/backward/currentState_reg[0]_bret_bret__1
cores_102/backward/currentState_reg[0]_bret_bret__2
cores_102/backward/currentState_reg[0]_bret_bret__3
cores_102/backward/currentState_reg[0]_bret_bret__4
cores_102/backward/currentState_reg[1]_bret
cores_102/backward/currentState_reg[1]_bret__1
cores_102/backward/currentState_reg[1]_bret__2
cores_102/backward/currentState_reg[1]_bret__3
cores_102/backward/currentState_reg[2]_bret
cores_102/backward/currentState_reg[2]_bret__1
cores_102/backward/currentState_reg[2]_bret__2
cores_102/backward/currentState_reg[2]_bret__3
cores_102/backward/currentState_reg[3]_bret
cores_102/backward/currentState_reg[3]_bret__1
cores_102/backward/currentState_reg[3]_bret__2
cores_102/backward/currentState_reg[3]_bret__3
cores_102/backward/currentState_reg[4]_bret
cores_102/backward/currentState_reg[4]_bret__1
cores_102/backward/currentState_reg[4]_bret__2
cores_102/backward/currentState_reg[4]_bret__3
cores_102/backward/currentState_reg[5]_bret
cores_102/backward/currentState_reg[5]_bret__0_bret
cores_102/backward/currentState_reg[5]_bret__0_bret__0
cores_102/backward/currentState_reg[5]_bret__0_bret__1
cores_102/backward/currentState_reg[5]_bret__0_bret__2
cores_102/backward/currentState_reg[5]_bret__0_bret__3
cores_102/backward/currentState_reg[5]_bret__0_bret__4
cores_102/backward/currentState_reg[5]_bret__1
cores_102/backward/currentState_reg[5]_bret__2
cores_102/backward/currentState_reg[5]_bret__3
cores_103/backward/currentState_reg[0]_bret__0
cores_103/backward/currentState_reg[0]_bret__1
cores_103/backward/currentState_reg[0]_bret__2
cores_103/backward/currentState_reg[0]_bret__3
cores_103/backward/currentState_reg[0]_bret__4
cores_103/backward/currentState_reg[0]_bret_bret
cores_103/backward/currentState_reg[0]_bret_bret__0
cores_103/backward/currentState_reg[0]_bret_bret__1
cores_103/backward/currentState_reg[0]_bret_bret__2
cores_103/backward/currentState_reg[0]_bret_bret__3
cores_103/backward/currentState_reg[0]_bret_bret__4
cores_103/backward/currentState_reg[1]_bret
cores_103/backward/currentState_reg[1]_bret__1
cores_103/backward/currentState_reg[1]_bret__2
cores_103/backward/currentState_reg[1]_bret__3
cores_103/backward/currentState_reg[2]_bret
cores_103/backward/currentState_reg[2]_bret__1
cores_103/backward/currentState_reg[2]_bret__2
cores_103/backward/currentState_reg[2]_bret__3
cores_103/backward/currentState_reg[3]_bret
cores_103/backward/currentState_reg[3]_bret__1
cores_103/backward/currentState_reg[3]_bret__2
cores_103/backward/currentState_reg[3]_bret__3
cores_103/backward/currentState_reg[4]_bret
cores_103/backward/currentState_reg[4]_bret__1
cores_103/backward/currentState_reg[4]_bret__2
cores_103/backward/currentState_reg[4]_bret__3
cores_103/backward/currentState_reg[5]_bret
cores_103/backward/currentState_reg[5]_bret__0_bret
cores_103/backward/currentState_reg[5]_bret__0_bret__0
cores_103/backward/currentState_reg[5]_bret__0_bret__1
cores_103/backward/currentState_reg[5]_bret__0_bret__2
cores_103/backward/currentState_reg[5]_bret__0_bret__3
cores_103/backward/currentState_reg[5]_bret__0_bret__4
cores_103/backward/currentState_reg[5]_bret__1
cores_103/backward/currentState_reg[5]_bret__2
cores_103/backward/currentState_reg[5]_bret__3
cores_122/backward/currentState_reg[0]_bret__0
cores_122/backward/currentState_reg[0]_bret__1
cores_122/backward/currentState_reg[0]_bret__2
cores_122/backward/currentState_reg[0]_bret__3
cores_122/backward/currentState_reg[0]_bret__4
cores_122/backward/currentState_reg[0]_bret_bret
cores_122/backward/currentState_reg[0]_bret_bret__0
cores_122/backward/currentState_reg[0]_bret_bret__1
cores_122/backward/currentState_reg[0]_bret_bret__2
cores_122/backward/currentState_reg[0]_bret_bret__3
cores_122/backward/currentState_reg[0]_bret_bret__4
cores_122/backward/currentState_reg[1]_bret
cores_122/backward/currentState_reg[1]_bret__1
cores_122/backward/currentState_reg[1]_bret__2
cores_122/backward/currentState_reg[1]_bret__3
cores_122/backward/currentState_reg[2]_bret
cores_122/backward/currentState_reg[2]_bret__1
cores_122/backward/currentState_reg[2]_bret__2
cores_122/backward/currentState_reg[2]_bret__3
cores_122/backward/currentState_reg[3]_bret
cores_122/backward/currentState_reg[3]_bret__1
cores_122/backward/currentState_reg[3]_bret__2
cores_122/backward/currentState_reg[3]_bret__3
cores_122/backward/currentState_reg[4]_bret
cores_122/backward/currentState_reg[4]_bret__1
cores_122/backward/currentState_reg[4]_bret__2
cores_122/backward/currentState_reg[4]_bret__3
cores_122/backward/currentState_reg[5]_bret
cores_122/backward/currentState_reg[5]_bret__0_bret
cores_122/backward/currentState_reg[5]_bret__0_bret__0
cores_122/backward/currentState_reg[5]_bret__0_bret__1
cores_122/backward/currentState_reg[5]_bret__0_bret__2
cores_122/backward/currentState_reg[5]_bret__0_bret__3
cores_122/backward/currentState_reg[5]_bret__0_bret__4
cores_122/backward/currentState_reg[5]_bret__1
cores_122/backward/currentState_reg[5]_bret__2
cores_122/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB13_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB14_tempName`
Numbers of forward move = 0, and backward move = 48
Retimed registers names:
cores_94/backward/currentState_reg[0]_bret__0
cores_94/backward/currentState_reg[0]_bret__1
cores_94/backward/currentState_reg[0]_bret__2
cores_94/backward/currentState_reg[0]_bret__3
cores_94/backward/currentState_reg[0]_bret__4
cores_94/backward/currentState_reg[0]_bret_bret
cores_94/backward/currentState_reg[0]_bret_bret__0
cores_94/backward/currentState_reg[0]_bret_bret__1
cores_94/backward/currentState_reg[0]_bret_bret__2
cores_94/backward/currentState_reg[0]_bret_bret__3
cores_94/backward/currentState_reg[0]_bret_bret__4
cores_94/backward/currentState_reg[1]_bret
cores_94/backward/currentState_reg[1]_bret__1
cores_94/backward/currentState_reg[1]_bret__2
cores_94/backward/currentState_reg[1]_bret__3
cores_94/backward/currentState_reg[2]_bret
cores_94/backward/currentState_reg[2]_bret__1
cores_94/backward/currentState_reg[2]_bret__2
cores_94/backward/currentState_reg[2]_bret__3
cores_94/backward/currentState_reg[3]_bret
cores_94/backward/currentState_reg[3]_bret__1
cores_94/backward/currentState_reg[3]_bret__2
cores_94/backward/currentState_reg[3]_bret__3
cores_94/backward/currentState_reg[4]_bret
cores_94/backward/currentState_reg[4]_bret__1
cores_94/backward/currentState_reg[4]_bret__2
cores_94/backward/currentState_reg[4]_bret__3
cores_94/backward/currentState_reg[5]_bret
cores_94/backward/currentState_reg[5]_bret__0_bret
cores_94/backward/currentState_reg[5]_bret__0_bret__0
cores_94/backward/currentState_reg[5]_bret__0_bret__1
cores_94/backward/currentState_reg[5]_bret__0_bret__2
cores_94/backward/currentState_reg[5]_bret__0_bret__3
cores_94/backward/currentState_reg[5]_bret__0_bret__4
cores_94/backward/currentState_reg[5]_bret__1
cores_94/backward/currentState_reg[5]_bret__2
cores_94/backward/currentState_reg[5]_bret__3
cores_95/backward/currentState_reg[0]_bret__0
cores_95/backward/currentState_reg[0]_bret__1
cores_95/backward/currentState_reg[0]_bret__2
cores_95/backward/currentState_reg[0]_bret__3
cores_95/backward/currentState_reg[0]_bret__4
cores_95/backward/currentState_reg[0]_bret_bret
cores_95/backward/currentState_reg[0]_bret_bret__0
cores_95/backward/currentState_reg[0]_bret_bret__1
cores_95/backward/currentState_reg[0]_bret_bret__2
cores_95/backward/currentState_reg[0]_bret_bret__3
cores_95/backward/currentState_reg[0]_bret_bret__4
cores_95/backward/currentState_reg[1]_bret
cores_95/backward/currentState_reg[1]_bret__1
cores_95/backward/currentState_reg[1]_bret__2
cores_95/backward/currentState_reg[1]_bret__3
cores_95/backward/currentState_reg[2]_bret
cores_95/backward/currentState_reg[2]_bret__1
cores_95/backward/currentState_reg[2]_bret__2
cores_95/backward/currentState_reg[2]_bret__3
cores_95/backward/currentState_reg[3]_bret
cores_95/backward/currentState_reg[3]_bret__1
cores_95/backward/currentState_reg[3]_bret__2
cores_95/backward/currentState_reg[3]_bret__3
cores_95/backward/currentState_reg[4]_bret
cores_95/backward/currentState_reg[4]_bret__1
cores_95/backward/currentState_reg[4]_bret__2
cores_95/backward/currentState_reg[4]_bret__3
cores_95/backward/currentState_reg[5]_bret
cores_95/backward/currentState_reg[5]_bret__0_bret
cores_95/backward/currentState_reg[5]_bret__0_bret__0
cores_95/backward/currentState_reg[5]_bret__0_bret__1
cores_95/backward/currentState_reg[5]_bret__0_bret__2
cores_95/backward/currentState_reg[5]_bret__0_bret__3
cores_95/backward/currentState_reg[5]_bret__0_bret__4
cores_95/backward/currentState_reg[5]_bret__1
cores_95/backward/currentState_reg[5]_bret__2
cores_95/backward/currentState_reg[5]_bret__3
cores_96/backward/currentState_reg[0]_bret__0
cores_96/backward/currentState_reg[0]_bret__1
cores_96/backward/currentState_reg[0]_bret__2
cores_96/backward/currentState_reg[0]_bret__3
cores_96/backward/currentState_reg[0]_bret__4
cores_96/backward/currentState_reg[0]_bret_bret
cores_96/backward/currentState_reg[0]_bret_bret__0
cores_96/backward/currentState_reg[0]_bret_bret__1
cores_96/backward/currentState_reg[0]_bret_bret__2
cores_96/backward/currentState_reg[0]_bret_bret__3
cores_96/backward/currentState_reg[0]_bret_bret__4
cores_96/backward/currentState_reg[1]_bret
cores_96/backward/currentState_reg[1]_bret__1
cores_96/backward/currentState_reg[1]_bret__2
cores_96/backward/currentState_reg[1]_bret__3
cores_96/backward/currentState_reg[2]_bret
cores_96/backward/currentState_reg[2]_bret__1
cores_96/backward/currentState_reg[2]_bret__2
cores_96/backward/currentState_reg[2]_bret__3
cores_96/backward/currentState_reg[3]_bret
cores_96/backward/currentState_reg[3]_bret__1
cores_96/backward/currentState_reg[3]_bret__2
cores_96/backward/currentState_reg[3]_bret__3
cores_96/backward/currentState_reg[4]_bret
cores_96/backward/currentState_reg[4]_bret__1
cores_96/backward/currentState_reg[4]_bret__2
cores_96/backward/currentState_reg[4]_bret__3
cores_96/backward/currentState_reg[5]_bret
cores_96/backward/currentState_reg[5]_bret__0_bret
cores_96/backward/currentState_reg[5]_bret__0_bret__0
cores_96/backward/currentState_reg[5]_bret__0_bret__1
cores_96/backward/currentState_reg[5]_bret__0_bret__2
cores_96/backward/currentState_reg[5]_bret__0_bret__3
cores_96/backward/currentState_reg[5]_bret__0_bret__4
cores_96/backward/currentState_reg[5]_bret__1
cores_96/backward/currentState_reg[5]_bret__2
cores_96/backward/currentState_reg[5]_bret__3
cores_97/backward/currentState_reg[0]_bret__0
cores_97/backward/currentState_reg[0]_bret__1
cores_97/backward/currentState_reg[0]_bret__2
cores_97/backward/currentState_reg[0]_bret__3
cores_97/backward/currentState_reg[0]_bret__4
cores_97/backward/currentState_reg[0]_bret_bret
cores_97/backward/currentState_reg[0]_bret_bret__0
cores_97/backward/currentState_reg[0]_bret_bret__1
cores_97/backward/currentState_reg[0]_bret_bret__2
cores_97/backward/currentState_reg[0]_bret_bret__3
cores_97/backward/currentState_reg[0]_bret_bret__4
cores_97/backward/currentState_reg[1]_bret
cores_97/backward/currentState_reg[1]_bret__1
cores_97/backward/currentState_reg[1]_bret__2
cores_97/backward/currentState_reg[1]_bret__3
cores_97/backward/currentState_reg[2]_bret
cores_97/backward/currentState_reg[2]_bret__1
cores_97/backward/currentState_reg[2]_bret__2
cores_97/backward/currentState_reg[2]_bret__3
cores_97/backward/currentState_reg[3]_bret
cores_97/backward/currentState_reg[3]_bret__1
cores_97/backward/currentState_reg[3]_bret__2
cores_97/backward/currentState_reg[3]_bret__3
cores_97/backward/currentState_reg[4]_bret
cores_97/backward/currentState_reg[4]_bret__1
cores_97/backward/currentState_reg[4]_bret__2
cores_97/backward/currentState_reg[4]_bret__3
cores_97/backward/currentState_reg[5]_bret
cores_97/backward/currentState_reg[5]_bret__0_bret
cores_97/backward/currentState_reg[5]_bret__0_bret__0
cores_97/backward/currentState_reg[5]_bret__0_bret__1
cores_97/backward/currentState_reg[5]_bret__0_bret__2
cores_97/backward/currentState_reg[5]_bret__0_bret__3
cores_97/backward/currentState_reg[5]_bret__0_bret__4
cores_97/backward/currentState_reg[5]_bret__1
cores_97/backward/currentState_reg[5]_bret__2
cores_97/backward/currentState_reg[5]_bret__3
cores_98/backward/currentState_reg[0]_bret__0
cores_98/backward/currentState_reg[0]_bret__1
cores_98/backward/currentState_reg[0]_bret__2
cores_98/backward/currentState_reg[0]_bret__3
cores_98/backward/currentState_reg[0]_bret__4
cores_98/backward/currentState_reg[0]_bret_bret
cores_98/backward/currentState_reg[0]_bret_bret__0
cores_98/backward/currentState_reg[0]_bret_bret__1
cores_98/backward/currentState_reg[0]_bret_bret__2
cores_98/backward/currentState_reg[0]_bret_bret__3
cores_98/backward/currentState_reg[0]_bret_bret__4
cores_98/backward/currentState_reg[1]_bret
cores_98/backward/currentState_reg[1]_bret__1
cores_98/backward/currentState_reg[1]_bret__2
cores_98/backward/currentState_reg[1]_bret__3
cores_98/backward/currentState_reg[2]_bret
cores_98/backward/currentState_reg[2]_bret__1
cores_98/backward/currentState_reg[2]_bret__2
cores_98/backward/currentState_reg[2]_bret__3
cores_98/backward/currentState_reg[3]_bret
cores_98/backward/currentState_reg[3]_bret__1
cores_98/backward/currentState_reg[3]_bret__2
cores_98/backward/currentState_reg[3]_bret__3
cores_98/backward/currentState_reg[4]_bret
cores_98/backward/currentState_reg[4]_bret__1
cores_98/backward/currentState_reg[4]_bret__2
cores_98/backward/currentState_reg[4]_bret__3
cores_98/backward/currentState_reg[5]_bret
cores_98/backward/currentState_reg[5]_bret__0_bret
cores_98/backward/currentState_reg[5]_bret__0_bret__0
cores_98/backward/currentState_reg[5]_bret__0_bret__1
cores_98/backward/currentState_reg[5]_bret__0_bret__2
cores_98/backward/currentState_reg[5]_bret__0_bret__3
cores_98/backward/currentState_reg[5]_bret__0_bret__4
cores_98/backward/currentState_reg[5]_bret__1
cores_98/backward/currentState_reg[5]_bret__2
cores_98/backward/currentState_reg[5]_bret__3
cores_99/backward/currentState_reg[0]_bret__0
cores_99/backward/currentState_reg[0]_bret__1
cores_99/backward/currentState_reg[0]_bret__2
cores_99/backward/currentState_reg[0]_bret__3
cores_99/backward/currentState_reg[0]_bret__4
cores_99/backward/currentState_reg[0]_bret_bret
cores_99/backward/currentState_reg[0]_bret_bret__0
cores_99/backward/currentState_reg[0]_bret_bret__1
cores_99/backward/currentState_reg[0]_bret_bret__2
cores_99/backward/currentState_reg[0]_bret_bret__3
cores_99/backward/currentState_reg[0]_bret_bret__4
cores_99/backward/currentState_reg[1]_bret
cores_99/backward/currentState_reg[1]_bret__1
cores_99/backward/currentState_reg[1]_bret__2
cores_99/backward/currentState_reg[1]_bret__3
cores_99/backward/currentState_reg[2]_bret
cores_99/backward/currentState_reg[2]_bret__1
cores_99/backward/currentState_reg[2]_bret__2
cores_99/backward/currentState_reg[2]_bret__3
cores_99/backward/currentState_reg[3]_bret
cores_99/backward/currentState_reg[3]_bret__1
cores_99/backward/currentState_reg[3]_bret__2
cores_99/backward/currentState_reg[3]_bret__3
cores_99/backward/currentState_reg[4]_bret
cores_99/backward/currentState_reg[4]_bret__1
cores_99/backward/currentState_reg[4]_bret__2
cores_99/backward/currentState_reg[4]_bret__3
cores_99/backward/currentState_reg[5]_bret
cores_99/backward/currentState_reg[5]_bret__0_bret
cores_99/backward/currentState_reg[5]_bret__0_bret__0
cores_99/backward/currentState_reg[5]_bret__0_bret__1
cores_99/backward/currentState_reg[5]_bret__0_bret__2
cores_99/backward/currentState_reg[5]_bret__0_bret__3
cores_99/backward/currentState_reg[5]_bret__0_bret__4
cores_99/backward/currentState_reg[5]_bret__1
cores_99/backward/currentState_reg[5]_bret__2
cores_99/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB14_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB15_tempName`
Numbers of forward move = 0, and backward move = 64
Retimed registers names:
cores_86/backward/currentState_reg[0]_bret__0
cores_86/backward/currentState_reg[0]_bret__1
cores_86/backward/currentState_reg[0]_bret__2
cores_86/backward/currentState_reg[0]_bret__3
cores_86/backward/currentState_reg[0]_bret__4
cores_86/backward/currentState_reg[0]_bret_bret
cores_86/backward/currentState_reg[0]_bret_bret__0
cores_86/backward/currentState_reg[0]_bret_bret__1
cores_86/backward/currentState_reg[0]_bret_bret__2
cores_86/backward/currentState_reg[0]_bret_bret__3
cores_86/backward/currentState_reg[0]_bret_bret__4
cores_86/backward/currentState_reg[1]_bret
cores_86/backward/currentState_reg[1]_bret__1
cores_86/backward/currentState_reg[1]_bret__2
cores_86/backward/currentState_reg[1]_bret__3
cores_86/backward/currentState_reg[2]_bret
cores_86/backward/currentState_reg[2]_bret__1
cores_86/backward/currentState_reg[2]_bret__2
cores_86/backward/currentState_reg[2]_bret__3
cores_86/backward/currentState_reg[3]_bret
cores_86/backward/currentState_reg[3]_bret__1
cores_86/backward/currentState_reg[3]_bret__2
cores_86/backward/currentState_reg[3]_bret__3
cores_86/backward/currentState_reg[4]_bret
cores_86/backward/currentState_reg[4]_bret__1
cores_86/backward/currentState_reg[4]_bret__2
cores_86/backward/currentState_reg[4]_bret__3
cores_86/backward/currentState_reg[5]_bret
cores_86/backward/currentState_reg[5]_bret__0_bret
cores_86/backward/currentState_reg[5]_bret__0_bret__0
cores_86/backward/currentState_reg[5]_bret__0_bret__1
cores_86/backward/currentState_reg[5]_bret__0_bret__2
cores_86/backward/currentState_reg[5]_bret__0_bret__3
cores_86/backward/currentState_reg[5]_bret__0_bret__4
cores_86/backward/currentState_reg[5]_bret__1
cores_86/backward/currentState_reg[5]_bret__2
cores_86/backward/currentState_reg[5]_bret__3
cores_87/backward/currentState_reg[0]_bret__0
cores_87/backward/currentState_reg[0]_bret__1
cores_87/backward/currentState_reg[0]_bret__2
cores_87/backward/currentState_reg[0]_bret__3
cores_87/backward/currentState_reg[0]_bret__4
cores_87/backward/currentState_reg[0]_bret_bret
cores_87/backward/currentState_reg[0]_bret_bret__0
cores_87/backward/currentState_reg[0]_bret_bret__1
cores_87/backward/currentState_reg[0]_bret_bret__2
cores_87/backward/currentState_reg[0]_bret_bret__3
cores_87/backward/currentState_reg[0]_bret_bret__4
cores_87/backward/currentState_reg[1]_bret
cores_87/backward/currentState_reg[1]_bret__1
cores_87/backward/currentState_reg[1]_bret__2
cores_87/backward/currentState_reg[1]_bret__3
cores_87/backward/currentState_reg[2]_bret
cores_87/backward/currentState_reg[2]_bret__1
cores_87/backward/currentState_reg[2]_bret__2
cores_87/backward/currentState_reg[2]_bret__3
cores_87/backward/currentState_reg[3]_bret
cores_87/backward/currentState_reg[3]_bret__1
cores_87/backward/currentState_reg[3]_bret__2
cores_87/backward/currentState_reg[3]_bret__3
cores_87/backward/currentState_reg[4]_bret
cores_87/backward/currentState_reg[4]_bret__1
cores_87/backward/currentState_reg[4]_bret__2
cores_87/backward/currentState_reg[4]_bret__3
cores_87/backward/currentState_reg[5]_bret
cores_87/backward/currentState_reg[5]_bret__0_bret
cores_87/backward/currentState_reg[5]_bret__0_bret__0
cores_87/backward/currentState_reg[5]_bret__0_bret__1
cores_87/backward/currentState_reg[5]_bret__0_bret__2
cores_87/backward/currentState_reg[5]_bret__0_bret__3
cores_87/backward/currentState_reg[5]_bret__0_bret__4
cores_87/backward/currentState_reg[5]_bret__1
cores_87/backward/currentState_reg[5]_bret__2
cores_87/backward/currentState_reg[5]_bret__3
cores_88/backward/currentState_reg[0]_bret__0
cores_88/backward/currentState_reg[0]_bret__1
cores_88/backward/currentState_reg[0]_bret__2
cores_88/backward/currentState_reg[0]_bret__3
cores_88/backward/currentState_reg[0]_bret__4
cores_88/backward/currentState_reg[0]_bret_bret
cores_88/backward/currentState_reg[0]_bret_bret__0
cores_88/backward/currentState_reg[0]_bret_bret__1
cores_88/backward/currentState_reg[0]_bret_bret__2
cores_88/backward/currentState_reg[0]_bret_bret__3
cores_88/backward/currentState_reg[0]_bret_bret__4
cores_88/backward/currentState_reg[1]_bret
cores_88/backward/currentState_reg[1]_bret__1
cores_88/backward/currentState_reg[1]_bret__2
cores_88/backward/currentState_reg[1]_bret__3
cores_88/backward/currentState_reg[2]_bret
cores_88/backward/currentState_reg[2]_bret__1
cores_88/backward/currentState_reg[2]_bret__2
cores_88/backward/currentState_reg[2]_bret__3
cores_88/backward/currentState_reg[3]_bret
cores_88/backward/currentState_reg[3]_bret__1
cores_88/backward/currentState_reg[3]_bret__2
cores_88/backward/currentState_reg[3]_bret__3
cores_88/backward/currentState_reg[4]_bret
cores_88/backward/currentState_reg[4]_bret__1
cores_88/backward/currentState_reg[4]_bret__2
cores_88/backward/currentState_reg[4]_bret__3
cores_88/backward/currentState_reg[5]_bret
cores_88/backward/currentState_reg[5]_bret__0_bret
cores_88/backward/currentState_reg[5]_bret__0_bret__0
cores_88/backward/currentState_reg[5]_bret__0_bret__1
cores_88/backward/currentState_reg[5]_bret__0_bret__2
cores_88/backward/currentState_reg[5]_bret__0_bret__3
cores_88/backward/currentState_reg[5]_bret__0_bret__4
cores_88/backward/currentState_reg[5]_bret__1
cores_88/backward/currentState_reg[5]_bret__2
cores_88/backward/currentState_reg[5]_bret__3
cores_89/backward/currentState_reg[0]_bret__0
cores_89/backward/currentState_reg[0]_bret__1
cores_89/backward/currentState_reg[0]_bret__2
cores_89/backward/currentState_reg[0]_bret__3
cores_89/backward/currentState_reg[0]_bret__4
cores_89/backward/currentState_reg[0]_bret_bret
cores_89/backward/currentState_reg[0]_bret_bret__0
cores_89/backward/currentState_reg[0]_bret_bret__1
cores_89/backward/currentState_reg[0]_bret_bret__2
cores_89/backward/currentState_reg[0]_bret_bret__3
cores_89/backward/currentState_reg[0]_bret_bret__4
cores_89/backward/currentState_reg[1]_bret
cores_89/backward/currentState_reg[1]_bret__1
cores_89/backward/currentState_reg[1]_bret__2
cores_89/backward/currentState_reg[1]_bret__3
cores_89/backward/currentState_reg[2]_bret
cores_89/backward/currentState_reg[2]_bret__1
cores_89/backward/currentState_reg[2]_bret__2
cores_89/backward/currentState_reg[2]_bret__3
cores_89/backward/currentState_reg[3]_bret
cores_89/backward/currentState_reg[3]_bret__1
cores_89/backward/currentState_reg[3]_bret__2
cores_89/backward/currentState_reg[3]_bret__3
cores_89/backward/currentState_reg[4]_bret
cores_89/backward/currentState_reg[4]_bret__1
cores_89/backward/currentState_reg[4]_bret__2
cores_89/backward/currentState_reg[4]_bret__3
cores_89/backward/currentState_reg[5]_bret
cores_89/backward/currentState_reg[5]_bret__0_bret
cores_89/backward/currentState_reg[5]_bret__0_bret__0
cores_89/backward/currentState_reg[5]_bret__0_bret__1
cores_89/backward/currentState_reg[5]_bret__0_bret__2
cores_89/backward/currentState_reg[5]_bret__0_bret__3
cores_89/backward/currentState_reg[5]_bret__0_bret__4
cores_89/backward/currentState_reg[5]_bret__1
cores_89/backward/currentState_reg[5]_bret__2
cores_89/backward/currentState_reg[5]_bret__3
cores_90/backward/currentState_reg[0]_bret__0
cores_90/backward/currentState_reg[0]_bret__1
cores_90/backward/currentState_reg[0]_bret__2
cores_90/backward/currentState_reg[0]_bret__3
cores_90/backward/currentState_reg[0]_bret__4
cores_90/backward/currentState_reg[0]_bret_bret
cores_90/backward/currentState_reg[0]_bret_bret__0
cores_90/backward/currentState_reg[0]_bret_bret__1
cores_90/backward/currentState_reg[0]_bret_bret__2
cores_90/backward/currentState_reg[0]_bret_bret__3
cores_90/backward/currentState_reg[0]_bret_bret__4
cores_90/backward/currentState_reg[1]_bret
cores_90/backward/currentState_reg[1]_bret__1
cores_90/backward/currentState_reg[1]_bret__2
cores_90/backward/currentState_reg[1]_bret__3
cores_90/backward/currentState_reg[2]_bret
cores_90/backward/currentState_reg[2]_bret__1
cores_90/backward/currentState_reg[2]_bret__2
cores_90/backward/currentState_reg[2]_bret__3
cores_90/backward/currentState_reg[3]_bret
cores_90/backward/currentState_reg[3]_bret__1
cores_90/backward/currentState_reg[3]_bret__2
cores_90/backward/currentState_reg[3]_bret__3
cores_90/backward/currentState_reg[4]_bret
cores_90/backward/currentState_reg[4]_bret__1
cores_90/backward/currentState_reg[4]_bret__2
cores_90/backward/currentState_reg[4]_bret__3
cores_90/backward/currentState_reg[5]_bret
cores_90/backward/currentState_reg[5]_bret__0_bret
cores_90/backward/currentState_reg[5]_bret__0_bret__0
cores_90/backward/currentState_reg[5]_bret__0_bret__1
cores_90/backward/currentState_reg[5]_bret__0_bret__2
cores_90/backward/currentState_reg[5]_bret__0_bret__3
cores_90/backward/currentState_reg[5]_bret__0_bret__4
cores_90/backward/currentState_reg[5]_bret__1
cores_90/backward/currentState_reg[5]_bret__2
cores_90/backward/currentState_reg[5]_bret__3
cores_91/backward/currentState_reg[0]_bret__0
cores_91/backward/currentState_reg[0]_bret__1
cores_91/backward/currentState_reg[0]_bret__2
cores_91/backward/currentState_reg[0]_bret__3
cores_91/backward/currentState_reg[0]_bret__4
cores_91/backward/currentState_reg[0]_bret_bret
cores_91/backward/currentState_reg[0]_bret_bret__0
cores_91/backward/currentState_reg[0]_bret_bret__1
cores_91/backward/currentState_reg[0]_bret_bret__2
cores_91/backward/currentState_reg[0]_bret_bret__3
cores_91/backward/currentState_reg[0]_bret_bret__4
cores_91/backward/currentState_reg[1]_bret
cores_91/backward/currentState_reg[1]_bret__1
cores_91/backward/currentState_reg[1]_bret__2
cores_91/backward/currentState_reg[1]_bret__3
cores_91/backward/currentState_reg[2]_bret
cores_91/backward/currentState_reg[2]_bret__1
cores_91/backward/currentState_reg[2]_bret__2
cores_91/backward/currentState_reg[2]_bret__3
cores_91/backward/currentState_reg[3]_bret
cores_91/backward/currentState_reg[3]_bret__1
cores_91/backward/currentState_reg[3]_bret__2
cores_91/backward/currentState_reg[3]_bret__3
cores_91/backward/currentState_reg[4]_bret
cores_91/backward/currentState_reg[4]_bret__1
cores_91/backward/currentState_reg[4]_bret__2
cores_91/backward/currentState_reg[4]_bret__3
cores_91/backward/currentState_reg[5]_bret
cores_91/backward/currentState_reg[5]_bret__0_bret
cores_91/backward/currentState_reg[5]_bret__0_bret__0
cores_91/backward/currentState_reg[5]_bret__0_bret__1
cores_91/backward/currentState_reg[5]_bret__0_bret__2
cores_91/backward/currentState_reg[5]_bret__0_bret__3
cores_91/backward/currentState_reg[5]_bret__0_bret__4
cores_91/backward/currentState_reg[5]_bret__1
cores_91/backward/currentState_reg[5]_bret__2
cores_91/backward/currentState_reg[5]_bret__3
cores_92/backward/currentState_reg[0]_bret__0
cores_92/backward/currentState_reg[0]_bret__1
cores_92/backward/currentState_reg[0]_bret__2
cores_92/backward/currentState_reg[0]_bret__3
cores_92/backward/currentState_reg[0]_bret__4
cores_92/backward/currentState_reg[0]_bret_bret
cores_92/backward/currentState_reg[0]_bret_bret__0
cores_92/backward/currentState_reg[0]_bret_bret__1
cores_92/backward/currentState_reg[0]_bret_bret__2
cores_92/backward/currentState_reg[0]_bret_bret__3
cores_92/backward/currentState_reg[0]_bret_bret__4
cores_92/backward/currentState_reg[1]_bret
cores_92/backward/currentState_reg[1]_bret__1
cores_92/backward/currentState_reg[1]_bret__2
cores_92/backward/currentState_reg[1]_bret__3
cores_92/backward/currentState_reg[2]_bret
cores_92/backward/currentState_reg[2]_bret__1
cores_92/backward/currentState_reg[2]_bret__2
cores_92/backward/currentState_reg[2]_bret__3
cores_92/backward/currentState_reg[3]_bret
cores_92/backward/currentState_reg[3]_bret__1
cores_92/backward/currentState_reg[3]_bret__2
cores_92/backward/currentState_reg[3]_bret__3
cores_92/backward/currentState_reg[4]_bret
cores_92/backward/currentState_reg[4]_bret__1
cores_92/backward/currentState_reg[4]_bret__2
cores_92/backward/currentState_reg[4]_bret__3
cores_92/backward/currentState_reg[5]_bret
cores_92/backward/currentState_reg[5]_bret__0_bret
cores_92/backward/currentState_reg[5]_bret__0_bret__0
cores_92/backward/currentState_reg[5]_bret__0_bret__1
cores_92/backward/currentState_reg[5]_bret__0_bret__2
cores_92/backward/currentState_reg[5]_bret__0_bret__3
cores_92/backward/currentState_reg[5]_bret__0_bret__4
cores_92/backward/currentState_reg[5]_bret__1
cores_92/backward/currentState_reg[5]_bret__2
cores_92/backward/currentState_reg[5]_bret__3
cores_93/backward/currentState_reg[0]_bret__0
cores_93/backward/currentState_reg[0]_bret__1
cores_93/backward/currentState_reg[0]_bret__2
cores_93/backward/currentState_reg[0]_bret__3
cores_93/backward/currentState_reg[0]_bret__4
cores_93/backward/currentState_reg[0]_bret_bret
cores_93/backward/currentState_reg[0]_bret_bret__0
cores_93/backward/currentState_reg[0]_bret_bret__1
cores_93/backward/currentState_reg[0]_bret_bret__2
cores_93/backward/currentState_reg[0]_bret_bret__3
cores_93/backward/currentState_reg[0]_bret_bret__4
cores_93/backward/currentState_reg[1]_bret
cores_93/backward/currentState_reg[1]_bret__1
cores_93/backward/currentState_reg[1]_bret__2
cores_93/backward/currentState_reg[1]_bret__3
cores_93/backward/currentState_reg[2]_bret
cores_93/backward/currentState_reg[2]_bret__1
cores_93/backward/currentState_reg[2]_bret__2
cores_93/backward/currentState_reg[2]_bret__3
cores_93/backward/currentState_reg[3]_bret
cores_93/backward/currentState_reg[3]_bret__1
cores_93/backward/currentState_reg[3]_bret__2
cores_93/backward/currentState_reg[3]_bret__3
cores_93/backward/currentState_reg[4]_bret
cores_93/backward/currentState_reg[4]_bret__1
cores_93/backward/currentState_reg[4]_bret__2
cores_93/backward/currentState_reg[4]_bret__3
cores_93/backward/currentState_reg[5]_bret
cores_93/backward/currentState_reg[5]_bret__0_bret
cores_93/backward/currentState_reg[5]_bret__0_bret__0
cores_93/backward/currentState_reg[5]_bret__0_bret__1
cores_93/backward/currentState_reg[5]_bret__0_bret__2
cores_93/backward/currentState_reg[5]_bret__0_bret__3
cores_93/backward/currentState_reg[5]_bret__0_bret__4
cores_93/backward/currentState_reg[5]_bret__1
cores_93/backward/currentState_reg[5]_bret__2
cores_93/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB15_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB16_tempName`
Numbers of forward move = 0, and backward move = 80
Retimed registers names:
cores_104/backward/currentState_reg[0]_bret__0
cores_104/backward/currentState_reg[0]_bret__1
cores_104/backward/currentState_reg[0]_bret__2
cores_104/backward/currentState_reg[0]_bret__3
cores_104/backward/currentState_reg[0]_bret__4
cores_104/backward/currentState_reg[0]_bret_bret
cores_104/backward/currentState_reg[0]_bret_bret__0
cores_104/backward/currentState_reg[0]_bret_bret__1
cores_104/backward/currentState_reg[0]_bret_bret__2
cores_104/backward/currentState_reg[0]_bret_bret__3
cores_104/backward/currentState_reg[0]_bret_bret__4
cores_104/backward/currentState_reg[1]_bret
cores_104/backward/currentState_reg[1]_bret__1
cores_104/backward/currentState_reg[1]_bret__2
cores_104/backward/currentState_reg[1]_bret__3
cores_104/backward/currentState_reg[2]_bret
cores_104/backward/currentState_reg[2]_bret__1
cores_104/backward/currentState_reg[2]_bret__2
cores_104/backward/currentState_reg[2]_bret__3
cores_104/backward/currentState_reg[3]_bret
cores_104/backward/currentState_reg[3]_bret__1
cores_104/backward/currentState_reg[3]_bret__2
cores_104/backward/currentState_reg[3]_bret__3
cores_104/backward/currentState_reg[4]_bret
cores_104/backward/currentState_reg[4]_bret__1
cores_104/backward/currentState_reg[4]_bret__2
cores_104/backward/currentState_reg[4]_bret__3
cores_104/backward/currentState_reg[5]_bret
cores_104/backward/currentState_reg[5]_bret__0_bret
cores_104/backward/currentState_reg[5]_bret__0_bret__0
cores_104/backward/currentState_reg[5]_bret__0_bret__1
cores_104/backward/currentState_reg[5]_bret__0_bret__2
cores_104/backward/currentState_reg[5]_bret__0_bret__3
cores_104/backward/currentState_reg[5]_bret__0_bret__4
cores_104/backward/currentState_reg[5]_bret__1
cores_104/backward/currentState_reg[5]_bret__2
cores_104/backward/currentState_reg[5]_bret__3
cores_77/backward/currentState_reg[0]_bret__0
cores_77/backward/currentState_reg[0]_bret__1
cores_77/backward/currentState_reg[0]_bret__2
cores_77/backward/currentState_reg[0]_bret__3
cores_77/backward/currentState_reg[0]_bret__4
cores_77/backward/currentState_reg[0]_bret_bret
cores_77/backward/currentState_reg[0]_bret_bret__0
cores_77/backward/currentState_reg[0]_bret_bret__1
cores_77/backward/currentState_reg[0]_bret_bret__2
cores_77/backward/currentState_reg[0]_bret_bret__3
cores_77/backward/currentState_reg[0]_bret_bret__4
cores_77/backward/currentState_reg[1]_bret
cores_77/backward/currentState_reg[1]_bret__1
cores_77/backward/currentState_reg[1]_bret__2
cores_77/backward/currentState_reg[1]_bret__3
cores_77/backward/currentState_reg[2]_bret
cores_77/backward/currentState_reg[2]_bret__1
cores_77/backward/currentState_reg[2]_bret__2
cores_77/backward/currentState_reg[2]_bret__3
cores_77/backward/currentState_reg[3]_bret
cores_77/backward/currentState_reg[3]_bret__1
cores_77/backward/currentState_reg[3]_bret__2
cores_77/backward/currentState_reg[3]_bret__3
cores_77/backward/currentState_reg[4]_bret
cores_77/backward/currentState_reg[4]_bret__1
cores_77/backward/currentState_reg[4]_bret__2
cores_77/backward/currentState_reg[4]_bret__3
cores_77/backward/currentState_reg[5]_bret
cores_77/backward/currentState_reg[5]_bret__0_bret
cores_77/backward/currentState_reg[5]_bret__0_bret__0
cores_77/backward/currentState_reg[5]_bret__0_bret__1
cores_77/backward/currentState_reg[5]_bret__0_bret__2
cores_77/backward/currentState_reg[5]_bret__0_bret__3
cores_77/backward/currentState_reg[5]_bret__0_bret__4
cores_77/backward/currentState_reg[5]_bret__1
cores_77/backward/currentState_reg[5]_bret__2
cores_77/backward/currentState_reg[5]_bret__3
cores_78/backward/currentState_reg[0]_bret__0
cores_78/backward/currentState_reg[0]_bret__1
cores_78/backward/currentState_reg[0]_bret__2
cores_78/backward/currentState_reg[0]_bret__3
cores_78/backward/currentState_reg[0]_bret__4
cores_78/backward/currentState_reg[0]_bret_bret
cores_78/backward/currentState_reg[0]_bret_bret__0
cores_78/backward/currentState_reg[0]_bret_bret__1
cores_78/backward/currentState_reg[0]_bret_bret__2
cores_78/backward/currentState_reg[0]_bret_bret__3
cores_78/backward/currentState_reg[0]_bret_bret__4
cores_78/backward/currentState_reg[1]_bret
cores_78/backward/currentState_reg[1]_bret__1
cores_78/backward/currentState_reg[1]_bret__2
cores_78/backward/currentState_reg[1]_bret__3
cores_78/backward/currentState_reg[2]_bret
cores_78/backward/currentState_reg[2]_bret__1
cores_78/backward/currentState_reg[2]_bret__2
cores_78/backward/currentState_reg[2]_bret__3
cores_78/backward/currentState_reg[3]_bret
cores_78/backward/currentState_reg[3]_bret__1
cores_78/backward/currentState_reg[3]_bret__2
cores_78/backward/currentState_reg[3]_bret__3
cores_78/backward/currentState_reg[4]_bret
cores_78/backward/currentState_reg[4]_bret__1
cores_78/backward/currentState_reg[4]_bret__2
cores_78/backward/currentState_reg[4]_bret__3
cores_78/backward/currentState_reg[5]_bret
cores_78/backward/currentState_reg[5]_bret__0_bret
cores_78/backward/currentState_reg[5]_bret__0_bret__0
cores_78/backward/currentState_reg[5]_bret__0_bret__1
cores_78/backward/currentState_reg[5]_bret__0_bret__2
cores_78/backward/currentState_reg[5]_bret__0_bret__3
cores_78/backward/currentState_reg[5]_bret__0_bret__4
cores_78/backward/currentState_reg[5]_bret__1
cores_78/backward/currentState_reg[5]_bret__2
cores_78/backward/currentState_reg[5]_bret__3
cores_79/backward/currentState_reg[0]_bret__0
cores_79/backward/currentState_reg[0]_bret__1
cores_79/backward/currentState_reg[0]_bret__2
cores_79/backward/currentState_reg[0]_bret__3
cores_79/backward/currentState_reg[0]_bret__4
cores_79/backward/currentState_reg[0]_bret_bret
cores_79/backward/currentState_reg[0]_bret_bret__0
cores_79/backward/currentState_reg[0]_bret_bret__1
cores_79/backward/currentState_reg[0]_bret_bret__2
cores_79/backward/currentState_reg[0]_bret_bret__3
cores_79/backward/currentState_reg[0]_bret_bret__4
cores_79/backward/currentState_reg[1]_bret
cores_79/backward/currentState_reg[1]_bret__1
cores_79/backward/currentState_reg[1]_bret__2
cores_79/backward/currentState_reg[1]_bret__3
cores_79/backward/currentState_reg[2]_bret
cores_79/backward/currentState_reg[2]_bret__1
cores_79/backward/currentState_reg[2]_bret__2
cores_79/backward/currentState_reg[2]_bret__3
cores_79/backward/currentState_reg[3]_bret
cores_79/backward/currentState_reg[3]_bret__1
cores_79/backward/currentState_reg[3]_bret__2
cores_79/backward/currentState_reg[3]_bret__3
cores_79/backward/currentState_reg[4]_bret
cores_79/backward/currentState_reg[4]_bret__1
cores_79/backward/currentState_reg[4]_bret__2
cores_79/backward/currentState_reg[4]_bret__3
cores_79/backward/currentState_reg[5]_bret
cores_79/backward/currentState_reg[5]_bret__0_bret
cores_79/backward/currentState_reg[5]_bret__0_bret__0
cores_79/backward/currentState_reg[5]_bret__0_bret__1
cores_79/backward/currentState_reg[5]_bret__0_bret__2
cores_79/backward/currentState_reg[5]_bret__0_bret__3
cores_79/backward/currentState_reg[5]_bret__0_bret__4
cores_79/backward/currentState_reg[5]_bret__1
cores_79/backward/currentState_reg[5]_bret__2
cores_79/backward/currentState_reg[5]_bret__3
cores_80/backward/currentState_reg[0]_bret__0
cores_80/backward/currentState_reg[0]_bret__1
cores_80/backward/currentState_reg[0]_bret__2
cores_80/backward/currentState_reg[0]_bret__3
cores_80/backward/currentState_reg[0]_bret__4
cores_80/backward/currentState_reg[0]_bret_bret
cores_80/backward/currentState_reg[0]_bret_bret__0
cores_80/backward/currentState_reg[0]_bret_bret__1
cores_80/backward/currentState_reg[0]_bret_bret__2
cores_80/backward/currentState_reg[0]_bret_bret__3
cores_80/backward/currentState_reg[0]_bret_bret__4
cores_80/backward/currentState_reg[1]_bret
cores_80/backward/currentState_reg[1]_bret__1
cores_80/backward/currentState_reg[1]_bret__2
cores_80/backward/currentState_reg[1]_bret__3
cores_80/backward/currentState_reg[2]_bret
cores_80/backward/currentState_reg[2]_bret__1
cores_80/backward/currentState_reg[2]_bret__2
cores_80/backward/currentState_reg[2]_bret__3
cores_80/backward/currentState_reg[3]_bret
cores_80/backward/currentState_reg[3]_bret__1
cores_80/backward/currentState_reg[3]_bret__2
cores_80/backward/currentState_reg[3]_bret__3
cores_80/backward/currentState_reg[4]_bret
cores_80/backward/currentState_reg[4]_bret__1
cores_80/backward/currentState_reg[4]_bret__2
cores_80/backward/currentState_reg[4]_bret__3
cores_80/backward/currentState_reg[5]_bret
cores_80/backward/currentState_reg[5]_bret__0_bret
cores_80/backward/currentState_reg[5]_bret__0_bret__0
cores_80/backward/currentState_reg[5]_bret__0_bret__1
cores_80/backward/currentState_reg[5]_bret__0_bret__2
cores_80/backward/currentState_reg[5]_bret__0_bret__3
cores_80/backward/currentState_reg[5]_bret__0_bret__4
cores_80/backward/currentState_reg[5]_bret__1
cores_80/backward/currentState_reg[5]_bret__2
cores_80/backward/currentState_reg[5]_bret__3
cores_81/backward/currentState_reg[0]_bret__0
cores_81/backward/currentState_reg[0]_bret__1
cores_81/backward/currentState_reg[0]_bret__2
cores_81/backward/currentState_reg[0]_bret__3
cores_81/backward/currentState_reg[0]_bret__4
cores_81/backward/currentState_reg[0]_bret_bret
cores_81/backward/currentState_reg[0]_bret_bret__0
cores_81/backward/currentState_reg[0]_bret_bret__1
cores_81/backward/currentState_reg[0]_bret_bret__2
cores_81/backward/currentState_reg[0]_bret_bret__3
cores_81/backward/currentState_reg[0]_bret_bret__4
cores_81/backward/currentState_reg[1]_bret
cores_81/backward/currentState_reg[1]_bret__1
cores_81/backward/currentState_reg[1]_bret__2
cores_81/backward/currentState_reg[1]_bret__3
cores_81/backward/currentState_reg[2]_bret
cores_81/backward/currentState_reg[2]_bret__1
cores_81/backward/currentState_reg[2]_bret__2
cores_81/backward/currentState_reg[2]_bret__3
cores_81/backward/currentState_reg[3]_bret
cores_81/backward/currentState_reg[3]_bret__1
cores_81/backward/currentState_reg[3]_bret__2
cores_81/backward/currentState_reg[3]_bret__3
cores_81/backward/currentState_reg[4]_bret
cores_81/backward/currentState_reg[4]_bret__1
cores_81/backward/currentState_reg[4]_bret__2
cores_81/backward/currentState_reg[4]_bret__3
cores_81/backward/currentState_reg[5]_bret
cores_81/backward/currentState_reg[5]_bret__0_bret
cores_81/backward/currentState_reg[5]_bret__0_bret__0
cores_81/backward/currentState_reg[5]_bret__0_bret__1
cores_81/backward/currentState_reg[5]_bret__0_bret__2
cores_81/backward/currentState_reg[5]_bret__0_bret__3
cores_81/backward/currentState_reg[5]_bret__0_bret__4
cores_81/backward/currentState_reg[5]_bret__1
cores_81/backward/currentState_reg[5]_bret__2
cores_81/backward/currentState_reg[5]_bret__3
cores_82/backward/currentState_reg[0]_bret__0
cores_82/backward/currentState_reg[0]_bret__1
cores_82/backward/currentState_reg[0]_bret__2
cores_82/backward/currentState_reg[0]_bret__3
cores_82/backward/currentState_reg[0]_bret__4
cores_82/backward/currentState_reg[0]_bret_bret
cores_82/backward/currentState_reg[0]_bret_bret__0
cores_82/backward/currentState_reg[0]_bret_bret__1
cores_82/backward/currentState_reg[0]_bret_bret__2
cores_82/backward/currentState_reg[0]_bret_bret__3
cores_82/backward/currentState_reg[0]_bret_bret__4
cores_82/backward/currentState_reg[1]_bret
cores_82/backward/currentState_reg[1]_bret__1
cores_82/backward/currentState_reg[1]_bret__2
cores_82/backward/currentState_reg[1]_bret__3
cores_82/backward/currentState_reg[2]_bret
cores_82/backward/currentState_reg[2]_bret__1
cores_82/backward/currentState_reg[2]_bret__2
cores_82/backward/currentState_reg[2]_bret__3
cores_82/backward/currentState_reg[3]_bret
cores_82/backward/currentState_reg[3]_bret__1
cores_82/backward/currentState_reg[3]_bret__2
cores_82/backward/currentState_reg[3]_bret__3
cores_82/backward/currentState_reg[4]_bret
cores_82/backward/currentState_reg[4]_bret__1
cores_82/backward/currentState_reg[4]_bret__2
cores_82/backward/currentState_reg[4]_bret__3
cores_82/backward/currentState_reg[5]_bret
cores_82/backward/currentState_reg[5]_bret__0_bret
cores_82/backward/currentState_reg[5]_bret__0_bret__0
cores_82/backward/currentState_reg[5]_bret__0_bret__1
cores_82/backward/currentState_reg[5]_bret__0_bret__2
cores_82/backward/currentState_reg[5]_bret__0_bret__3
cores_82/backward/currentState_reg[5]_bret__0_bret__4
cores_82/backward/currentState_reg[5]_bret__1
cores_82/backward/currentState_reg[5]_bret__2
cores_82/backward/currentState_reg[5]_bret__3
cores_83/backward/currentState_reg[0]_bret__0
cores_83/backward/currentState_reg[0]_bret__1
cores_83/backward/currentState_reg[0]_bret__2
cores_83/backward/currentState_reg[0]_bret__3
cores_83/backward/currentState_reg[0]_bret__4
cores_83/backward/currentState_reg[0]_bret_bret
cores_83/backward/currentState_reg[0]_bret_bret__0
cores_83/backward/currentState_reg[0]_bret_bret__1
cores_83/backward/currentState_reg[0]_bret_bret__2
cores_83/backward/currentState_reg[0]_bret_bret__3
cores_83/backward/currentState_reg[0]_bret_bret__4
cores_83/backward/currentState_reg[1]_bret
cores_83/backward/currentState_reg[1]_bret__1
cores_83/backward/currentState_reg[1]_bret__2
cores_83/backward/currentState_reg[1]_bret__3
cores_83/backward/currentState_reg[2]_bret
cores_83/backward/currentState_reg[2]_bret__1
cores_83/backward/currentState_reg[2]_bret__2
cores_83/backward/currentState_reg[2]_bret__3
cores_83/backward/currentState_reg[3]_bret
cores_83/backward/currentState_reg[3]_bret__1
cores_83/backward/currentState_reg[3]_bret__2
cores_83/backward/currentState_reg[3]_bret__3
cores_83/backward/currentState_reg[4]_bret
cores_83/backward/currentState_reg[4]_bret__1
cores_83/backward/currentState_reg[4]_bret__2
cores_83/backward/currentState_reg[4]_bret__3
cores_83/backward/currentState_reg[5]_bret
cores_83/backward/currentState_reg[5]_bret__0_bret
cores_83/backward/currentState_reg[5]_bret__0_bret__0
cores_83/backward/currentState_reg[5]_bret__0_bret__1
cores_83/backward/currentState_reg[5]_bret__0_bret__2
cores_83/backward/currentState_reg[5]_bret__0_bret__3
cores_83/backward/currentState_reg[5]_bret__0_bret__4
cores_83/backward/currentState_reg[5]_bret__1
cores_83/backward/currentState_reg[5]_bret__2
cores_83/backward/currentState_reg[5]_bret__3
cores_84/backward/currentState_reg[0]_bret__0
cores_84/backward/currentState_reg[0]_bret__1
cores_84/backward/currentState_reg[0]_bret__2
cores_84/backward/currentState_reg[0]_bret__3
cores_84/backward/currentState_reg[0]_bret__4
cores_84/backward/currentState_reg[0]_bret_bret
cores_84/backward/currentState_reg[0]_bret_bret__0
cores_84/backward/currentState_reg[0]_bret_bret__1
cores_84/backward/currentState_reg[0]_bret_bret__2
cores_84/backward/currentState_reg[0]_bret_bret__3
cores_84/backward/currentState_reg[0]_bret_bret__4
cores_84/backward/currentState_reg[1]_bret
cores_84/backward/currentState_reg[1]_bret__1
cores_84/backward/currentState_reg[1]_bret__2
cores_84/backward/currentState_reg[1]_bret__3
cores_84/backward/currentState_reg[2]_bret
cores_84/backward/currentState_reg[2]_bret__1
cores_84/backward/currentState_reg[2]_bret__2
cores_84/backward/currentState_reg[2]_bret__3
cores_84/backward/currentState_reg[3]_bret
cores_84/backward/currentState_reg[3]_bret__1
cores_84/backward/currentState_reg[3]_bret__2
cores_84/backward/currentState_reg[3]_bret__3
cores_84/backward/currentState_reg[4]_bret
cores_84/backward/currentState_reg[4]_bret__1
cores_84/backward/currentState_reg[4]_bret__2
cores_84/backward/currentState_reg[4]_bret__3
cores_84/backward/currentState_reg[5]_bret
cores_84/backward/currentState_reg[5]_bret__0_bret
cores_84/backward/currentState_reg[5]_bret__0_bret__0
cores_84/backward/currentState_reg[5]_bret__0_bret__1
cores_84/backward/currentState_reg[5]_bret__0_bret__2
cores_84/backward/currentState_reg[5]_bret__0_bret__3
cores_84/backward/currentState_reg[5]_bret__0_bret__4
cores_84/backward/currentState_reg[5]_bret__1
cores_84/backward/currentState_reg[5]_bret__2
cores_84/backward/currentState_reg[5]_bret__3
cores_85/backward/currentState_reg[0]_bret__0
cores_85/backward/currentState_reg[0]_bret__1
cores_85/backward/currentState_reg[0]_bret__2
cores_85/backward/currentState_reg[0]_bret__3
cores_85/backward/currentState_reg[0]_bret__4
cores_85/backward/currentState_reg[0]_bret_bret
cores_85/backward/currentState_reg[0]_bret_bret__0
cores_85/backward/currentState_reg[0]_bret_bret__1
cores_85/backward/currentState_reg[0]_bret_bret__2
cores_85/backward/currentState_reg[0]_bret_bret__3
cores_85/backward/currentState_reg[0]_bret_bret__4
cores_85/backward/currentState_reg[1]_bret
cores_85/backward/currentState_reg[1]_bret__1
cores_85/backward/currentState_reg[1]_bret__2
cores_85/backward/currentState_reg[1]_bret__3
cores_85/backward/currentState_reg[2]_bret
cores_85/backward/currentState_reg[2]_bret__1
cores_85/backward/currentState_reg[2]_bret__2
cores_85/backward/currentState_reg[2]_bret__3
cores_85/backward/currentState_reg[3]_bret
cores_85/backward/currentState_reg[3]_bret__1
cores_85/backward/currentState_reg[3]_bret__2
cores_85/backward/currentState_reg[3]_bret__3
cores_85/backward/currentState_reg[4]_bret
cores_85/backward/currentState_reg[4]_bret__1
cores_85/backward/currentState_reg[4]_bret__2
cores_85/backward/currentState_reg[4]_bret__3
cores_85/backward/currentState_reg[5]_bret
cores_85/backward/currentState_reg[5]_bret__0_bret
cores_85/backward/currentState_reg[5]_bret__0_bret__0
cores_85/backward/currentState_reg[5]_bret__0_bret__1
cores_85/backward/currentState_reg[5]_bret__0_bret__2
cores_85/backward/currentState_reg[5]_bret__0_bret__3
cores_85/backward/currentState_reg[5]_bret__0_bret__4
cores_85/backward/currentState_reg[5]_bret__1
cores_85/backward/currentState_reg[5]_bret__2
cores_85/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB16_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB17_tempName`
Numbers of forward move = 0, and backward move = 88
Retimed registers names:
cores_64/backward/currentState_reg[0]_bret__0
cores_64/backward/currentState_reg[0]_bret__1
cores_64/backward/currentState_reg[0]_bret__2
cores_64/backward/currentState_reg[0]_bret__3
cores_64/backward/currentState_reg[0]_bret__4
cores_64/backward/currentState_reg[0]_bret_bret
cores_64/backward/currentState_reg[0]_bret_bret__0
cores_64/backward/currentState_reg[0]_bret_bret__1
cores_64/backward/currentState_reg[0]_bret_bret__2
cores_64/backward/currentState_reg[0]_bret_bret__3
cores_64/backward/currentState_reg[0]_bret_bret__4
cores_64/backward/currentState_reg[1]_bret
cores_64/backward/currentState_reg[1]_bret__1
cores_64/backward/currentState_reg[1]_bret__2
cores_64/backward/currentState_reg[1]_bret__3
cores_64/backward/currentState_reg[2]_bret
cores_64/backward/currentState_reg[2]_bret__1
cores_64/backward/currentState_reg[2]_bret__2
cores_64/backward/currentState_reg[2]_bret__3
cores_64/backward/currentState_reg[3]_bret
cores_64/backward/currentState_reg[3]_bret__1
cores_64/backward/currentState_reg[3]_bret__2
cores_64/backward/currentState_reg[3]_bret__3
cores_64/backward/currentState_reg[4]_bret
cores_64/backward/currentState_reg[4]_bret__1
cores_64/backward/currentState_reg[4]_bret__2
cores_64/backward/currentState_reg[4]_bret__3
cores_64/backward/currentState_reg[5]_bret
cores_64/backward/currentState_reg[5]_bret__0_bret
cores_64/backward/currentState_reg[5]_bret__0_bret__0
cores_64/backward/currentState_reg[5]_bret__0_bret__1
cores_64/backward/currentState_reg[5]_bret__0_bret__2
cores_64/backward/currentState_reg[5]_bret__0_bret__3
cores_64/backward/currentState_reg[5]_bret__0_bret__4
cores_64/backward/currentState_reg[5]_bret__1
cores_64/backward/currentState_reg[5]_bret__2
cores_64/backward/currentState_reg[5]_bret__3
cores_66/backward/currentState_reg[0]_bret__0
cores_66/backward/currentState_reg[0]_bret__1
cores_66/backward/currentState_reg[0]_bret__2
cores_66/backward/currentState_reg[0]_bret__3
cores_66/backward/currentState_reg[0]_bret__4
cores_66/backward/currentState_reg[0]_bret_bret
cores_66/backward/currentState_reg[0]_bret_bret__0
cores_66/backward/currentState_reg[0]_bret_bret__1
cores_66/backward/currentState_reg[0]_bret_bret__2
cores_66/backward/currentState_reg[0]_bret_bret__3
cores_66/backward/currentState_reg[0]_bret_bret__4
cores_66/backward/currentState_reg[1]_bret
cores_66/backward/currentState_reg[1]_bret__1
cores_66/backward/currentState_reg[1]_bret__2
cores_66/backward/currentState_reg[1]_bret__3
cores_66/backward/currentState_reg[2]_bret
cores_66/backward/currentState_reg[2]_bret__1
cores_66/backward/currentState_reg[2]_bret__2
cores_66/backward/currentState_reg[2]_bret__3
cores_66/backward/currentState_reg[3]_bret
cores_66/backward/currentState_reg[3]_bret__1
cores_66/backward/currentState_reg[3]_bret__2
cores_66/backward/currentState_reg[3]_bret__3
cores_66/backward/currentState_reg[4]_bret
cores_66/backward/currentState_reg[4]_bret__1
cores_66/backward/currentState_reg[4]_bret__2
cores_66/backward/currentState_reg[4]_bret__3
cores_66/backward/currentState_reg[5]_bret
cores_66/backward/currentState_reg[5]_bret__0_bret
cores_66/backward/currentState_reg[5]_bret__0_bret__0
cores_66/backward/currentState_reg[5]_bret__0_bret__1
cores_66/backward/currentState_reg[5]_bret__0_bret__2
cores_66/backward/currentState_reg[5]_bret__0_bret__3
cores_66/backward/currentState_reg[5]_bret__0_bret__4
cores_66/backward/currentState_reg[5]_bret__1
cores_66/backward/currentState_reg[5]_bret__2
cores_66/backward/currentState_reg[5]_bret__3
cores_67/backward/currentState_reg[0]_bret__0
cores_67/backward/currentState_reg[0]_bret__1
cores_67/backward/currentState_reg[0]_bret__2
cores_67/backward/currentState_reg[0]_bret__3
cores_67/backward/currentState_reg[0]_bret__4
cores_67/backward/currentState_reg[0]_bret_bret
cores_67/backward/currentState_reg[0]_bret_bret__0
cores_67/backward/currentState_reg[0]_bret_bret__1
cores_67/backward/currentState_reg[0]_bret_bret__2
cores_67/backward/currentState_reg[0]_bret_bret__3
cores_67/backward/currentState_reg[0]_bret_bret__4
cores_67/backward/currentState_reg[1]_bret
cores_67/backward/currentState_reg[1]_bret__1
cores_67/backward/currentState_reg[1]_bret__2
cores_67/backward/currentState_reg[1]_bret__3
cores_67/backward/currentState_reg[2]_bret
cores_67/backward/currentState_reg[2]_bret__1
cores_67/backward/currentState_reg[2]_bret__2
cores_67/backward/currentState_reg[2]_bret__3
cores_67/backward/currentState_reg[3]_bret
cores_67/backward/currentState_reg[3]_bret__1
cores_67/backward/currentState_reg[3]_bret__2
cores_67/backward/currentState_reg[3]_bret__3
cores_67/backward/currentState_reg[4]_bret
cores_67/backward/currentState_reg[4]_bret__1
cores_67/backward/currentState_reg[4]_bret__2
cores_67/backward/currentState_reg[4]_bret__3
cores_67/backward/currentState_reg[5]_bret
cores_67/backward/currentState_reg[5]_bret__0_bret
cores_67/backward/currentState_reg[5]_bret__0_bret__0
cores_67/backward/currentState_reg[5]_bret__0_bret__1
cores_67/backward/currentState_reg[5]_bret__0_bret__2
cores_67/backward/currentState_reg[5]_bret__0_bret__3
cores_67/backward/currentState_reg[5]_bret__0_bret__4
cores_67/backward/currentState_reg[5]_bret__1
cores_67/backward/currentState_reg[5]_bret__2
cores_67/backward/currentState_reg[5]_bret__3
cores_68/backward/currentState_reg[0]_bret__0
cores_68/backward/currentState_reg[0]_bret__1
cores_68/backward/currentState_reg[0]_bret__2
cores_68/backward/currentState_reg[0]_bret__3
cores_68/backward/currentState_reg[0]_bret__4
cores_68/backward/currentState_reg[0]_bret_bret
cores_68/backward/currentState_reg[0]_bret_bret__0
cores_68/backward/currentState_reg[0]_bret_bret__1
cores_68/backward/currentState_reg[0]_bret_bret__2
cores_68/backward/currentState_reg[0]_bret_bret__3
cores_68/backward/currentState_reg[0]_bret_bret__4
cores_68/backward/currentState_reg[1]_bret
cores_68/backward/currentState_reg[1]_bret__1
cores_68/backward/currentState_reg[1]_bret__2
cores_68/backward/currentState_reg[1]_bret__3
cores_68/backward/currentState_reg[2]_bret
cores_68/backward/currentState_reg[2]_bret__1
cores_68/backward/currentState_reg[2]_bret__2
cores_68/backward/currentState_reg[2]_bret__3
cores_68/backward/currentState_reg[3]_bret
cores_68/backward/currentState_reg[3]_bret__1
cores_68/backward/currentState_reg[3]_bret__2
cores_68/backward/currentState_reg[3]_bret__3
cores_68/backward/currentState_reg[4]_bret
cores_68/backward/currentState_reg[4]_bret__1
cores_68/backward/currentState_reg[4]_bret__2
cores_68/backward/currentState_reg[4]_bret__3
cores_68/backward/currentState_reg[5]_bret
cores_68/backward/currentState_reg[5]_bret__0_bret
cores_68/backward/currentState_reg[5]_bret__0_bret__0
cores_68/backward/currentState_reg[5]_bret__0_bret__1
cores_68/backward/currentState_reg[5]_bret__0_bret__2
cores_68/backward/currentState_reg[5]_bret__0_bret__3
cores_68/backward/currentState_reg[5]_bret__0_bret__4
cores_68/backward/currentState_reg[5]_bret__1
cores_68/backward/currentState_reg[5]_bret__2
cores_68/backward/currentState_reg[5]_bret__3
cores_70/backward/currentState_reg[0]_bret__0
cores_70/backward/currentState_reg[0]_bret__1
cores_70/backward/currentState_reg[0]_bret__2
cores_70/backward/currentState_reg[0]_bret__3
cores_70/backward/currentState_reg[0]_bret__4
cores_70/backward/currentState_reg[0]_bret_bret
cores_70/backward/currentState_reg[0]_bret_bret__0
cores_70/backward/currentState_reg[0]_bret_bret__1
cores_70/backward/currentState_reg[0]_bret_bret__2
cores_70/backward/currentState_reg[0]_bret_bret__3
cores_70/backward/currentState_reg[0]_bret_bret__4
cores_70/backward/currentState_reg[1]_bret
cores_70/backward/currentState_reg[1]_bret__1
cores_70/backward/currentState_reg[1]_bret__2
cores_70/backward/currentState_reg[1]_bret__3
cores_70/backward/currentState_reg[2]_bret
cores_70/backward/currentState_reg[2]_bret__1
cores_70/backward/currentState_reg[2]_bret__2
cores_70/backward/currentState_reg[2]_bret__3
cores_70/backward/currentState_reg[3]_bret
cores_70/backward/currentState_reg[3]_bret__1
cores_70/backward/currentState_reg[3]_bret__2
cores_70/backward/currentState_reg[3]_bret__3
cores_70/backward/currentState_reg[4]_bret
cores_70/backward/currentState_reg[4]_bret__1
cores_70/backward/currentState_reg[4]_bret__2
cores_70/backward/currentState_reg[4]_bret__3
cores_70/backward/currentState_reg[5]_bret
cores_70/backward/currentState_reg[5]_bret__0_bret
cores_70/backward/currentState_reg[5]_bret__0_bret__0
cores_70/backward/currentState_reg[5]_bret__0_bret__1
cores_70/backward/currentState_reg[5]_bret__0_bret__2
cores_70/backward/currentState_reg[5]_bret__0_bret__3
cores_70/backward/currentState_reg[5]_bret__0_bret__4
cores_70/backward/currentState_reg[5]_bret__1
cores_70/backward/currentState_reg[5]_bret__2
cores_70/backward/currentState_reg[5]_bret__3
cores_71/backward/currentState_reg[0]_bret__0
cores_71/backward/currentState_reg[0]_bret__1
cores_71/backward/currentState_reg[0]_bret__2
cores_71/backward/currentState_reg[0]_bret__3
cores_71/backward/currentState_reg[0]_bret__4
cores_71/backward/currentState_reg[0]_bret_bret
cores_71/backward/currentState_reg[0]_bret_bret__0
cores_71/backward/currentState_reg[0]_bret_bret__1
cores_71/backward/currentState_reg[0]_bret_bret__2
cores_71/backward/currentState_reg[0]_bret_bret__3
cores_71/backward/currentState_reg[0]_bret_bret__4
cores_71/backward/currentState_reg[1]_bret
cores_71/backward/currentState_reg[1]_bret__1
cores_71/backward/currentState_reg[1]_bret__2
cores_71/backward/currentState_reg[1]_bret__3
cores_71/backward/currentState_reg[2]_bret
cores_71/backward/currentState_reg[2]_bret__1
cores_71/backward/currentState_reg[2]_bret__2
cores_71/backward/currentState_reg[2]_bret__3
cores_71/backward/currentState_reg[3]_bret
cores_71/backward/currentState_reg[3]_bret__1
cores_71/backward/currentState_reg[3]_bret__2
cores_71/backward/currentState_reg[3]_bret__3
cores_71/backward/currentState_reg[4]_bret
cores_71/backward/currentState_reg[4]_bret__1
cores_71/backward/currentState_reg[4]_bret__2
cores_71/backward/currentState_reg[4]_bret__3
cores_71/backward/currentState_reg[5]_bret
cores_71/backward/currentState_reg[5]_bret__0_bret
cores_71/backward/currentState_reg[5]_bret__0_bret__0
cores_71/backward/currentState_reg[5]_bret__0_bret__1
cores_71/backward/currentState_reg[5]_bret__0_bret__2
cores_71/backward/currentState_reg[5]_bret__0_bret__3
cores_71/backward/currentState_reg[5]_bret__0_bret__4
cores_71/backward/currentState_reg[5]_bret__1
cores_71/backward/currentState_reg[5]_bret__2
cores_71/backward/currentState_reg[5]_bret__3
cores_72/backward/currentState_reg[0]_bret__0
cores_72/backward/currentState_reg[0]_bret__1
cores_72/backward/currentState_reg[0]_bret__2
cores_72/backward/currentState_reg[0]_bret__3
cores_72/backward/currentState_reg[0]_bret__4
cores_72/backward/currentState_reg[0]_bret_bret
cores_72/backward/currentState_reg[0]_bret_bret__0
cores_72/backward/currentState_reg[0]_bret_bret__1
cores_72/backward/currentState_reg[0]_bret_bret__2
cores_72/backward/currentState_reg[0]_bret_bret__3
cores_72/backward/currentState_reg[0]_bret_bret__4
cores_72/backward/currentState_reg[1]_bret
cores_72/backward/currentState_reg[1]_bret__1
cores_72/backward/currentState_reg[1]_bret__2
cores_72/backward/currentState_reg[1]_bret__3
cores_72/backward/currentState_reg[2]_bret
cores_72/backward/currentState_reg[2]_bret__1
cores_72/backward/currentState_reg[2]_bret__2
cores_72/backward/currentState_reg[2]_bret__3
cores_72/backward/currentState_reg[3]_bret
cores_72/backward/currentState_reg[3]_bret__1
cores_72/backward/currentState_reg[3]_bret__2
cores_72/backward/currentState_reg[3]_bret__3
cores_72/backward/currentState_reg[4]_bret
cores_72/backward/currentState_reg[4]_bret__1
cores_72/backward/currentState_reg[4]_bret__2
cores_72/backward/currentState_reg[4]_bret__3
cores_72/backward/currentState_reg[5]_bret
cores_72/backward/currentState_reg[5]_bret__0_bret
cores_72/backward/currentState_reg[5]_bret__0_bret__0
cores_72/backward/currentState_reg[5]_bret__0_bret__1
cores_72/backward/currentState_reg[5]_bret__0_bret__2
cores_72/backward/currentState_reg[5]_bret__0_bret__3
cores_72/backward/currentState_reg[5]_bret__0_bret__4
cores_72/backward/currentState_reg[5]_bret__1
cores_72/backward/currentState_reg[5]_bret__2
cores_72/backward/currentState_reg[5]_bret__3
cores_73/backward/currentState_reg[0]_bret__0
cores_73/backward/currentState_reg[0]_bret__1
cores_73/backward/currentState_reg[0]_bret__2
cores_73/backward/currentState_reg[0]_bret__3
cores_73/backward/currentState_reg[0]_bret__4
cores_73/backward/currentState_reg[0]_bret_bret
cores_73/backward/currentState_reg[0]_bret_bret__0
cores_73/backward/currentState_reg[0]_bret_bret__1
cores_73/backward/currentState_reg[0]_bret_bret__2
cores_73/backward/currentState_reg[0]_bret_bret__3
cores_73/backward/currentState_reg[0]_bret_bret__4
cores_73/backward/currentState_reg[1]_bret
cores_73/backward/currentState_reg[1]_bret__1
cores_73/backward/currentState_reg[1]_bret__2
cores_73/backward/currentState_reg[1]_bret__3
cores_73/backward/currentState_reg[2]_bret
cores_73/backward/currentState_reg[2]_bret__1
cores_73/backward/currentState_reg[2]_bret__2
cores_73/backward/currentState_reg[2]_bret__3
cores_73/backward/currentState_reg[3]_bret
cores_73/backward/currentState_reg[3]_bret__1
cores_73/backward/currentState_reg[3]_bret__2
cores_73/backward/currentState_reg[3]_bret__3
cores_73/backward/currentState_reg[4]_bret
cores_73/backward/currentState_reg[4]_bret__1
cores_73/backward/currentState_reg[4]_bret__2
cores_73/backward/currentState_reg[4]_bret__3
cores_73/backward/currentState_reg[5]_bret
cores_73/backward/currentState_reg[5]_bret__0_bret
cores_73/backward/currentState_reg[5]_bret__0_bret__0
cores_73/backward/currentState_reg[5]_bret__0_bret__1
cores_73/backward/currentState_reg[5]_bret__0_bret__2
cores_73/backward/currentState_reg[5]_bret__0_bret__3
cores_73/backward/currentState_reg[5]_bret__0_bret__4
cores_73/backward/currentState_reg[5]_bret__1
cores_73/backward/currentState_reg[5]_bret__2
cores_73/backward/currentState_reg[5]_bret__3
cores_74/backward/currentState_reg[0]_bret__0
cores_74/backward/currentState_reg[0]_bret__1
cores_74/backward/currentState_reg[0]_bret__2
cores_74/backward/currentState_reg[0]_bret__3
cores_74/backward/currentState_reg[0]_bret__4
cores_74/backward/currentState_reg[0]_bret_bret
cores_74/backward/currentState_reg[0]_bret_bret__0
cores_74/backward/currentState_reg[0]_bret_bret__1
cores_74/backward/currentState_reg[0]_bret_bret__2
cores_74/backward/currentState_reg[0]_bret_bret__3
cores_74/backward/currentState_reg[0]_bret_bret__4
cores_74/backward/currentState_reg[1]_bret
cores_74/backward/currentState_reg[1]_bret__1
cores_74/backward/currentState_reg[1]_bret__2
cores_74/backward/currentState_reg[1]_bret__3
cores_74/backward/currentState_reg[2]_bret
cores_74/backward/currentState_reg[2]_bret__1
cores_74/backward/currentState_reg[2]_bret__2
cores_74/backward/currentState_reg[2]_bret__3
cores_74/backward/currentState_reg[3]_bret
cores_74/backward/currentState_reg[3]_bret__1
cores_74/backward/currentState_reg[3]_bret__2
cores_74/backward/currentState_reg[3]_bret__3
cores_74/backward/currentState_reg[4]_bret
cores_74/backward/currentState_reg[4]_bret__1
cores_74/backward/currentState_reg[4]_bret__2
cores_74/backward/currentState_reg[4]_bret__3
cores_74/backward/currentState_reg[5]_bret
cores_74/backward/currentState_reg[5]_bret__0_bret
cores_74/backward/currentState_reg[5]_bret__0_bret__0
cores_74/backward/currentState_reg[5]_bret__0_bret__1
cores_74/backward/currentState_reg[5]_bret__0_bret__2
cores_74/backward/currentState_reg[5]_bret__0_bret__3
cores_74/backward/currentState_reg[5]_bret__0_bret__4
cores_74/backward/currentState_reg[5]_bret__1
cores_74/backward/currentState_reg[5]_bret__2
cores_74/backward/currentState_reg[5]_bret__3
cores_75/backward/currentState_reg[0]_bret__0
cores_75/backward/currentState_reg[0]_bret__1
cores_75/backward/currentState_reg[0]_bret__2
cores_75/backward/currentState_reg[0]_bret__3
cores_75/backward/currentState_reg[0]_bret__4
cores_75/backward/currentState_reg[0]_bret_bret
cores_75/backward/currentState_reg[0]_bret_bret__0
cores_75/backward/currentState_reg[0]_bret_bret__1
cores_75/backward/currentState_reg[0]_bret_bret__2
cores_75/backward/currentState_reg[0]_bret_bret__3
cores_75/backward/currentState_reg[0]_bret_bret__4
cores_75/backward/currentState_reg[1]_bret
cores_75/backward/currentState_reg[1]_bret__1
cores_75/backward/currentState_reg[1]_bret__2
cores_75/backward/currentState_reg[1]_bret__3
cores_75/backward/currentState_reg[2]_bret
cores_75/backward/currentState_reg[2]_bret__1
cores_75/backward/currentState_reg[2]_bret__2
cores_75/backward/currentState_reg[2]_bret__3
cores_75/backward/currentState_reg[3]_bret
cores_75/backward/currentState_reg[3]_bret__1
cores_75/backward/currentState_reg[3]_bret__2
cores_75/backward/currentState_reg[3]_bret__3
cores_75/backward/currentState_reg[4]_bret
cores_75/backward/currentState_reg[4]_bret__1
cores_75/backward/currentState_reg[4]_bret__2
cores_75/backward/currentState_reg[4]_bret__3
cores_75/backward/currentState_reg[5]_bret
cores_75/backward/currentState_reg[5]_bret__0_bret
cores_75/backward/currentState_reg[5]_bret__0_bret__0
cores_75/backward/currentState_reg[5]_bret__0_bret__1
cores_75/backward/currentState_reg[5]_bret__0_bret__2
cores_75/backward/currentState_reg[5]_bret__0_bret__3
cores_75/backward/currentState_reg[5]_bret__0_bret__4
cores_75/backward/currentState_reg[5]_bret__1
cores_75/backward/currentState_reg[5]_bret__2
cores_75/backward/currentState_reg[5]_bret__3
cores_76/backward/currentState_reg[0]_bret__0
cores_76/backward/currentState_reg[0]_bret__1
cores_76/backward/currentState_reg[0]_bret__2
cores_76/backward/currentState_reg[0]_bret__3
cores_76/backward/currentState_reg[0]_bret__4
cores_76/backward/currentState_reg[0]_bret_bret
cores_76/backward/currentState_reg[0]_bret_bret__0
cores_76/backward/currentState_reg[0]_bret_bret__1
cores_76/backward/currentState_reg[0]_bret_bret__2
cores_76/backward/currentState_reg[0]_bret_bret__3
cores_76/backward/currentState_reg[0]_bret_bret__4
cores_76/backward/currentState_reg[1]_bret
cores_76/backward/currentState_reg[1]_bret__1
cores_76/backward/currentState_reg[1]_bret__2
cores_76/backward/currentState_reg[1]_bret__3
cores_76/backward/currentState_reg[2]_bret
cores_76/backward/currentState_reg[2]_bret__1
cores_76/backward/currentState_reg[2]_bret__2
cores_76/backward/currentState_reg[2]_bret__3
cores_76/backward/currentState_reg[3]_bret
cores_76/backward/currentState_reg[3]_bret__1
cores_76/backward/currentState_reg[3]_bret__2
cores_76/backward/currentState_reg[3]_bret__3
cores_76/backward/currentState_reg[4]_bret
cores_76/backward/currentState_reg[4]_bret__1
cores_76/backward/currentState_reg[4]_bret__2
cores_76/backward/currentState_reg[4]_bret__3
cores_76/backward/currentState_reg[5]_bret
cores_76/backward/currentState_reg[5]_bret__0_bret
cores_76/backward/currentState_reg[5]_bret__0_bret__0
cores_76/backward/currentState_reg[5]_bret__0_bret__1
cores_76/backward/currentState_reg[5]_bret__0_bret__2
cores_76/backward/currentState_reg[5]_bret__0_bret__3
cores_76/backward/currentState_reg[5]_bret__0_bret__4
cores_76/backward/currentState_reg[5]_bret__1
cores_76/backward/currentState_reg[5]_bret__2
cores_76/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB17_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB18_tempName`
Numbers of forward move = 0, and backward move = 24
Retimed registers names:
cores_124/backward/currentState_reg[0]_bret__0
cores_124/backward/currentState_reg[0]_bret__1
cores_124/backward/currentState_reg[0]_bret__2
cores_124/backward/currentState_reg[0]_bret__3
cores_124/backward/currentState_reg[0]_bret__4
cores_124/backward/currentState_reg[0]_bret_bret
cores_124/backward/currentState_reg[0]_bret_bret__0
cores_124/backward/currentState_reg[0]_bret_bret__1
cores_124/backward/currentState_reg[0]_bret_bret__2
cores_124/backward/currentState_reg[0]_bret_bret__3
cores_124/backward/currentState_reg[0]_bret_bret__4
cores_124/backward/currentState_reg[1]_bret
cores_124/backward/currentState_reg[1]_bret__1
cores_124/backward/currentState_reg[1]_bret__2
cores_124/backward/currentState_reg[1]_bret__3
cores_124/backward/currentState_reg[2]_bret
cores_124/backward/currentState_reg[2]_bret__1
cores_124/backward/currentState_reg[2]_bret__2
cores_124/backward/currentState_reg[2]_bret__3
cores_124/backward/currentState_reg[3]_bret
cores_124/backward/currentState_reg[3]_bret__1
cores_124/backward/currentState_reg[3]_bret__2
cores_124/backward/currentState_reg[3]_bret__3
cores_124/backward/currentState_reg[4]_bret
cores_124/backward/currentState_reg[4]_bret__1
cores_124/backward/currentState_reg[4]_bret__2
cores_124/backward/currentState_reg[4]_bret__3
cores_124/backward/currentState_reg[5]_bret
cores_124/backward/currentState_reg[5]_bret__0_bret
cores_124/backward/currentState_reg[5]_bret__0_bret__0
cores_124/backward/currentState_reg[5]_bret__0_bret__1
cores_124/backward/currentState_reg[5]_bret__0_bret__2
cores_124/backward/currentState_reg[5]_bret__0_bret__3
cores_124/backward/currentState_reg[5]_bret__0_bret__4
cores_124/backward/currentState_reg[5]_bret__1
cores_124/backward/currentState_reg[5]_bret__2
cores_124/backward/currentState_reg[5]_bret__3
cores_65/backward/currentState_reg[0]_bret__0
cores_65/backward/currentState_reg[0]_bret__1
cores_65/backward/currentState_reg[0]_bret__2
cores_65/backward/currentState_reg[0]_bret__3
cores_65/backward/currentState_reg[0]_bret__4
cores_65/backward/currentState_reg[0]_bret_bret
cores_65/backward/currentState_reg[0]_bret_bret__0
cores_65/backward/currentState_reg[0]_bret_bret__1
cores_65/backward/currentState_reg[0]_bret_bret__2
cores_65/backward/currentState_reg[0]_bret_bret__3
cores_65/backward/currentState_reg[0]_bret_bret__4
cores_65/backward/currentState_reg[1]_bret
cores_65/backward/currentState_reg[1]_bret__1
cores_65/backward/currentState_reg[1]_bret__2
cores_65/backward/currentState_reg[1]_bret__3
cores_65/backward/currentState_reg[2]_bret
cores_65/backward/currentState_reg[2]_bret__1
cores_65/backward/currentState_reg[2]_bret__2
cores_65/backward/currentState_reg[2]_bret__3
cores_65/backward/currentState_reg[3]_bret
cores_65/backward/currentState_reg[3]_bret__1
cores_65/backward/currentState_reg[3]_bret__2
cores_65/backward/currentState_reg[3]_bret__3
cores_65/backward/currentState_reg[4]_bret
cores_65/backward/currentState_reg[4]_bret__1
cores_65/backward/currentState_reg[4]_bret__2
cores_65/backward/currentState_reg[4]_bret__3
cores_65/backward/currentState_reg[5]_bret
cores_65/backward/currentState_reg[5]_bret__0_bret
cores_65/backward/currentState_reg[5]_bret__0_bret__0
cores_65/backward/currentState_reg[5]_bret__0_bret__1
cores_65/backward/currentState_reg[5]_bret__0_bret__2
cores_65/backward/currentState_reg[5]_bret__0_bret__3
cores_65/backward/currentState_reg[5]_bret__0_bret__4
cores_65/backward/currentState_reg[5]_bret__1
cores_65/backward/currentState_reg[5]_bret__2
cores_65/backward/currentState_reg[5]_bret__3
cores_69/backward/currentState_reg[0]_bret__0
cores_69/backward/currentState_reg[0]_bret__1
cores_69/backward/currentState_reg[0]_bret__2
cores_69/backward/currentState_reg[0]_bret__3
cores_69/backward/currentState_reg[0]_bret__4
cores_69/backward/currentState_reg[0]_bret_bret
cores_69/backward/currentState_reg[0]_bret_bret__0
cores_69/backward/currentState_reg[0]_bret_bret__1
cores_69/backward/currentState_reg[0]_bret_bret__2
cores_69/backward/currentState_reg[0]_bret_bret__3
cores_69/backward/currentState_reg[0]_bret_bret__4
cores_69/backward/currentState_reg[1]_bret
cores_69/backward/currentState_reg[1]_bret__1
cores_69/backward/currentState_reg[1]_bret__2
cores_69/backward/currentState_reg[1]_bret__3
cores_69/backward/currentState_reg[2]_bret
cores_69/backward/currentState_reg[2]_bret__1
cores_69/backward/currentState_reg[2]_bret__2
cores_69/backward/currentState_reg[2]_bret__3
cores_69/backward/currentState_reg[3]_bret
cores_69/backward/currentState_reg[3]_bret__1
cores_69/backward/currentState_reg[3]_bret__2
cores_69/backward/currentState_reg[3]_bret__3
cores_69/backward/currentState_reg[4]_bret
cores_69/backward/currentState_reg[4]_bret__1
cores_69/backward/currentState_reg[4]_bret__2
cores_69/backward/currentState_reg[4]_bret__3
cores_69/backward/currentState_reg[5]_bret
cores_69/backward/currentState_reg[5]_bret__0_bret
cores_69/backward/currentState_reg[5]_bret__0_bret__0
cores_69/backward/currentState_reg[5]_bret__0_bret__1
cores_69/backward/currentState_reg[5]_bret__0_bret__2
cores_69/backward/currentState_reg[5]_bret__0_bret__3
cores_69/backward/currentState_reg[5]_bret__0_bret__4
cores_69/backward/currentState_reg[5]_bret__1
cores_69/backward/currentState_reg[5]_bret__2
cores_69/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn__GB18_tempName' done
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthViterbiFtn' done
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:05:41 ; elapsed = 00:07:19 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 21350 ; free virtual = 58149
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:06:00 ; elapsed = 00:07:39 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23419 ; free virtual = 60316
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:06:01 ; elapsed = 00:07:40 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23302 ; free virtual = 60199
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:06:15 ; elapsed = 00:07:54 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23297 ; free virtual = 60194
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:06:15 ; elapsed = 00:07:54 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23296 ; free virtual = 60193
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:06:18 ; elapsed = 00:07:58 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23148 ; free virtual = 60045
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:06:19 ; elapsed = 00:07:58 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23142 ; free virtual = 60039
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+----------------+-----------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+----------------+-----------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|synthViterbiFtn | cores_51/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_51/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_47/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_47/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_44/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_44/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_40/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_40/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_39/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_39/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_48/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_48/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_26/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_26/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_14/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_14/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_2/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_2/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_0/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_0/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_123/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_123/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_108/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_108/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_105/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_105/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_100/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_100/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_94/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_94/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_86/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_86/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_77/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_77/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_66/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_66/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_124/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthViterbiFtn | cores_124/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
+----------------+-----------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
Retiming Report:
+--------------------+------+
|Retiming summary: | |
+--------------------+------+
|Forward Retiming | 0 |
|Backward Retiming | 976 |
|New registers added | 4514 |
|Registers deleted | 732 |
+--------------------+------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |LUT1 | 280|
|2 |LUT2 | 4925|
|3 |LUT3 | 2408|
|4 |LUT4 | 41910|
|5 |LUT5 | 25348|
|6 |LUT6 | 50454|
|7 |MUXF7 | 4064|
|8 |MUXF8 | 244|
|9 |RAM128X1D | 127|
|10 |RAM64M8 | 370|
|11 |RAMB36E2 | 488|
|13 |SRLC32E | 76|
|14 |FDCE | 26881|
|15 |FDPE | 8270|
|16 |FDRE | 3365|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:06:19 ; elapsed = 00:07:58 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 23138 ; free virtual = 60035
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 127 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:05:59 ; elapsed = 00:07:44 . Memory (MB): peak = 7058.367 ; gain = 1544.809 ; free physical = 34411 ; free virtual = 71308
Synthesis Optimization Complete : Time (s): cpu = 00:06:23 ; elapsed = 00:08:03 . Memory (MB): peak = 7058.367 ; gain = 1781.809 ; free physical = 34429 ; free virtual = 71308
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 7058.367 ; gain = 0.000 ; free physical = 34371 ; free virtual = 71250
INFO: [Netlist 29-17] Analyzing 4805 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 7066.371 ; gain = 0.000 ; free physical = 34296 ; free virtual = 71175
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 497 instances were transformed.
RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 127 instances
RAM64M8 => RAM64M8 (RAMD64E(x8)): 370 instances
Synth Design complete, checksum: d28fd1fc
INFO: [Common 17-83] Releasing license: Synthesis
1027 Infos, 201 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:06:55 ; elapsed = 00:08:35 . Memory (MB): peak = 7066.371 ; gain = 1898.570 ; free physical = 34538 ; free virtual = 71417
# write_checkpoint -force synthViterbiFtn_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthViterbiFtn/synthViterbiFtn_after_synth.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:32 ; elapsed = 00:00:19 . Memory (MB): peak = 7210.441 ; gain = 144.070 ; free physical = 34223 ; free virtual = 71199
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:33:24 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthViterbiFtn
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+----------------------------+--------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+--------+-------+------------+-----------+-------+
| CLB LUTs* | 120487 | 0 | 0 | 1182240 | 10.19 |
| LUT as Logic | 116943 | 0 | 0 | 1182240 | 9.89 |
| LUT as Memory | 3544 | 0 | 0 | 591840 | 0.60 |
| LUT as Distributed RAM | 3468 | 0 | | | |
| LUT as Shift Register | 76 | 0 | | | |
| CLB Registers | 38516 | 0 | 0 | 2364480 | 1.63 |
| Register as Flip Flop | 38516 | 0 | 0 | 2364480 | 1.63 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 147780 | 0.00 |
| F7 Muxes | 4318 | 0 | 0 | 591120 | 0.73 |
| F8 Muxes | 244 | 0 | 0 | 295560 | 0.08 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+----------------------------+--------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 8270 | Yes | - | Set |
| 26881 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 3365 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 488 | 0 | 0 | 2160 | 22.59 |
| RAMB36/FIFO* | 488 | 0 | 0 | 2160 | 22.59 |
| RAMB36E2 only | 488 | | | | |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+----------+-------+---------------------+
| LUT6 | 50454 | CLB |
| LUT4 | 41910 | CLB |
| FDCE | 26881 | Register |
| LUT5 | 25348 | CLB |
| FDPE | 8270 | Register |
| LUT2 | 4925 | CLB |
| MUXF7 | 4318 | CLB |
| RAMD64E | 3468 | CLB |
| FDRE | 3365 | Register |
| LUT3 | 2408 | CLB |
| RAMB36E2 | 488 | BLOCKRAM |
| LUT1 | 280 | CLB |
| MUXF8 | 244 | CLB |
| SRLC32E | 76 | CLB |
+----------+-------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:33:49 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthViterbiFtn
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -0.417ns (required time - arrival time)
Source: cores_0/recordStack_reg_3/CLKARDCLK
(rising edge-triggered cell RAMB36E2 clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: cores_0/backward/currentState_reg[5]_bret__0_bret__0/D
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 1.601ns (logic 1.171ns (73.142%) route 0.430ns (26.858%))
Logic Levels: 3 (LUT6=2 MUXF7=1)
Clock Path Skew: -0.056ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.076ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=43035, unset) 0.076 0.076 cores_0/clk
RAMB36E2 r cores_0/recordStack_reg_3/CLKARDCLK
------------------------------------------------------------------- -------------------
RAMB36E2 (Prop_RAMB36E2_CLKARDCLK_DOUTADOUT[18])
0.856 0.932 r cores_0/recordStack_reg_3/DOUTADOUT[18]
net (fo=1, unplaced) 0.208 1.140 cores_0/backward/_zz_recordStack_port1[234]
LUT6 (Prop_LUT6_I0_O) 0.150 1.290 r cores_0/backward/currentState[5]_bret__0_bret__0_i_7__57/O
net (fo=1, unplaced) 0.018 1.308 cores_0/backward/currentState[5]_bret__0_bret__0_i_7__57_n_0
MUXF7 (Prop_MUXF7_I1_O) 0.065 1.373 r cores_0/backward/currentState_reg[5]_bret__0_bret__0_i_2__57/O
net (fo=1, unplaced) 0.156 1.529 cores_0/backward/currentState_reg[5]_bret__0_bret__0_i_2__57_n_0
LUT6 (Prop_LUT6_I0_O) 0.100 1.629 r cores_0/backward/currentState[5]_bret__0_bret__0_i_1__57/O
net (fo=1, unplaced) 0.048 1.677 cores_0/backward/candidateDiscrepancies_0__123[2]
FDCE r cores_0/backward/currentState_reg[5]_bret__0_bret__0/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=43035, unset) 0.020 1.270 cores_0/backward/clk
FDCE r cores_0/backward/currentState_reg[5]_bret__0_bret__0/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDCE (Setup_FDCE_C_D) 0.025 1.260 cores_0/backward/currentState_reg[5]_bret__0_bret__0
-------------------------------------------------------------------
required time 1.260
arrival time -1.677
-------------------------------------------------------------------
slack -0.417
report_timing: Time (s): cpu = 00:00:42 ; elapsed = 00:00:25 . Memory (MB): peak = 7771.109 ; gain = 560.668 ; free physical = 33964 ; free virtual = 70940
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:33:50 2022...
-
[INFO ]
-
: binary adder cost = 70104
-
[INFO ]
-
: ternary adder cost = 0
-
[INFO ]
-
: reg cost = 86106
-
[INFO ]
-
:
LUT: 120487
FF: 38516
DSP: 0
BRAM: 488
CARRY8: 0
-
[INFO ]
-
:
fmax = 599.8800239952009 MHz
-
1 m 20 s
passedshould synth for deintrlvFtn
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:33:54
[Progress] at 2078.577 : Elaborate components
[Progress] at 2078.628 : Checks and transforms
[Progress] at 2078.664 : Generate Verilog
[Done] at 2078.675
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog synthDeintrlvFtn.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthDeintrlvFtn -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthDeintrlvFtn -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 20458
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5612.348 ; gain = 337.793 ; free physical = 34667 ; free virtual = 71140
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthDeintrlvFtn' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthDeintrlvFtn/synthDeintrlvFtn.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthDeintrlvFtn' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthDeintrlvFtn/synthDeintrlvFtn.v:6]
WARNING: [Synth 8-7129] Port validIn in module synthDeintrlvFtn is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5677.285 ; gain = 402.730 ; free physical = 35978 ; free virtual = 72451
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5695.098 ; gain = 420.543 ; free physical = 35978 ; free virtual = 72452
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5695.098 ; gain = 420.543 ; free physical = 35978 ; free virtual = 72452
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 5695.098 ; gain = 0.000 ; free physical = 35971 ; free virtual = 72444
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthDeintrlvFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthDeintrlvFtn/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5848.660 ; gain = 0.000 ; free physical = 35846 ; free virtual = 72325
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00 . Memory (MB): peak = 5848.660 ; gain = 0.000 ; free physical = 35846 ; free virtual = 72325
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 5848.660 ; gain = 574.105 ; free physical = 35934 ; free virtual = 72414
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 5848.660 ; gain = 574.105 ; free physical = 35936 ; free virtual = 72416
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 5848.660 ; gain = 574.105 ; free physical = 35938 ; free virtual = 72418
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 5848.660 ; gain = 574.105 ; free physical = 35930 ; free virtual = 72411
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 7 Bit Adders := 1
+---Registers :
7 Bit Registers := 1
+---Muxes :
2 Input 254 Bit Muxes := 7
2 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port validIn in module synthDeintrlvFtn is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 5848.660 ; gain = 574.105 ; free physical = 35752 ; free virtual = 72237
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:27 . Memory (MB): peak = 6053.926 ; gain = 779.371 ; free physical = 35455 ; free virtual = 71940
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35386 ; free virtual = 71871
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `synthDeintrlvFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthDeintrlvFtn' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35382 ; free virtual = 71867
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35381 ; free virtual = 71866
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35381 ; free virtual = 71866
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35381 ; free virtual = 71866
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:34 ; elapsed = 00:00:35 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35381 ; free virtual = 71866
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35381 ; free virtual = 71866
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35381 ; free virtual = 71866
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT2 | 1|
|2 |LUT3 | 4|
|3 |LUT4 | 2|
|4 |LUT5 | 259|
|5 |LUT6 | 767|
|6 |FDCE | 8|
|7 |FDRE | 254|
+------+-----+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 6232.191 ; gain = 957.637 ; free physical = 35381 ; free virtual = 71866
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 6232.191 ; gain = 804.074 ; free physical = 35414 ; free virtual = 71899
Synthesis Optimization Complete : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 6232.199 ; gain = 957.637 ; free physical = 35414 ; free virtual = 71899
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6232.199 ; gain = 0.000 ; free physical = 35496 ; free virtual = 71981
WARNING: [Netlist 29-101] Netlist 'synthDeintrlvFtn' is not ideal for floorplanning, since the cellview 'synthDeintrlvFtn' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthDeintrlvFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthDeintrlvFtn/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6238.129 ; gain = 0.000 ; free physical = 35393 ; free virtual = 71878
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: fa64980e
INFO: [Common 17-83] Releasing license: Synthesis
17 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:49 ; elapsed = 00:00:47 . Memory (MB): peak = 6238.129 ; gain = 1070.332 ; free physical = 35630 ; free virtual = 72115
# write_checkpoint -force synthDeintrlvFtn_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthDeintrlvFtn/synthDeintrlvFtn_after_synth.dcp' has been generated.
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:34:51 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthDeintrlvFtn
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| CLB LUTs* | 1033 | 0 | 0 | 1182240 | 0.09 |
| LUT as Logic | 1033 | 0 | 0 | 1182240 | 0.09 |
| LUT as Memory | 0 | 0 | 0 | 591840 | 0.00 |
| CLB Registers | 262 | 0 | 0 | 2364480 | 0.01 |
| Register as Flip Flop | 262 | 0 | 0 | 2364480 | 0.01 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 147780 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 591120 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 8 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 254 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT6 | 767 | CLB |
| LUT5 | 259 | CLB |
| FDRE | 254 | Register |
| FDCE | 8 | Register |
| LUT3 | 4 | CLB |
| LUT4 | 2 | CLB |
| LUT2 | 1 | CLB |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:35:10 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthDeintrlvFtn
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -0.579ns (required time - arrival time)
Source: localCounter_value_reg[4]/C
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: ret_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 1.811ns (logic 0.568ns (31.364%) route 1.243ns (68.636%))
Logic Levels: 6 (LUT5=2 LUT6=4)
Clock Path Skew: -0.008ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.028ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=261, unset) 0.028 0.028 clk
FDCE r localCounter_value_reg[4]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_FDCE_C_Q) 0.077 0.105 r localCounter_value_reg[4]/Q
net (fo=5, unplaced) 0.126 0.231 localCounter_value[4]
LUT5 (Prop_LUT5_I0_O) 0.125 0.356 r ret[0]_i_2/O
net (fo=129, unplaced) 0.246 0.602 ret[0]_i_2_n_0
LUT6 (Prop_LUT6_I1_O) 0.090 0.692 r localCounter_value[6]_i_1/O
net (fo=128, unplaced) 0.288 0.980 p_0_in[6]
LUT6 (Prop_LUT6_I4_O) 0.038 1.018 r ret[0]_i_30/O
net (fo=4, unplaced) 0.169 1.187 _zz_ret_5[120]
LUT6 (Prop_LUT6_I0_O) 0.100 1.287 r ret[0]_i_10/O
net (fo=4, unplaced) 0.169 1.456 _zz_ret_3[96]
LUT6 (Prop_LUT6_I0_O) 0.100 1.556 r ret[0]_i_5/O
net (fo=2, unplaced) 0.197 1.753 _zz_ret_1[0]
LUT5 (Prop_LUT5_I4_O) 0.038 1.791 r ret[0]_i_1/O
net (fo=1, unplaced) 0.048 1.839 _zz_ret[0]
FDRE r ret_reg[0]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=261, unset) 0.020 1.270 clk
FDRE r ret_reg[0]/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDRE (Setup_FDRE_C_D) 0.025 1.260 ret_reg[0]
-------------------------------------------------------------------
required time 1.260
arrival time -1.839
-------------------------------------------------------------------
slack -0.579
report_timing: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 7076.543 ; gain = 699.512 ; free physical = 35115 ; free virtual = 71600
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:35:10 2022...
-
[INFO ]
-
: binary adder cost = 7
-
[INFO ]
-
: ternary adder cost = 0
-
[INFO ]
-
: reg cost = 7
-
[INFO ]
-
:
LUT: 1033
FF: 262
DSP: 0
BRAM: 0
CARRY8: 0
-
[INFO ]
-
:
fmax = 546.7468562055768 MHz
-
1 m 45 s
passedshould synth for qamdemodFtn
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:35:14
[Progress] at 2158.803 : Elaborate components
[Progress] at 2158.917 : Checks and transforms
[Progress] at 2159.315 : Generate Verilog
[Warning] 3 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 2159.500
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog unamed.v
# read_verilog unamed_1.v
# read_verilog synthQamdemodFtn.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthQamdemodFtn -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthQamdemodFtn -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 21680
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5613.328 ; gain = 338.793 ; free physical = 34846 ; free virtual = 71327
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthQamdemodFtn' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/synthQamdemodFtn.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/unamed.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/unamed.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_1' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/unamed_1.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_1' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/unamed_1.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthQamdemodFtn' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/synthQamdemodFtn.v:6]
WARNING: [Synth 8-7129] Port validIn in module unamed_1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 5779.203 ; gain = 504.668 ; free physical = 35868 ; free virtual = 72352
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 5794.047 ; gain = 519.512 ; free physical = 35838 ; free virtual = 72322
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 5794.047 ; gain = 519.512 ; free physical = 35838 ; free virtual = 72322
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.16 . Memory (MB): peak = 5794.047 ; gain = 0.000 ; free physical = 35853 ; free virtual = 72337
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 5975.672 ; gain = 0.000 ; free physical = 35725 ; free virtual = 72209
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.1 . Memory (MB): peak = 5975.672 ; gain = 0.000 ; free physical = 35724 ; free virtual = 72207
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 5975.672 ; gain = 701.137 ; free physical = 35865 ; free virtual = 72349
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 5975.672 ; gain = 701.137 ; free physical = 35865 ; free virtual = 72349
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 5975.672 ; gain = 701.137 ; free physical = 35865 ; free virtual = 72349
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 5975.672 ; gain = 701.137 ; free physical = 35847 ; free virtual = 72334
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
3 Input 18 Bit Adders := 508
2 Input 2 Bit Adders := 1
+---Registers :
18 Bit Registers := 508
4 Bit Registers := 254
1 Bit Registers := 1528
+---Muxes :
2 Input 18 Bit Muxes := 508
2 Input 2 Bit Muxes := 1
4 Input 1 Bit Muxes := 254
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 5975.672 ; gain = 701.137 ; free physical = 35806 ; free virtual = 72313
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:43 . Memory (MB): peak = 6099.406 ; gain = 824.871 ; free physical = 35253 ; free virtual = 71760
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:45 ; elapsed = 00:00:48 . Memory (MB): peak = 6144.422 ; gain = 869.887 ; free physical = 35161 ; free virtual = 71668
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `synthQamdemodFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthQamdemodFtn' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:48 ; elapsed = 00:00:51 . Memory (MB): peak = 6168.445 ; gain = 893.910 ; free physical = 35488 ; free virtual = 71995
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:52 ; elapsed = 00:00:55 . Memory (MB): peak = 6176.383 ; gain = 901.848 ; free physical = 35298 ; free virtual = 71804
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:52 ; elapsed = 00:00:55 . Memory (MB): peak = 6176.383 ; gain = 901.848 ; free physical = 35298 ; free virtual = 71804
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:53 ; elapsed = 00:00:55 . Memory (MB): peak = 6176.383 ; gain = 901.848 ; free physical = 35301 ; free virtual = 71808
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:53 ; elapsed = 00:00:56 . Memory (MB): peak = 6176.383 ; gain = 901.848 ; free physical = 35276 ; free virtual = 71782
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:53 ; elapsed = 00:00:56 . Memory (MB): peak = 6176.383 ; gain = 901.848 ; free physical = 35232 ; free virtual = 71738
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:53 ; elapsed = 00:00:56 . Memory (MB): peak = 6176.383 ; gain = 901.848 ; free physical = 35175 ; free virtual = 71681
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |CARRY8 | 1524|
|2 |LUT1 | 762|
|3 |LUT2 | 8131|
|4 |LUT3 | 510|
|5 |LUT6 | 254|
|6 |FDCE | 6|
|7 |FDRE | 3048|
+------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:53 ; elapsed = 00:00:56 . Memory (MB): peak = 6176.383 ; gain = 901.848 ; free physical = 35172 ; free virtual = 71679
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:46 ; elapsed = 00:00:49 . Memory (MB): peak = 6176.383 ; gain = 720.223 ; free physical = 35200 ; free virtual = 71706
Synthesis Optimization Complete : Time (s): cpu = 00:00:53 ; elapsed = 00:00:56 . Memory (MB): peak = 6176.391 ; gain = 901.848 ; free physical = 35200 ; free virtual = 71706
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.14 . Memory (MB): peak = 6187.289 ; gain = 0.000 ; free physical = 35292 ; free virtual = 71799
INFO: [Netlist 29-17] Analyzing 1524 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
WARNING: [Netlist 29-101] Netlist 'synthQamdemodFtn' is not ideal for floorplanning, since the cellview 'unamed' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 6257.422 ; gain = 0.000 ; free physical = 35461 ; free virtual = 71967
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: b3dbafa4
INFO: [Common 17-83] Releasing license: Synthesis
23 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:10 ; elapsed = 00:01:10 . Memory (MB): peak = 6257.422 ; gain = 1089.645 ; free physical = 35685 ; free virtual = 72191
# write_checkpoint -force synthQamdemodFtn_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthQamdemodFtn/synthQamdemodFtn_after_synth.dcp' has been generated.
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:36:35 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthQamdemodFtn
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| CLB LUTs* | 9149 | 0 | 0 | 1182240 | 0.77 |
| LUT as Logic | 9149 | 0 | 0 | 1182240 | 0.77 |
| LUT as Memory | 0 | 0 | 0 | 591840 | 0.00 |
| CLB Registers | 3054 | 0 | 0 | 2364480 | 0.13 |
| Register as Flip Flop | 3054 | 0 | 0 | 2364480 | 0.13 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 1524 | 0 | 0 | 147780 | 1.03 |
| F7 Muxes | 0 | 0 | 0 | 591120 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 6 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 3048 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT2 | 8131 | CLB |
| FDRE | 3048 | Register |
| CARRY8 | 1524 | CLB |
| LUT1 | 762 | CLB |
| LUT3 | 510 | CLB |
| LUT6 | 254 | CLB |
| FDCE | 6 | Register |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:36:55 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthQamdemodFtn
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (MET) : 0.471ns (required time - arrival time)
Source: p2s/localCounter_value_reg[0]/C
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: p2s/dataIn_1000_regNextWhen_reg[0]/CE
(rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 0.675ns (logic 0.115ns (17.037%) route 0.560ns (82.963%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.008ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.028ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=3053, unset) 0.028 0.028 p2s/clk
FDCE r p2s/localCounter_value_reg[0]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_FDCE_C_Q) 0.077 0.105 f p2s/localCounter_value_reg[0]/Q
net (fo=131, unplaced) 0.241 0.346 p2s/localCounter_value[0]
LUT2 (Prop_LUT2_I1_O) 0.038 0.384 r p2s/dataIn_762_regNextWhen[0]_i_1/O
net (fo=762, unplaced) 0.319 0.703 p2s/when_P2S_l56
FDRE r p2s/dataIn_1000_regNextWhen_reg[0]/CE
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=3053, unset) 0.020 1.270 p2s/clk
FDRE r p2s/dataIn_1000_regNextWhen_reg[0]/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDRE (Setup_FDRE_C_CE) -0.061 1.174 p2s/dataIn_1000_regNextWhen_reg[0]
-------------------------------------------------------------------
required time 1.174
arrival time -0.703
-------------------------------------------------------------------
slack 0.471
report_timing: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 7117.809 ; gain = 709.512 ; free physical = 35065 ; free virtual = 71574
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:36:56 2022...
-
[INFO ]
-
: binary adder cost = 2
-
[INFO ]
-
: ternary adder cost = 9144
-
[INFO ]
-
: reg cost = 11688
-
[INFO ]
-
:
LUT: 9149
FF: 3054
DSP: 0
BRAM: 0
CARRY8: 1524
-
[INFO ]
-
:
fmax = 1283.697047496791 MHz
-
7 m 21 s
passedshould synth for rvFftFtn
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:36:59
[Progress] at 2264.250 : Elaborate components
[Progress] at 2264.402 : Checks and transforms
[Progress] at 2265.771 : Generate Verilog
[Warning] 248 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 2266.291
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog ComplexMult.v
# read_verilog unamed.v
# read_verilog unamed_3.v
# read_verilog unamed_11.v
# read_verilog unamed_20.v
# read_verilog unamed_21.v
# read_verilog unamed_22.v
# read_verilog unamed_23.v
# read_verilog unamed_24.v
# read_verilog unamed_25.v
# read_verilog unamed_26.v
# read_verilog unamed_31.v
# read_verilog unamed_32.v
# read_verilog unamed_33.v
# read_verilog unamed_34.v
# read_verilog unamed_38.v
# read_verilog unamed_40.v
# read_verilog unamed_41.v
# read_verilog unamed_42.v
# read_verilog unamed_47.v
# read_verilog unamed_48.v
# read_verilog unamed_49.v
# read_verilog unamed_50.v
# read_verilog unamed_56.v
# read_verilog unamed_57.v
# read_verilog unamed_58.v
# read_verilog unamed_65.v
# read_verilog unamed_66.v
# read_verilog unamed_74.v
# read_verilog unamed_91.v
# read_verilog unamed_92.v
# read_verilog unamed_94.v
# read_verilog unamed_95.v
# read_verilog unamed_103.v
# read_verilog matintrlv_r64_c8_w36_sw64_dut.v
# read_verilog matintrlv_r8_c64_w36_sw64_dut.v
# read_verilog fft_n64_factors_8_8_scales_2_2_dut.v
# read_verilog fft_n8_factors_8_scales_1_dut.v
# read_verilog anon.v
# read_verilog unamed_104.v
# read_verilog rvFftPre_dut.v
# read_verilog fft_n512_sw64_factors_8_8_8_dut.v
# read_verilog unamed_105.v
# read_verilog anon_1.v
# read_verilog rvFftPre_fft_n512_sw64_factors_8_8_8_dut.v
# read_verilog rvFftPost_dut.v
# read_verilog unamed_106.v
# read_verilog synthRvFftFtn.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthRvFftFtn -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthRvFftFtn -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 23361
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5613.324 ; gain = 337.793 ; free physical = 34811 ; free virtual = 71298
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthRvFftFtn' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/synthRvFftFtn.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_106' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_106.v:6]
INFO: [Synth 8-6157] synthesizing module 'rvFftPre_fft_n512_sw64_factors_8_8_8_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/rvFftPre_fft_n512_sw64_factors_8_8_8_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_105' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_105.v:6]
INFO: [Synth 8-6157] synthesizing module 'rvFftPre_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/rvFftPre_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'anon' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_103' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_103.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_103' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_103.v:6]
INFO: [Synth 8-6155] done synthesizing module 'anon' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:6]
INFO: [Synth 8-6155] done synthesizing module 'rvFftPre_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/rvFftPre_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'fft_n512_sw64_factors_8_8_8_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/fft_n512_sw64_factors_8_8_8_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_104' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:6]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_0.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2365]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_1.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2374]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_2.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2383]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_3.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2392]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_4.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2401]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_5.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2410]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_6.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2419]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_7.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2428]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_8.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2437]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_9.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2446]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_10.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2455]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_11.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2464]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_12.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2473]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_13.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2482]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_14.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2491]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_15.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2500]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_16.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2509]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_17.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2518]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_18.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2527]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_19.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2536]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_20.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2545]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_21.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2554]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_22.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2563]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_23.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2572]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_24.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2581]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_25.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2590]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_26.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2599]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_27.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2608]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_28.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2617]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_29.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2626]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_30.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2635]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_31.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2644]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_32.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2653]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_33.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2662]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_34.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2671]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_35.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2680]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_36.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2689]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_37.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2698]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_38.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2707]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_39.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2716]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_40.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2725]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_41.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2734]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_42.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2743]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_43.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2752]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_44.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2761]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_45.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2770]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_46.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2779]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_47.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2788]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_48.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2797]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_49.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2806]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_50.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2815]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_51.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2824]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_52.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2833]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_53.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2842]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_54.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2851]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_55.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2860]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_56.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2869]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_57.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2878]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_58.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2887]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_59.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2896]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_60.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2905]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_61.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2914]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_62.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2923]
INFO: [Synth 8-3876] $readmem data file 'synthRvFftFtn.v_toplevel_core_core0_core_core1_core_twiddleFactorROMs_63.bin' is read successfully [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:2932]
INFO: [Synth 8-6157] synthesizing module 'matintrlv_r64_c8_w36_sw64_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/matintrlv_r64_c8_w36_sw64_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_91' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_91.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_91' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_91.v:6]
INFO: [Synth 8-6155] done synthesizing module 'matintrlv_r64_c8_w36_sw64_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/matintrlv_r64_c8_w36_sw64_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'matintrlv_r8_c64_w36_sw64_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/matintrlv_r8_c64_w36_sw64_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_92' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_92.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_92' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_92.v:6]
INFO: [Synth 8-6155] done synthesizing module 'matintrlv_r8_c64_w36_sw64_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/matintrlv_r8_c64_w36_sw64_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'fft_n64_factors_8_8_scales_2_2_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/fft_n64_factors_8_8_scales_2_2_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_94' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_94.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_3' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_3.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_3' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_3.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_11' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_11.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_11' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_11.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_20' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_20.v:6]
INFO: [Synth 8-6157] synthesizing module 'ComplexMult' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:6]
INFO: [Synth 8-6155] done synthesizing module 'ComplexMult' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_20' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_20.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_21' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_21.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_21' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_21.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_22' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_22.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_22' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_22.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_23' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_23.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_23' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_23.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_24' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_24.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_24' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_24.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_25' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_25.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_25' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_25.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_26' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_26.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_26' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_26.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_31' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_31.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_31' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_31.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_32' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_32.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_32' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_32.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_33' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_33.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_33' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_33.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_34' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_34.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_34' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_34.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_38' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_38.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_38' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_38.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_40' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_40.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_40' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_40.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_41' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_41.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_41' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_41.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_42' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_42.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_42' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_42.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_47' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_47.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_47' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_47.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_48' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_48.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_48' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_48.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_49' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_49.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_49' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_49.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_50' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_50.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_50' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_50.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_56' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_56.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_56' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_56.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_57' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_57.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_57' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_57.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_58' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_58.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_58' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_58.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_65' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_65.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_65' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_65.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_66' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_66.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_66' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_66.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_74' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_74.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_74' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_74.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_94' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_94.v:6]
INFO: [Synth 8-6155] done synthesizing module 'fft_n64_factors_8_8_scales_2_2_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/fft_n64_factors_8_8_scales_2_2_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'fft_n8_factors_8_scales_1_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/fft_n8_factors_8_scales_1_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed_95' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_95.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_95' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_95.v:6]
INFO: [Synth 8-6155] done synthesizing module 'fft_n8_factors_8_scales_1_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/fft_n8_factors_8_scales_1_dut.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_104' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_104.v:6]
INFO: [Synth 8-6155] done synthesizing module 'fft_n512_sw64_factors_8_8_8_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/fft_n512_sw64_factors_8_8_8_dut.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_105' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_105.v:6]
INFO: [Synth 8-6155] done synthesizing module 'rvFftPre_fft_n512_sw64_factors_8_8_8_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/rvFftPre_fft_n512_sw64_factors_8_8_8_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'rvFftPost_dut' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/rvFftPost_dut.v:6]
INFO: [Synth 8-6157] synthesizing module 'anon_1' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon_1.v:6]
INFO: [Synth 8-6155] done synthesizing module 'anon_1' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon_1.v:6]
INFO: [Synth 8-6155] done synthesizing module 'rvFftPost_dut' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/rvFftPost_dut.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed_106' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_106.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthRvFftFtn' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/synthRvFftFtn.v:6]
WARNING: [Synth 8-6014] Unused sequential element part0_0_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:4551]
WARNING: [Synth 8-6014] Unused sequential element part0_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:4552]
WARNING: [Synth 8-6014] Unused sequential element part0_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:4553]
WARNING: [Synth 8-6014] Unused sequential element part0_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:4554]
WARNING: [Synth 8-6014] Unused sequential element part0_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:4555]
WARNING: [Synth 8-6014] Unused sequential element part0_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:4556]
WARNING: [Synth 8-6014] Unused sequential element part0_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:4557]
WARNING: [Synth 8-6014] Unused sequential element part0_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:4558]
WARNING: [Synth 8-3848] Net p2s_validIn in module/entity anon does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/anon.v:337]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1401]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1402]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1403]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1404]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1405]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1406]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1407]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1408]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1412]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1413]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1414]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1415]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1416]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1417]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1418]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1419]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1423]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1424]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1425]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1426]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1427]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1428]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1429]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1430]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1434]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1435]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1436]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1437]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1438]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1439]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1440]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1441]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1445]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1446]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1447]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1448]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1449]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1450]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1451]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1452]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1456]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1457]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1458]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1459]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1460]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1461]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1462]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1463]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1467]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1468]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1469]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1470]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1471]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1472]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1473]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1474]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1489]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1490]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1491]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1492]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1493]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1494]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1495]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1496]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1500]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1501]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1502]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1503]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1504]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1505]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1506]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1507]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1511]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1512]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1513]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1514]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1515]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1516]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1517]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1518]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1522]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1523]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1524]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1525]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1526]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1527]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1528]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1529]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1533]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1534]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1535]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed.v:1536]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3848] Net core_validIn in module/entity synthRvFftFtn does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/synthRvFftFtn.v:209]
WARNING: [Synth 8-7129] Port validIn in module anon_1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module ComplexMult is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_49 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_47 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_31 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_103 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module anon is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module synthRvFftFtn is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 5816.199 ; gain = 540.668 ; free physical = 34786 ; free virtual = 71276
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 5831.043 ; gain = 555.512 ; free physical = 34577 ; free virtual = 71067
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 5831.043 ; gain = 555.512 ; free physical = 34577 ; free virtual = 71067
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 5840.309 ; gain = 0.000 ; free physical = 35592 ; free virtual = 72082
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 6259.730 ; gain = 0.000 ; free physical = 35256 ; free virtual = 71746
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 6331.730 ; gain = 72.000 ; free physical = 35240 ; free virtual = 71729
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 6331.730 ; gain = 1056.199 ; free physical = 35714 ; free virtual = 72203
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 6331.730 ; gain = 1056.199 ; free physical = 35714 ; free virtual = 72203
---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 6331.730 ; gain = 1056.199 ; free physical = 35714 ; free virtual = 72203
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INFO: [Synth 8-6904] The RAM "unamed_103:/_zz_14_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed_103:/_zz_12_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_0_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_1_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_2_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_3_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_4_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_5_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_6_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_7_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:39 ; elapsed = 00:00:35 . Memory (MB): peak = 6331.730 ; gain = 1056.199 ; free physical = 35771 ; free virtual = 72264
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Start RTL Component Statistics
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Detailed RTL Component Info :
+---Adders :
2 Input 18 Bit Adders := 680
3 Input 18 Bit Adders := 888
2 Input 3 Bit Adders := 10
2 Input 2 Bit Adders := 2
2 Input 1 Bit Adders := 1
+---Registers :
2304 Bit Registers := 2
288 Bit Registers := 72
32 Bit Registers := 64
18 Bit Registers := 5292
16 Bit Registers := 648
3 Bit Registers := 32
1 Bit Registers := 361
+---RAMs :
9K Bit (4 X 2304 bit) RAMs := 2
4K Bit (16 X 288 bit) RAMs := 24
+---Muxes :
8 Input 288 Bit Muxes := 24
2 Input 36 Bit Muxes := 64
9 Input 32 Bit Muxes := 64
4 Input 18 Bit Muxes := 128
2 Input 18 Bit Muxes := 128
5 Input 18 Bit Muxes := 128
2 Input 3 Bit Muxes := 33
2 Input 2 Bit Muxes := 2
5 Input 2 Bit Muxes := 128
2 Input 1 Bit Muxes := 5
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Finished RTL Component Statistics
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Start Part Resource Summary
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Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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INFO: [Synth 8-6904] The RAM "synthRvFftFtn/rams_7_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthRvFftFtn/rams_0_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_1_imag_5_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_3.v:179]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_1_real_15_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_3.v:181]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_1_imag_10_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_3.v:182]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_1_real_10_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_3.v:180]
DSP Report: Generating DSP _zz_ret_1_real_15_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_1_real_14_reg is absorbed into DSP _zz_ret_1_real_15_reg.
DSP Report: register _zz_ret_1_real_15_reg is absorbed into DSP _zz_ret_1_real_15_reg.
DSP Report: operator _zz_ret_1_real_150 is absorbed into DSP _zz_ret_1_real_15_reg.
DSP Report: Generating DSP _zz_ret_1_real_10_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_1_real_9_reg is absorbed into DSP _zz_ret_1_real_10_reg.
DSP Report: register _zz_ret_1_real_10_reg is absorbed into DSP _zz_ret_1_real_10_reg.
DSP Report: operator _zz_ret_1_real_100 is absorbed into DSP _zz_ret_1_real_10_reg.
DSP Report: Generating DSP _zz_ret_1_imag_10_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_1_imag_9_reg is absorbed into DSP _zz_ret_1_imag_10_reg.
DSP Report: register _zz_ret_1_imag_10_reg is absorbed into DSP _zz_ret_1_imag_10_reg.
DSP Report: operator _zz_ret_1_imag_100 is absorbed into DSP _zz_ret_1_imag_10_reg.
DSP Report: Generating DSP _zz_ret_1_imag_5_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_1_imag_4_reg is absorbed into DSP _zz_ret_1_imag_5_reg.
DSP Report: register _zz_ret_1_imag_5_reg is absorbed into DSP _zz_ret_1_imag_5_reg.
DSP Report: operator _zz_ret_1_imag_50 is absorbed into DSP _zz_ret_1_imag_5_reg.
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_124/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_125/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_126/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_127/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_128/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/_zz_ret_imag_1_reg' and it is trimmed from '34' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_31.v:42]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/_zz_ret_real_4_reg' and it is trimmed from '34' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/unamed_31.v:41]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_136/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_140/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_140/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_140/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:62]
INFO: [Common 17-14] Message 'Synth 8-3936' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
DSP Report: Generating DSP unamed_124/complexMult_108/mid_reg, operation Mode is: (((D:0x3fb1)'+(A:0xf9bb)')*B'')'.
DSP Report: register unamed_124/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/arD1_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/mid_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_mid0 is absorbed into DSP unamed_124/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_124/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_124/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/aiD2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_124/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_124/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_124/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_124/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_124/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_124/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_125/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xf384)')*B'')'.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/arD1_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/mid_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_mid0 is absorbed into DSP unamed_125/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_125/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_125/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/aiD2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_125/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_125/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_125/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_125/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_126/complexMult_108/mid_reg, operation Mode is: (((D:0x3d3e)'+(A:0xed6c)')*B'')'.
DSP Report: register unamed_126/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/arD1_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/mid_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_mid0 is absorbed into DSP unamed_126/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_126/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_126/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/aiD2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_126/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_126/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_126/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_126/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_127/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0xe783)')*B'')'.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/arD1_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/mid_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_127/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_127/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_127/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/aiD2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_127/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_127/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_127/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_127/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_128/complexMult_108/mid_reg, operation Mode is: (((D:0x3871)'+(A:0xe1d5)')*B'')'.
DSP Report: register unamed_128/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/arD1_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/mid_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_mid0 is absorbed into DSP unamed_128/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_128/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_128/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/aiD2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_128/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_128/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_128/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_128/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_129/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0xdc72)')*B'')'.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/arD1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/mid_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_129/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_129/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/aiD2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_129/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_129/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/mid_reg, operation Mode is: (((D:0x3179)'+(A:0xd767)')*B'')'.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/arD1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/mid_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_130/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/aiD2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_130/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xf384)')*B'')'.
DSP Report: register unamed_132/complexMult_108/arD1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/mid_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: operator unamed_125/complexMult_108/_zz_mid0 is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_132/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/aiD2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_132/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0xe783)')*B'')'.
DSP Report: register unamed_133/complexMult_108/arD1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/mid_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_133/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/aiD2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_133/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0xdc72)')*B'')'.
DSP Report: register unamed_134/complexMult_108/arD1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/mid_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_134/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/aiD2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_134/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_135/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_135/_zz_ret_real_1_reg is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: register unamed_135/_zz_ret_real_reg is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: register unamed_135/_zz_ret_real_4_reg is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: register unamed_135/_zz_ret_real_3_reg is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: operator unamed_135/_zz_ret_real_40 is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: operator unamed_135/_zz_ret_real_30 is absorbed into DSP unamed_135/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_135/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_135/_zz_ret_real_1_reg is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: register unamed_135/_zz_ret_imag_1_reg is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: register unamed_135/_zz_ret_imag_1_reg is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: register unamed_135/_zz_ret_imag_reg is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: operator unamed_135/_zz_ret_imag_10 is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: operator unamed_135/_zz_ret_imag0 is absorbed into DSP unamed_135/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_136/complexMult_108/mid_reg, operation Mode is: (((D:0x238e)'+(A:0xcaca)')*B'')'.
DSP Report: register unamed_136/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/arD1_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/mid_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_mid0 is absorbed into DSP unamed_136/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_136/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_136/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/aiD2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_136/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_136/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_136/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_136/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/mid_reg, operation Mode is: (((D:0x187d)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_137/complexMult_108/arD1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/mid_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_mid0 is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_137/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/aiD2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_137/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/mid_reg, operation Mode is: (((D:0xc7c)'+(A:0xc13b)')*B'')'.
DSP Report: register unamed_138/complexMult_108/arD1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/mid_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_mid0 is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_138/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/aiD2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_138/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_140/complexMult_108/mid_reg, operation Mode is: (((D:0x3d3e)'+(A:0xed6c)')*B'')'.
DSP Report: register unamed_140/complexMult_108/arD1_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_140/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_140/complexMult_108/mid_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_140/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: register unamed_126/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: operator unamed_126/complexMult_108/_zz_mid0 is absorbed into DSP unamed_140/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_140/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_140/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/aiD2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_126/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_140/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_140/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_140/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_126/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_140/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_140/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_140/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0xdc72)')*B'')'.
DSP Report: register unamed_141/complexMult_108/arD1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/mid_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_141/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/aiD2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_141/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_160/complexMult_108/mid_reg, operation Mode is: (((D:0xce87)'+(A:0xd767)')*B'')'.
DSP Report: register unamed_160/complexMult_108/arD1_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/mid_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: register unamed_160/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_mid0 is absorbed into DSP unamed_160/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_160/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_160/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_160/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/mid_reg, operation Mode is: (((D:0x2899)'+(A:0xce87)')*B'')'.
DSP Report: register unamed_142/complexMult_108/arD1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/mid_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_mid0 is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_142/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_142/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/mid_reg, operation Mode is: (((D:0x187d)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_143/complexMult_108/arD1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/mid_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_mid0 is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_143/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/aiD2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_143/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_144/complexMult_108/mid_reg, operation Mode is: (((D:0x645)'+(A:0xc04f)')*B'')'.
DSP Report: register unamed_144/complexMult_108/arD1_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/mid_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_mid0 is absorbed into DSP unamed_144/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_144/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_144/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/aiD2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_144/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_144/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_144/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_144/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/mid_reg, operation Mode is: (((D:0xf384)'+(A:0xc13b)')*B'')'.
DSP Report: register unamed_145/complexMult_108/arD1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/mid_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid0 is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_145/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_145/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/mid_reg, operation Mode is: (((D:0xe1d5)'+(A:0xc78f)')*B'')'.
DSP Report: register unamed_146/complexMult_108/arD1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/mid_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_mid0 is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_146/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/aiD2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_146/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0xe783)')*B'')'.
DSP Report: register unamed_148/complexMult_108/arD1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/mid_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: operator unamed_127/complexMult_108/_zz_mid0 is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_148/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/aiD2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_148/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_149/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_149/_zz_ret_real_1_reg is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: register unamed_149/_zz_ret_real_reg is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: register unamed_149/_zz_ret_real_4_reg is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: register unamed_149/_zz_ret_real_3_reg is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: operator unamed_149/_zz_ret_real_40 is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: operator unamed_149/_zz_ret_real_30 is absorbed into DSP unamed_149/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_149/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_149/_zz_ret_real_1_reg is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: register unamed_149/_zz_ret_imag_1_reg is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: register unamed_149/_zz_ret_imag_1_reg is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: register unamed_149/_zz_ret_imag_reg is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: operator unamed_149/_zz_ret_imag_10 is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: operator unamed_149/_zz_ret_imag0 is absorbed into DSP unamed_149/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/mid_reg, operation Mode is: (((D:0x187d)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_150/complexMult_108/arD1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/mid_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_mid0 is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_150/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/aiD2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_150/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_152/complexMult_108/mid_reg, operation Mode is: (((D:0xe783)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_152/complexMult_108/arD1_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/mid_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_mid0 is absorbed into DSP unamed_152/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_152/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_152/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/aiD2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_152/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_152/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_152/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_152/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_152/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_153/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_153/_zz_ret_real_1_reg is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: register unamed_153/_zz_ret_real_reg is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: register unamed_153/_zz_ret_real_4_reg is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: register unamed_153/_zz_ret_real_3_reg is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: operator unamed_153/_zz_ret_real_40 is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: operator unamed_153/_zz_ret_real_30 is absorbed into DSP unamed_153/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_153/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_153/_zz_ret_real_1_reg is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: register unamed_153/_zz_ret_real_reg is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: register unamed_153/_zz_ret_imag_1_reg is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: register unamed_153/_zz_ret_imag_reg is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: operator unamed_153/_zz_ret_imag_10 is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: operator unamed_153/_zz_ret_imag0 is absorbed into DSP unamed_153/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_154/complexMult_108/mid_reg, operation Mode is: (((D:0xe783)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_154/complexMult_108/arD1_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/mid_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_154/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_mid0 is absorbed into DSP unamed_154/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_154/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_154/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_154/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_154/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_154/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_154/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_154/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_154/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_156/complexMult_108/mid_reg, operation Mode is: (((D:0x3871)'+(A:0xe1d5)')*B'')'.
DSP Report: register unamed_156/complexMult_108/arD1_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_156/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_156/complexMult_108/mid_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_156/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: operator unamed_128/complexMult_108/_zz_mid0 is absorbed into DSP unamed_156/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_156/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_156/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/aiD2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_156/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_156/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_156/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_156/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_156/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_156/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/mid_reg, operation Mode is: (((D:0x238e)'+(A:0xcaca)')*B'')'.
DSP Report: register unamed_157/complexMult_108/arD1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/mid_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_136/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: operator unamed_136/complexMult_108/_zz_mid0 is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_157/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/aiD2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_136/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_157/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_136/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_158/complexMult_108/mid_reg, operation Mode is: (((D:0x645)'+(A:0xc04f)')*B'')'.
DSP Report: register unamed_158/complexMult_108/arD1_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_158/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_158/complexMult_108/mid_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_158/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: operator unamed_144/complexMult_108/_zz_mid0 is absorbed into DSP unamed_158/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_158/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_158/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/aiD2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_144/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_158/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_158/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_158/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_158/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_158/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_158/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/mid_reg, operation Mode is: (((D:0xe783)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_159/complexMult_108/arD1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/mid_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_mid0 is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_159/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/aiD2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_159/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_160/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_160/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_160/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_160/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_160/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/mid_reg, operation Mode is: (((D:0xf384)'+(A:0xc13b)')*B'')'.
DSP Report: register unamed_161/complexMult_108/arD1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/mid_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid0 is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_161/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/aiD2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_161/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/mid_reg, operation Mode is: (((D:0xc2c2)'+(A:0x1294)')*B'')'.
DSP Report: register unamed_162/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/arD1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/mid_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_mid0 is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_162/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/aiD2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_162/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0xdc72)')*B'')'.
DSP Report: register unamed_164/complexMult_108/arD1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/mid_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_164/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/aiD2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_164/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/mid_reg, operation Mode is: (((D:0x187d)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_165/complexMult_108/arD1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/mid_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_mid0 is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_165/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/aiD2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_165/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/mid_reg, operation Mode is: (((D:0xf384)'+(A:0xc13b)')*B'')'.
DSP Report: register unamed_166/complexMult_108/arD1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/mid_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid0 is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_166/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_166/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_167/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_167/_zz_ret_real_1_reg is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: register unamed_167/_zz_ret_real_reg is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: register unamed_167/_zz_ret_real_4_reg is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: register unamed_167/_zz_ret_real_3_reg is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: operator unamed_167/_zz_ret_real_40 is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: operator unamed_167/_zz_ret_real_30 is absorbed into DSP unamed_167/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_167/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_167/_zz_ret_real_1_reg is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: register unamed_167/_zz_ret_real_reg is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: register unamed_167/_zz_ret_imag_1_reg is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: register unamed_167/_zz_ret_imag_reg is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: operator unamed_167/_zz_ret_imag_10 is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: operator unamed_167/_zz_ret_imag0 is absorbed into DSP unamed_167/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_168/complexMult_108/mid_reg, operation Mode is: (((D:0xf384)'+(A:0xc13b)')*B'')'.
DSP Report: register unamed_168/complexMult_108/arD1_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_168/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_125/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_168/complexMult_108/mid_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_168/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid0 is absorbed into DSP unamed_168/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_168/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_168/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/aiD2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_125/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_168/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_168/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_168/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_168/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_168/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_168/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/mid_reg, operation Mode is: (((D:0x187d)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_169/complexMult_108/arD1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/mid_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_mid0 is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_169/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_169/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0xdc72)')*B'')'.
DSP Report: register unamed_170/complexMult_108/arD1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/mid_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_170/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_170/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_172/complexMult_108/mid_reg, operation Mode is: (((D:0x3179)'+(A:0xd767)')*B'')'.
DSP Report: register unamed_172/complexMult_108/arD1_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_172/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_172/complexMult_108/mid_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_172/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_172/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_172/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_172/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/aiD2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_172/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_172/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_172/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_172/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_172/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_172/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/mid_reg, operation Mode is: (((D:0xc7c)'+(A:0xc13b)')*B'')'.
DSP Report: register unamed_173/complexMult_108/arD1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/mid_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_mid0 is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_173/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/aiD2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_173/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/mid_reg, operation Mode is: (((D:0xe1d5)'+(A:0xc78f)')*B'')'.
DSP Report: register unamed_174/complexMult_108/arD1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_128/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/mid_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_mid0 is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_174/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_174/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_128/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/mid_reg, operation Mode is: (((D:0xe783)'+(A:0xc4e0)')*B'')'.
DSP Report: register unamed_175/complexMult_108/arD1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_127/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/mid_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_152/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: operator unamed_152/complexMult_108/_zz_mid0 is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_175/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_127/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_175/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_176/complexMult_108/mid_reg, operation Mode is: (((D:0xc2c2)'+(A:0x1294)')*B'')'.
DSP Report: register unamed_176/complexMult_108/arD1_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_176/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_176/complexMult_108/mid_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_176/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_mid0 is absorbed into DSP unamed_176/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_176/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_176/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/aiD2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_176/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_176/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_176/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_176/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_176/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_176/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0xdc72)')*B'')'.
DSP Report: register unamed_177/complexMult_108/arD1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/mid_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_177/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_177/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/mid_reg, operation Mode is: (((D:0x645)'+(A:0x3fb1)')*B'')'.
DSP Report: register unamed_178/complexMult_108/arD1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_124/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_144/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/mid_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_mid0 is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_178/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/aiD2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_178/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_144/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
WARNING: [Synth 8-7129] Port validIn in module synthRvFftFtn is either unconnected or has no load
INFO: [Synth 8-6904] The RAM "synthRvFftFtn/rams_7_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "synthRvFftFtn/rams_0_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_3_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_4_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_5_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_6_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_1_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_2_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_3_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_4_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_5_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_6_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_1_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_2_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-4471] merging register 'complexMult_108/coeff_imag_delay_1_reg[15:0]' into 'complexMult_108/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_109/coeff_imag_delay_1_reg[15:0]' into 'complexMult_109/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_110/coeff_imag_delay_1_reg[15:0]' into 'complexMult_110/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_111/coeff_imag_delay_1_reg[15:0]' into 'complexMult_111/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_112/coeff_imag_delay_1_reg[15:0]' into 'complexMult_112/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_113/coeff_imag_delay_1_reg[15:0]' into 'complexMult_113/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_114/coeff_imag_delay_1_reg[15:0]' into 'complexMult_114/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_115/coeff_imag_delay_1_reg[15:0]' into 'complexMult_115/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_116/coeff_imag_delay_1_reg[15:0]' into 'complexMult_116/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_117/coeff_imag_delay_1_reg[15:0]' into 'complexMult_117/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_118/coeff_imag_delay_1_reg[15:0]' into 'complexMult_118/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_119/coeff_imag_delay_1_reg[15:0]' into 'complexMult_119/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_120/coeff_imag_delay_1_reg[15:0]' into 'complexMult_120/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_121/coeff_imag_delay_1_reg[15:0]' into 'complexMult_121/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_122/coeff_imag_delay_1_reg[15:0]' into 'complexMult_122/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_123/coeff_imag_delay_1_reg[15:0]' into 'complexMult_123/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_124/coeff_imag_delay_1_reg[15:0]' into 'complexMult_124/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_125/coeff_imag_delay_1_reg[15:0]' into 'complexMult_125/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_126/coeff_imag_delay_1_reg[15:0]' into 'complexMult_126/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_127/coeff_imag_delay_1_reg[15:0]' into 'complexMult_127/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_128/coeff_imag_delay_1_reg[15:0]' into 'complexMult_128/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_129/coeff_imag_delay_1_reg[15:0]' into 'complexMult_129/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_130/coeff_imag_delay_1_reg[15:0]' into 'complexMult_130/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_131/coeff_imag_delay_1_reg[15:0]' into 'complexMult_131/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_132/coeff_imag_delay_1_reg[15:0]' into 'complexMult_132/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_133/coeff_imag_delay_1_reg[15:0]' into 'complexMult_133/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_134/coeff_imag_delay_1_reg[15:0]' into 'complexMult_134/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_135/coeff_imag_delay_1_reg[15:0]' into 'complexMult_135/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_136/coeff_imag_delay_1_reg[15:0]' into 'complexMult_136/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_137/coeff_imag_delay_1_reg[15:0]' into 'complexMult_137/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_138/coeff_imag_delay_1_reg[15:0]' into 'complexMult_138/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_139/coeff_imag_delay_1_reg[15:0]' into 'complexMult_139/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_140/coeff_imag_delay_1_reg[15:0]' into 'complexMult_140/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_141/coeff_imag_delay_1_reg[15:0]' into 'complexMult_141/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_142/coeff_imag_delay_1_reg[15:0]' into 'complexMult_142/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_143/coeff_imag_delay_1_reg[15:0]' into 'complexMult_143/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_144/coeff_imag_delay_1_reg[15:0]' into 'complexMult_144/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_145/coeff_imag_delay_1_reg[15:0]' into 'complexMult_145/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_146/coeff_imag_delay_1_reg[15:0]' into 'complexMult_146/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_147/coeff_imag_delay_1_reg[15:0]' into 'complexMult_147/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_148/coeff_imag_delay_1_reg[15:0]' into 'complexMult_148/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_149/coeff_imag_delay_1_reg[15:0]' into 'complexMult_149/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_150/coeff_imag_delay_1_reg[15:0]' into 'complexMult_150/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_151/coeff_imag_delay_1_reg[15:0]' into 'complexMult_151/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_152/coeff_imag_delay_1_reg[15:0]' into 'complexMult_152/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_153/coeff_imag_delay_1_reg[15:0]' into 'complexMult_153/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_154/coeff_imag_delay_1_reg[15:0]' into 'complexMult_154/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_155/coeff_imag_delay_1_reg[15:0]' into 'complexMult_155/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_156/coeff_imag_delay_1_reg[15:0]' into 'complexMult_156/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_157/coeff_imag_delay_1_reg[15:0]' into 'complexMult_157/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_158/coeff_imag_delay_1_reg[15:0]' into 'complexMult_158/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_159/coeff_imag_delay_1_reg[15:0]' into 'complexMult_159/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_160/coeff_imag_delay_1_reg[15:0]' into 'complexMult_160/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_161/coeff_imag_delay_1_reg[15:0]' into 'complexMult_161/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_162/coeff_imag_delay_1_reg[15:0]' into 'complexMult_162/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_163/coeff_imag_delay_1_reg[15:0]' into 'complexMult_163/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_164/coeff_imag_delay_1_reg[15:0]' into 'complexMult_164/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_165/coeff_imag_delay_1_reg[15:0]' into 'complexMult_165/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_166/coeff_imag_delay_1_reg[15:0]' into 'complexMult_166/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_167/coeff_imag_delay_1_reg[15:0]' into 'complexMult_167/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_168/coeff_imag_delay_1_reg[15:0]' into 'complexMult_168/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_169/coeff_imag_delay_1_reg[15:0]' into 'complexMult_169/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_170/coeff_imag_delay_1_reg[15:0]' into 'complexMult_170/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_171/coeff_imag_delay_1_reg[15:0]' into 'complexMult_171/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_108/arD1_reg[17:0]' into 'complexMult_108/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_108/mid_delay_1_reg[34:0]' into 'complexMult_108/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_109/arD1_reg[17:0]' into 'complexMult_109/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_109/mid_delay_1_reg[34:0]' into 'complexMult_109/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_110/arD1_reg[17:0]' into 'complexMult_110/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_110/mid_delay_1_reg[34:0]' into 'complexMult_110/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_111/arD1_reg[17:0]' into 'complexMult_111/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_111/mid_delay_1_reg[34:0]' into 'complexMult_111/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_112/arD1_reg[17:0]' into 'complexMult_112/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_112/mid_delay_1_reg[34:0]' into 'complexMult_112/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_113/arD1_reg[17:0]' into 'complexMult_113/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_113/mid_delay_1_reg[34:0]' into 'complexMult_113/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_114/arD1_reg[17:0]' into 'complexMult_114/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_114/mid_delay_1_reg[34:0]' into 'complexMult_114/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_115/arD1_reg[17:0]' into 'complexMult_115/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_115/mid_delay_1_reg[34:0]' into 'complexMult_115/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_116/arD1_reg[17:0]' into 'complexMult_116/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_116/mid_delay_1_reg[34:0]' into 'complexMult_116/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_117/arD1_reg[17:0]' into 'complexMult_117/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_117/mid_delay_1_reg[34:0]' into 'complexMult_117/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_118/arD1_reg[17:0]' into 'complexMult_118/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_118/mid_delay_1_reg[34:0]' into 'complexMult_118/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_119/arD1_reg[17:0]' into 'complexMult_119/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_119/mid_delay_1_reg[34:0]' into 'complexMult_119/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_120/arD1_reg[17:0]' into 'complexMult_120/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_120/mid_delay_1_reg[34:0]' into 'complexMult_120/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_121/arD1_reg[17:0]' into 'complexMult_121/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_121/mid_delay_1_reg[34:0]' into 'complexMult_121/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_122/arD1_reg[17:0]' into 'complexMult_122/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_122/mid_delay_1_reg[34:0]' into 'complexMult_122/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_123/arD1_reg[17:0]' into 'complexMult_123/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_123/mid_delay_1_reg[34:0]' into 'complexMult_123/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_124/arD1_reg[17:0]' into 'complexMult_124/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_124/mid_delay_1_reg[34:0]' into 'complexMult_124/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_125/arD1_reg[17:0]' into 'complexMult_125/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_125/mid_delay_1_reg[34:0]' into 'complexMult_125/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftFtn/ComplexMult.v:79]
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3936' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
DSP Report: Generating DSP complexMult_108/mid_reg, operation Mode is: ((D'+(A:0x4000)'')*B'')'.
DSP Report: register complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/arD1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/data_real_delay_2_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_0_port0_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/coeff_real_delay_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/mid_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/_zz_mid_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/_zz_mid_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: operator complexMult_108/_zz_mid_10 is absorbed into DSP complexMult_108/mid_reg.
DSP Report: operator complexMult_108/_zz_mid0 is absorbed into DSP complexMult_108/mid_reg.
DSP Report: Generating DSP complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_108/biD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/biD2_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/data_real_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/arD1_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/mid_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/aiD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real_20 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real_10 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real0 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_108/aiD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/mid_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/brD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/brD2_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/arD1_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag_20 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag_10 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag0 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_109/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_109/coeff_imag_delay_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/arD1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/data_real_delay_2_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_1_port0_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/coeff_real_delay_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/mid_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/_zz_mid_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/_zz_mid_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: operator complexMult_109/_zz_mid_10 is absorbed into DSP complexMult_109/mid_reg.
DSP Report: operator complexMult_109/_zz_mid0 is absorbed into DSP complexMult_109/mid_reg.
DSP Report: Generating DSP complexMult_109/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_109/biD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/biD2_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/data_real_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/arD1_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/mid_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/aiD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real_20 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real_10 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real0 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_109/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_109/aiD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/mid_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/brD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/brD2_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/arD1_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag_20 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag_10 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag0 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_110/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_110/coeff_imag_delay_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/arD1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/data_real_delay_2_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_2_port0_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/coeff_real_delay_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/mid_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/_zz_mid_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/_zz_mid_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: operator complexMult_110/_zz_mid_10 is absorbed into DSP complexMult_110/mid_reg.
DSP Report: operator complexMult_110/_zz_mid0 is absorbed into DSP complexMult_110/mid_reg.
DSP Report: Generating DSP complexMult_110/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_110/biD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/biD2_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/data_real_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/arD1_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/mid_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/aiD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real_20 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real_10 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real0 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_110/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_110/aiD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/mid_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/brD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/brD2_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/arD1_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag_20 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag_10 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag0 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_111/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_111/coeff_imag_delay_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/arD1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/data_real_delay_2_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_3_port0_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/coeff_real_delay_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/mid_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/_zz_mid_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/_zz_mid_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: operator complexMult_111/_zz_mid_10 is absorbed into DSP complexMult_111/mid_reg.
DSP Report: operator complexMult_111/_zz_mid0 is absorbed into DSP complexMult_111/mid_reg.
DSP Report: Generating DSP complexMult_111/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_111/biD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/biD2_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/data_real_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/arD1_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/mid_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/aiD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real_20 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real_10 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real0 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_111/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_111/aiD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/mid_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/brD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/brD2_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/arD1_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag_20 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag_10 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag0 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_112/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_112/coeff_imag_delay_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/arD1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/data_real_delay_2_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_4_port0_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/coeff_real_delay_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/mid_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/_zz_mid_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/_zz_mid_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: operator complexMult_112/_zz_mid_10 is absorbed into DSP complexMult_112/mid_reg.
DSP Report: operator complexMult_112/_zz_mid0 is absorbed into DSP complexMult_112/mid_reg.
DSP Report: Generating DSP complexMult_112/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_112/biD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/biD2_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/data_real_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/arD1_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/mid_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/aiD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real_20 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real_10 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real0 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_112/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_112/aiD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/mid_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/brD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/brD2_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/arD1_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag_20 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag_10 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag0 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_113/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_113/coeff_imag_delay_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/arD1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/data_real_delay_2_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_5_port0_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/coeff_real_delay_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/mid_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/_zz_mid_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/_zz_mid_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: operator complexMult_113/_zz_mid_10 is absorbed into DSP complexMult_113/mid_reg.
DSP Report: operator complexMult_113/_zz_mid0 is absorbed into DSP complexMult_113/mid_reg.
DSP Report: Generating DSP complexMult_113/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_113/biD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/biD2_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/data_real_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/arD1_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/mid_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/aiD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real_20 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real_10 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real0 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_113/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_113/aiD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/mid_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/brD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/brD2_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/arD1_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag_20 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag_10 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag0 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_114/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_114/coeff_imag_delay_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/arD1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/data_real_delay_2_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_6_port0_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/coeff_real_delay_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/mid_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/_zz_mid_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/_zz_mid_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: operator complexMult_114/_zz_mid_10 is absorbed into DSP complexMult_114/mid_reg.
DSP Report: operator complexMult_114/_zz_mid0 is absorbed into DSP complexMult_114/mid_reg.
DSP Report: Generating DSP complexMult_114/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_114/biD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/biD2_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/data_real_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/arD1_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/mid_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/aiD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real_20 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real_10 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real0 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_114/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_114/aiD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/mid_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/brD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/brD2_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/arD1_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag_20 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag_10 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag0 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_115/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_115/coeff_imag_delay_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/arD1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/data_real_delay_2_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_7_port0_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/coeff_real_delay_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/mid_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/_zz_mid_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/_zz_mid_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: operator complexMult_115/_zz_mid_10 is absorbed into DSP complexMult_115/mid_reg.
DSP Report: operator complexMult_115/_zz_mid0 is absorbed into DSP complexMult_115/mid_reg.
DSP Report: Generating DSP complexMult_115/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_115/biD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/biD2_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/data_real_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/arD1_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/mid_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/aiD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real_20 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real_10 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real0 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_115/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_115/aiD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/mid_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/brD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/brD2_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/arD1_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag_20 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag_10 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag0 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_116/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_116/coeff_imag_delay_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/arD1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/data_real_delay_2_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_8_port0_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/coeff_real_delay_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/mid_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/_zz_mid_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/_zz_mid_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: operator complexMult_116/_zz_mid_10 is absorbed into DSP complexMult_116/mid_reg.
DSP Report: operator complexMult_116/_zz_mid0 is absorbed into DSP complexMult_116/mid_reg.
DSP Report: Generating DSP complexMult_116/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_116/biD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/biD2_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/data_real_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/arD1_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/mid_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/aiD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real_20 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real_10 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real0 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_116/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_116/aiD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/mid_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/brD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/brD2_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/arD1_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag_20 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag_10 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag0 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_117/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_117/coeff_imag_delay_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/arD1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/data_real_delay_2_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_9_port0_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/coeff_real_delay_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/mid_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/_zz_mid_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/_zz_mid_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: operator complexMult_117/_zz_mid_10 is absorbed into DSP complexMult_117/mid_reg.
DSP Report: operator complexMult_117/_zz_mid0 is absorbed into DSP complexMult_117/mid_reg.
DSP Report: Generating DSP complexMult_117/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_117/biD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/biD2_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/data_real_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/arD1_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/mid_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/aiD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real_20 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real_10 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real0 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_117/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_117/aiD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/mid_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/brD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/brD2_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/arD1_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag_20 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag_10 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag0 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_118/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_118/coeff_imag_delay_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/arD1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/data_real_delay_2_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_10_port0_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/coeff_real_delay_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/mid_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/_zz_mid_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/_zz_mid_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: operator complexMult_118/_zz_mid_10 is absorbed into DSP complexMult_118/mid_reg.
DSP Report: operator complexMult_118/_zz_mid0 is absorbed into DSP complexMult_118/mid_reg.
DSP Report: Generating DSP complexMult_118/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_118/biD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/biD2_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/data_real_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/arD1_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/mid_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/aiD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real_20 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real_10 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real0 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_118/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_118/aiD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/mid_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/brD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/brD2_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/arD1_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag_20 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag_10 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag0 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_119/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_119/coeff_imag_delay_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/arD1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/data_real_delay_2_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_11_port0_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/coeff_real_delay_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/mid_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/_zz_mid_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/_zz_mid_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: operator complexMult_119/_zz_mid_10 is absorbed into DSP complexMult_119/mid_reg.
DSP Report: operator complexMult_119/_zz_mid0 is absorbed into DSP complexMult_119/mid_reg.
DSP Report: Generating DSP complexMult_119/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_119/biD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/biD2_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/data_real_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/arD1_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/mid_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/aiD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real_20 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real_10 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real0 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_119/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_119/aiD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/mid_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/brD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/brD2_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/arD1_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag_20 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag_10 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag0 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_120/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_120/coeff_imag_delay_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/arD1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/data_real_delay_2_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_12_port0_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/coeff_real_delay_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/mid_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/_zz_mid_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/_zz_mid_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: operator complexMult_120/_zz_mid_10 is absorbed into DSP complexMult_120/mid_reg.
DSP Report: operator complexMult_120/_zz_mid0 is absorbed into DSP complexMult_120/mid_reg.
DSP Report: Generating DSP complexMult_120/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_120/biD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/biD2_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/data_real_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/arD1_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/mid_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/aiD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real_20 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real_10 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real0 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_120/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_120/aiD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/mid_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/brD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/brD2_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/arD1_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag_20 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag_10 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag0 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_121/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_121/coeff_imag_delay_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/arD1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/data_real_delay_2_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_13_port0_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/coeff_real_delay_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/mid_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/_zz_mid_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/_zz_mid_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: operator complexMult_121/_zz_mid_10 is absorbed into DSP complexMult_121/mid_reg.
DSP Report: operator complexMult_121/_zz_mid0 is absorbed into DSP complexMult_121/mid_reg.
DSP Report: Generating DSP complexMult_121/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_121/biD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/biD2_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/data_real_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/arD1_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/mid_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/aiD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real_20 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real_10 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real0 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_121/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_121/aiD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/mid_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/brD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/brD2_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/arD1_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag_20 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag_10 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag0 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_122/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_122/coeff_imag_delay_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/arD1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/data_real_delay_2_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_14_port0_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/coeff_real_delay_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/mid_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/_zz_mid_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/_zz_mid_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: operator complexMult_122/_zz_mid_10 is absorbed into DSP complexMult_122/mid_reg.
DSP Report: operator complexMult_122/_zz_mid0 is absorbed into DSP complexMult_122/mid_reg.
DSP Report: Generating DSP complexMult_122/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_122/biD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/biD2_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/data_real_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/arD1_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/mid_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/aiD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real_20 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real_10 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real0 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_122/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_122/aiD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/mid_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/brD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/brD2_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/arD1_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag_20 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag_10 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag0 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_123/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_123/coeff_imag_delay_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/arD1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/data_real_delay_2_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_15_port0_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/coeff_real_delay_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/mid_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/_zz_mid_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/_zz_mid_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: operator complexMult_123/_zz_mid_10 is absorbed into DSP complexMult_123/mid_reg.
DSP Report: operator complexMult_123/_zz_mid0 is absorbed into DSP complexMult_123/mid_reg.
DSP Report: Generating DSP complexMult_123/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_123/biD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/biD2_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/data_real_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/arD1_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/mid_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/aiD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real_20 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real_10 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real0 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_123/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_123/aiD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/mid_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/brD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/brD2_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/arD1_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag_20 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag_10 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag0 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_124/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_124/coeff_imag_delay_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/arD1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/data_real_delay_2_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_16_port0_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/coeff_real_delay_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/mid_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/_zz_mid_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/_zz_mid_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: operator complexMult_124/_zz_mid_10 is absorbed into DSP complexMult_124/mid_reg.
DSP Report: operator complexMult_124/_zz_mid0 is absorbed into DSP complexMult_124/mid_reg.
DSP Report: Generating DSP complexMult_124/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_124/biD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/biD2_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/data_real_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/arD1_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/mid_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/aiD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real_20 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real_10 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real0 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_124/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_124/aiD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/mid_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/brD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/brD2_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/arD1_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag_20 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag_10 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag0 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_125/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_125/coeff_imag_delay_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/arD1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/data_real_delay_2_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_17_port0_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/coeff_real_delay_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/mid_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/_zz_mid_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/_zz_mid_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: operator complexMult_125/_zz_mid_10 is absorbed into DSP complexMult_125/mid_reg.
DSP Report: operator complexMult_125/_zz_mid0 is absorbed into DSP complexMult_125/mid_reg.
DSP Report: Generating DSP complexMult_125/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_125/biD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/biD2_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/data_real_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/arD1_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/mid_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/aiD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real_20 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real_10 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real0 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_125/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_125/aiD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/mid_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/brD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/brD2_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/arD1_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag_20 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag_10 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag0 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_126/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_126/coeff_imag_delay_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/arD1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/data_real_delay_2_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_18_port0_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/coeff_real_delay_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/mid_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/_zz_mid_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/_zz_mid_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: operator complexMult_126/_zz_mid_10 is absorbed into DSP complexMult_126/mid_reg.
DSP Report: operator complexMult_126/_zz_mid0 is absorbed into DSP complexMult_126/mid_reg.
DSP Report: Generating DSP complexMult_126/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_126/biD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/biD2_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/data_real_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/arD1_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/mid_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/aiD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real_20 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real_10 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real0 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_126/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_126/aiD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/mid_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/brD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/brD2_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/arD1_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag_20 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag_10 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag0 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_127/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_127/coeff_imag_delay_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/arD1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/data_real_delay_2_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_19_port0_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/coeff_real_delay_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/mid_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/_zz_mid_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/_zz_mid_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: operator complexMult_127/_zz_mid_10 is absorbed into DSP complexMult_127/mid_reg.
DSP Report: operator complexMult_127/_zz_mid0 is absorbed into DSP complexMult_127/mid_reg.
DSP Report: Generating DSP complexMult_127/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_127/biD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/biD2_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/data_real_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/arD1_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/mid_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/aiD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real_20 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real_10 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real0 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_127/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_127/aiD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/mid_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/brD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/brD2_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/arD1_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag_20 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag_10 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag0 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_128/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_128/coeff_imag_delay_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/arD1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/data_real_delay_2_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_20_port0_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/coeff_real_delay_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/mid_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/_zz_mid_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/_zz_mid_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: operator complexMult_128/_zz_mid_10 is absorbed into DSP complexMult_128/mid_reg.
DSP Report: operator complexMult_128/_zz_mid0 is absorbed into DSP complexMult_128/mid_reg.
DSP Report: Generating DSP complexMult_128/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_128/biD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/biD2_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/data_real_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/arD1_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/mid_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/aiD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real_20 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real_10 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real0 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_128/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_128/aiD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/mid_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/brD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/brD2_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/arD1_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag_20 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag_10 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag0 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_129/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_129/coeff_imag_delay_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/arD1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/data_real_delay_2_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_21_port0_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/coeff_real_delay_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/mid_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/_zz_mid_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/_zz_mid_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: operator complexMult_129/_zz_mid_10 is absorbed into DSP complexMult_129/mid_reg.
DSP Report: operator complexMult_129/_zz_mid0 is absorbed into DSP complexMult_129/mid_reg.
DSP Report: Generating DSP complexMult_129/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_129/biD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/biD2_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/data_real_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/arD1_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/mid_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/aiD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real_20 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real_10 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real0 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_129/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_129/aiD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/mid_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/brD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/brD2_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/arD1_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag_20 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag_10 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag0 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_130/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_130/coeff_imag_delay_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/arD1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/data_real_delay_2_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_22_port0_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/coeff_real_delay_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/mid_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/_zz_mid_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/_zz_mid_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: operator complexMult_130/_zz_mid_10 is absorbed into DSP complexMult_130/mid_reg.
DSP Report: operator complexMult_130/_zz_mid0 is absorbed into DSP complexMult_130/mid_reg.
DSP Report: Generating DSP complexMult_130/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_130/biD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/biD2_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/data_real_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/arD1_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/mid_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/aiD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real_20 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real_10 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real0 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_130/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_130/aiD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/mid_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/brD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/brD2_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/arD1_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag_20 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag_10 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag0 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_131/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_131/coeff_imag_delay_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/arD1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/data_real_delay_2_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_23_port0_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/coeff_real_delay_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/mid_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/_zz_mid_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/_zz_mid_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: operator complexMult_131/_zz_mid_10 is absorbed into DSP complexMult_131/mid_reg.
DSP Report: operator complexMult_131/_zz_mid0 is absorbed into DSP complexMult_131/mid_reg.
DSP Report: Generating DSP complexMult_131/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_131/biD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/biD2_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/data_real_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/arD1_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/mid_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/aiD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real_20 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real_10 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real0 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_131/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_131/aiD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/mid_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/brD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/brD2_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/arD1_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag_20 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag_10 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag0 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_132/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_132/coeff_imag_delay_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/arD1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/data_real_delay_2_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_24_port0_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/coeff_real_delay_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/mid_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/_zz_mid_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/_zz_mid_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: operator complexMult_132/_zz_mid_10 is absorbed into DSP complexMult_132/mid_reg.
DSP Report: operator complexMult_132/_zz_mid0 is absorbed into DSP complexMult_132/mid_reg.
DSP Report: Generating DSP complexMult_132/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_132/biD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/biD2_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/data_real_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/arD1_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/mid_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/aiD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real_20 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real_10 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real0 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_132/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_132/aiD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/mid_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/brD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/brD2_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/arD1_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag_20 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag_10 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag0 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_133/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_133/coeff_imag_delay_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/arD1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/data_real_delay_2_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_25_port0_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/coeff_real_delay_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/mid_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/_zz_mid_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/_zz_mid_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: operator complexMult_133/_zz_mid_10 is absorbed into DSP complexMult_133/mid_reg.
DSP Report: operator complexMult_133/_zz_mid0 is absorbed into DSP complexMult_133/mid_reg.
DSP Report: Generating DSP complexMult_133/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_133/biD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/biD2_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/data_real_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/arD1_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/mid_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/aiD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real_20 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real_10 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real0 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_133/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_133/aiD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/mid_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/brD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/brD2_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/arD1_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag_20 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag_10 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag0 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_134/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_134/coeff_imag_delay_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/arD1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/data_real_delay_2_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_26_port0_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/coeff_real_delay_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/mid_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/_zz_mid_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/_zz_mid_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: operator complexMult_134/_zz_mid_10 is absorbed into DSP complexMult_134/mid_reg.
DSP Report: operator complexMult_134/_zz_mid0 is absorbed into DSP complexMult_134/mid_reg.
DSP Report: Generating DSP complexMult_134/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_134/biD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/biD2_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/data_real_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/arD1_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/mid_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/aiD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real_20 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real_10 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real0 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_134/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_134/aiD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/mid_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/brD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/brD2_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/arD1_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag_20 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag_10 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag0 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_135/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_135/coeff_imag_delay_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/arD1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/data_real_delay_2_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_27_port0_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/coeff_real_delay_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/mid_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/_zz_mid_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/_zz_mid_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: operator complexMult_135/_zz_mid_10 is absorbed into DSP complexMult_135/mid_reg.
DSP Report: operator complexMult_135/_zz_mid0 is absorbed into DSP complexMult_135/mid_reg.
DSP Report: Generating DSP complexMult_135/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_135/biD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/biD2_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/data_real_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/arD1_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/mid_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/aiD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real_20 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real_10 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real0 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_135/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_135/aiD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/mid_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/brD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/brD2_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/arD1_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag_20 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag_10 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag0 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_136/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_136/coeff_imag_delay_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/arD1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/data_real_delay_2_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_28_port0_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/coeff_real_delay_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/mid_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/_zz_mid_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/_zz_mid_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: operator complexMult_136/_zz_mid_10 is absorbed into DSP complexMult_136/mid_reg.
DSP Report: operator complexMult_136/_zz_mid0 is absorbed into DSP complexMult_136/mid_reg.
DSP Report: Generating DSP complexMult_136/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_136/biD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/biD2_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/data_real_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/arD1_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/mid_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/aiD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real_20 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real_10 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real0 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_136/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_136/aiD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/mid_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/brD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/brD2_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/arD1_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag_20 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag_10 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag0 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_137/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_137/coeff_imag_delay_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/arD1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/data_real_delay_2_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_29_port0_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/coeff_real_delay_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/mid_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/_zz_mid_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/_zz_mid_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: operator complexMult_137/_zz_mid_10 is absorbed into DSP complexMult_137/mid_reg.
DSP Report: operator complexMult_137/_zz_mid0 is absorbed into DSP complexMult_137/mid_reg.
DSP Report: Generating DSP complexMult_137/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_137/biD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/biD2_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/data_real_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/arD1_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/mid_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/aiD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real_20 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real_10 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real0 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_137/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_137/aiD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/mid_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/brD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/brD2_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/arD1_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag_20 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag_10 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag0 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_138/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_138/coeff_imag_delay_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/arD1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/data_real_delay_2_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_30_port0_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/coeff_real_delay_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/mid_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/_zz_mid_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/_zz_mid_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: operator complexMult_138/_zz_mid_10 is absorbed into DSP complexMult_138/mid_reg.
DSP Report: operator complexMult_138/_zz_mid0 is absorbed into DSP complexMult_138/mid_reg.
DSP Report: Generating DSP complexMult_138/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_138/biD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/biD2_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/data_real_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/arD1_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/mid_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/aiD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real_20 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real_10 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real0 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_138/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_138/aiD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/mid_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/brD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/brD2_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/arD1_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag_20 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag_10 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag0 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_139/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_139/coeff_imag_delay_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/arD1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/data_real_delay_2_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_31_port0_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/coeff_real_delay_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/mid_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/_zz_mid_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/_zz_mid_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: operator complexMult_139/_zz_mid_10 is absorbed into DSP complexMult_139/mid_reg.
DSP Report: operator complexMult_139/_zz_mid0 is absorbed into DSP complexMult_139/mid_reg.
DSP Report: Generating DSP complexMult_139/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_139/biD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/biD2_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/data_real_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/arD1_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/mid_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/aiD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real_20 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real_10 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real0 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_139/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_139/aiD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/mid_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/brD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/brD2_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/arD1_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag_20 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag_10 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag0 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_140/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_140/coeff_imag_delay_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/arD1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/data_real_delay_2_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_32_port0_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/coeff_real_delay_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/mid_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/_zz_mid_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/_zz_mid_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: operator complexMult_140/_zz_mid_10 is absorbed into DSP complexMult_140/mid_reg.
DSP Report: operator complexMult_140/_zz_mid0 is absorbed into DSP complexMult_140/mid_reg.
DSP Report: Generating DSP complexMult_140/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_140/biD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/biD2_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/data_real_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/arD1_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/mid_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/aiD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real_20 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real_10 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real0 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_140/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_140/aiD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/mid_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/brD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/brD2_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/arD1_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag_20 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag_10 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag0 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_141/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_141/coeff_imag_delay_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/arD1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/data_real_delay_2_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_33_port0_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/coeff_real_delay_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/mid_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/_zz_mid_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/_zz_mid_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: operator complexMult_141/_zz_mid_10 is absorbed into DSP complexMult_141/mid_reg.
DSP Report: operator complexMult_141/_zz_mid0 is absorbed into DSP complexMult_141/mid_reg.
DSP Report: Generating DSP complexMult_141/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_141/biD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/biD2_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/data_real_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/arD1_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/mid_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/aiD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real_20 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real_10 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real0 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_141/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_141/aiD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/mid_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/brD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/brD2_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/arD1_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag_20 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag_10 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag0 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_142/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_142/coeff_imag_delay_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/arD1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/data_real_delay_2_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_34_port0_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/coeff_real_delay_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/mid_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/_zz_mid_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/_zz_mid_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: operator complexMult_142/_zz_mid_10 is absorbed into DSP complexMult_142/mid_reg.
DSP Report: operator complexMult_142/_zz_mid0 is absorbed into DSP complexMult_142/mid_reg.
DSP Report: Generating DSP complexMult_142/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_142/biD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/biD2_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/data_real_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/arD1_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/mid_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/aiD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real_20 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real_10 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real0 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_142/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_142/aiD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/mid_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/brD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/brD2_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/arD1_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag_20 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag_10 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag0 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_143/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_143/coeff_imag_delay_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/arD1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/data_real_delay_2_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_35_port0_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/coeff_real_delay_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/mid_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/_zz_mid_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/_zz_mid_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: operator complexMult_143/_zz_mid_10 is absorbed into DSP complexMult_143/mid_reg.
DSP Report: operator complexMult_143/_zz_mid0 is absorbed into DSP complexMult_143/mid_reg.
DSP Report: Generating DSP complexMult_143/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_143/biD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/biD2_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/data_real_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/arD1_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/mid_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/aiD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real_20 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real_10 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real0 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_143/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_143/aiD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/mid_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/brD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/brD2_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/arD1_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag_20 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag_10 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag0 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_144/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_144/coeff_imag_delay_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/arD1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/data_real_delay_2_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_36_port0_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/coeff_real_delay_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/mid_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/_zz_mid_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/_zz_mid_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: operator complexMult_144/_zz_mid_10 is absorbed into DSP complexMult_144/mid_reg.
DSP Report: operator complexMult_144/_zz_mid0 is absorbed into DSP complexMult_144/mid_reg.
DSP Report: Generating DSP complexMult_144/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_144/biD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/biD2_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/data_real_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/arD1_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/mid_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/aiD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real_20 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real_10 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real0 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_144/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_144/aiD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/mid_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/brD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/brD2_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/arD1_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag_20 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag_10 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag0 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_145/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_145/coeff_imag_delay_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/arD1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/data_real_delay_2_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_37_port0_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/coeff_real_delay_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/mid_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/_zz_mid_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/_zz_mid_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: operator complexMult_145/_zz_mid_10 is absorbed into DSP complexMult_145/mid_reg.
DSP Report: operator complexMult_145/_zz_mid0 is absorbed into DSP complexMult_145/mid_reg.
DSP Report: Generating DSP complexMult_145/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_145/biD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/biD2_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/data_real_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/arD1_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/mid_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/aiD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real_20 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real_10 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real0 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_145/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_145/aiD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/mid_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/brD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/brD2_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/arD1_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag_20 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag_10 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag0 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_146/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_146/coeff_imag_delay_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/arD1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/data_real_delay_2_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_38_port0_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/coeff_real_delay_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/mid_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/_zz_mid_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/_zz_mid_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: operator complexMult_146/_zz_mid_10 is absorbed into DSP complexMult_146/mid_reg.
DSP Report: operator complexMult_146/_zz_mid0 is absorbed into DSP complexMult_146/mid_reg.
DSP Report: Generating DSP complexMult_146/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_146/biD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/biD2_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/data_real_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/arD1_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/mid_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/aiD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real_20 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real_10 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real0 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_146/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_146/aiD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/mid_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/brD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/brD2_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/arD1_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag_20 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag_10 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag0 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_147/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_147/coeff_imag_delay_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/arD1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/data_real_delay_2_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_39_port0_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/coeff_real_delay_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/mid_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/_zz_mid_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/_zz_mid_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: operator complexMult_147/_zz_mid_10 is absorbed into DSP complexMult_147/mid_reg.
DSP Report: operator complexMult_147/_zz_mid0 is absorbed into DSP complexMult_147/mid_reg.
DSP Report: Generating DSP complexMult_147/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_147/biD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/biD2_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/data_real_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/arD1_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/mid_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/aiD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real_20 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real_10 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real0 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_147/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_147/aiD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/mid_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/brD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/brD2_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/arD1_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag_20 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag_10 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag0 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_148/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_148/coeff_imag_delay_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/arD1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/data_real_delay_2_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_40_port0_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/coeff_real_delay_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/mid_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/_zz_mid_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/_zz_mid_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: operator complexMult_148/_zz_mid_10 is absorbed into DSP complexMult_148/mid_reg.
DSP Report: operator complexMult_148/_zz_mid0 is absorbed into DSP complexMult_148/mid_reg.
DSP Report: Generating DSP complexMult_148/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_148/biD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/biD2_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/data_real_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/arD1_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/mid_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/aiD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real_20 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real_10 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real0 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_148/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_148/aiD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/mid_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/brD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/brD2_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/arD1_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag_20 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag_10 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag0 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_149/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_149/coeff_imag_delay_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/arD1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/data_real_delay_2_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_41_port0_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/coeff_real_delay_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/mid_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/_zz_mid_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/_zz_mid_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: operator complexMult_149/_zz_mid_10 is absorbed into DSP complexMult_149/mid_reg.
DSP Report: operator complexMult_149/_zz_mid0 is absorbed into DSP complexMult_149/mid_reg.
DSP Report: Generating DSP complexMult_149/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_149/biD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/biD2_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/data_real_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/arD1_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/mid_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/aiD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real_20 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real_10 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real0 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_149/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_149/aiD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/mid_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/brD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/brD2_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/arD1_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag_20 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag_10 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag0 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_150/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_150/coeff_imag_delay_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/arD1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/data_real_delay_2_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_42_port0_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/coeff_real_delay_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/mid_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/_zz_mid_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/_zz_mid_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: operator complexMult_150/_zz_mid_10 is absorbed into DSP complexMult_150/mid_reg.
DSP Report: operator complexMult_150/_zz_mid0 is absorbed into DSP complexMult_150/mid_reg.
DSP Report: Generating DSP complexMult_150/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_150/biD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/biD2_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/data_real_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/arD1_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/mid_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/aiD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real_20 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real_10 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real0 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_150/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_150/aiD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/mid_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/brD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/brD2_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/arD1_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag_20 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag_10 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag0 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_151/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_151/coeff_imag_delay_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/arD1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/data_real_delay_2_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_43_port0_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/coeff_real_delay_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/mid_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/_zz_mid_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/_zz_mid_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: operator complexMult_151/_zz_mid_10 is absorbed into DSP complexMult_151/mid_reg.
DSP Report: operator complexMult_151/_zz_mid0 is absorbed into DSP complexMult_151/mid_reg.
DSP Report: Generating DSP complexMult_151/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_151/biD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/biD2_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/data_real_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/arD1_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/mid_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/aiD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real_20 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real_10 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real0 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_151/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_151/aiD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/mid_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/brD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/brD2_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/arD1_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag_20 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag_10 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag0 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_152/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_152/coeff_imag_delay_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/arD1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/data_real_delay_2_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_44_port0_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/coeff_real_delay_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/mid_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/_zz_mid_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/_zz_mid_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: operator complexMult_152/_zz_mid_10 is absorbed into DSP complexMult_152/mid_reg.
DSP Report: operator complexMult_152/_zz_mid0 is absorbed into DSP complexMult_152/mid_reg.
DSP Report: Generating DSP complexMult_152/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_152/biD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/biD2_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/data_real_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/arD1_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/mid_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/aiD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real_20 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real_10 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real0 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_152/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_152/aiD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/mid_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/brD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/brD2_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/arD1_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag_20 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag_10 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag0 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_153/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_153/coeff_imag_delay_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/arD1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/data_real_delay_2_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_45_port0_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/coeff_real_delay_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/mid_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/_zz_mid_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/_zz_mid_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: operator complexMult_153/_zz_mid_10 is absorbed into DSP complexMult_153/mid_reg.
DSP Report: operator complexMult_153/_zz_mid0 is absorbed into DSP complexMult_153/mid_reg.
DSP Report: Generating DSP complexMult_153/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_153/biD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/biD2_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/data_real_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/arD1_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/mid_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/aiD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real_20 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real_10 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real0 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_153/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_153/aiD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/mid_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/brD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/brD2_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/arD1_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag_20 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag_10 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag0 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_154/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_154/coeff_imag_delay_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/arD1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/data_real_delay_2_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_46_port0_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/coeff_real_delay_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/mid_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/_zz_mid_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/_zz_mid_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: operator complexMult_154/_zz_mid_10 is absorbed into DSP complexMult_154/mid_reg.
DSP Report: operator complexMult_154/_zz_mid0 is absorbed into DSP complexMult_154/mid_reg.
DSP Report: Generating DSP complexMult_154/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_154/biD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/biD2_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/data_real_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/arD1_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/mid_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/aiD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real_20 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real_10 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real0 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_154/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_154/aiD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/mid_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/brD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/brD2_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/arD1_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag_20 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag_10 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag0 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_155/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_155/coeff_imag_delay_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/arD1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/data_real_delay_2_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_47_port0_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/coeff_real_delay_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/mid_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/_zz_mid_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/_zz_mid_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: operator complexMult_155/_zz_mid_10 is absorbed into DSP complexMult_155/mid_reg.
DSP Report: operator complexMult_155/_zz_mid0 is absorbed into DSP complexMult_155/mid_reg.
DSP Report: Generating DSP complexMult_155/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_155/biD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/biD2_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/data_real_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/arD1_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/mid_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/aiD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real_20 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real_10 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real0 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_155/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_155/aiD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/mid_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/brD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/brD2_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/arD1_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag_20 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag_10 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag0 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_156/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_156/coeff_imag_delay_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/arD1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/data_real_delay_2_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_48_port0_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/coeff_real_delay_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/mid_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/_zz_mid_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/_zz_mid_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: operator complexMult_156/_zz_mid_10 is absorbed into DSP complexMult_156/mid_reg.
DSP Report: operator complexMult_156/_zz_mid0 is absorbed into DSP complexMult_156/mid_reg.
DSP Report: Generating DSP complexMult_156/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_156/biD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/biD2_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/data_real_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/arD1_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/mid_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/aiD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real_20 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real_10 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real0 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_156/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_156/aiD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/mid_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/brD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/brD2_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/arD1_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag_20 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag_10 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag0 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_157/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_157/coeff_imag_delay_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/arD1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/data_real_delay_2_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_49_port0_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/coeff_real_delay_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/mid_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/_zz_mid_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/_zz_mid_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: operator complexMult_157/_zz_mid_10 is absorbed into DSP complexMult_157/mid_reg.
DSP Report: operator complexMult_157/_zz_mid0 is absorbed into DSP complexMult_157/mid_reg.
DSP Report: Generating DSP complexMult_157/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_157/biD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/biD2_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/data_real_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/arD1_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/mid_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/aiD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real_20 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real_10 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real0 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_157/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_157/aiD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/mid_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/brD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/brD2_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/arD1_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag_20 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag_10 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag0 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_158/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_158/coeff_imag_delay_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/arD1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/data_real_delay_2_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_50_port0_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/coeff_real_delay_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/mid_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/_zz_mid_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/_zz_mid_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: operator complexMult_158/_zz_mid_10 is absorbed into DSP complexMult_158/mid_reg.
DSP Report: operator complexMult_158/_zz_mid0 is absorbed into DSP complexMult_158/mid_reg.
DSP Report: Generating DSP complexMult_158/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_158/biD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/biD2_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/data_real_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/arD1_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/mid_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/aiD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real_20 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real_10 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real0 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_158/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_158/aiD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/mid_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/brD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/brD2_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/arD1_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag_20 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag_10 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag0 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_159/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_159/coeff_imag_delay_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/arD1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/data_real_delay_2_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_51_port0_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/coeff_real_delay_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/mid_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/_zz_mid_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/_zz_mid_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: operator complexMult_159/_zz_mid_10 is absorbed into DSP complexMult_159/mid_reg.
DSP Report: operator complexMult_159/_zz_mid0 is absorbed into DSP complexMult_159/mid_reg.
DSP Report: Generating DSP complexMult_159/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_159/biD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/biD2_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/data_real_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/arD1_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/mid_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/aiD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real_20 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real_10 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real0 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_159/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_159/aiD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/mid_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/brD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/brD2_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/arD1_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag_20 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag_10 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag0 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_160/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_160/coeff_imag_delay_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/arD1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/data_real_delay_2_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_52_port0_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/coeff_real_delay_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/mid_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/_zz_mid_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/_zz_mid_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: operator complexMult_160/_zz_mid_10 is absorbed into DSP complexMult_160/mid_reg.
DSP Report: operator complexMult_160/_zz_mid0 is absorbed into DSP complexMult_160/mid_reg.
DSP Report: Generating DSP complexMult_160/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_160/biD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/biD2_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/data_real_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/arD1_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/mid_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/aiD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real_20 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real_10 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real0 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_160/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_160/aiD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/mid_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/brD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/brD2_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/arD1_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag_20 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag_10 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag0 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_161/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_161/coeff_imag_delay_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/arD1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/data_real_delay_2_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_53_port0_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/coeff_real_delay_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/mid_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/_zz_mid_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/_zz_mid_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: operator complexMult_161/_zz_mid_10 is absorbed into DSP complexMult_161/mid_reg.
DSP Report: operator complexMult_161/_zz_mid0 is absorbed into DSP complexMult_161/mid_reg.
DSP Report: Generating DSP complexMult_161/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_161/biD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/biD2_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/data_real_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/arD1_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/mid_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/aiD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real_20 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real_10 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real0 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_161/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_161/aiD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/mid_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/brD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/brD2_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/arD1_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag_20 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag_10 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag0 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_162/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_162/coeff_imag_delay_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/arD1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/data_real_delay_2_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_54_port0_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/coeff_real_delay_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/mid_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/_zz_mid_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/_zz_mid_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: operator complexMult_162/_zz_mid_10 is absorbed into DSP complexMult_162/mid_reg.
DSP Report: operator complexMult_162/_zz_mid0 is absorbed into DSP complexMult_162/mid_reg.
DSP Report: Generating DSP complexMult_162/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_162/biD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/biD2_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/data_real_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/arD1_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/mid_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/aiD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real_20 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real_10 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real0 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_162/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_162/aiD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/mid_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/brD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/brD2_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/arD1_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag_20 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag_10 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag0 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_163/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_163/coeff_imag_delay_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/arD1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/data_real_delay_2_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_55_port0_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/coeff_real_delay_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/mid_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/_zz_mid_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/_zz_mid_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: operator complexMult_163/_zz_mid_10 is absorbed into DSP complexMult_163/mid_reg.
DSP Report: operator complexMult_163/_zz_mid0 is absorbed into DSP complexMult_163/mid_reg.
DSP Report: Generating DSP complexMult_163/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_163/biD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/biD2_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/data_real_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/arD1_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/mid_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/aiD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real_20 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real_10 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real0 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_163/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_163/aiD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/mid_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/brD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/brD2_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/arD1_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag_20 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag_10 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag0 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_164/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_164/coeff_imag_delay_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/arD1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/data_real_delay_2_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_56_port0_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/coeff_real_delay_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/mid_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/_zz_mid_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/_zz_mid_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: operator complexMult_164/_zz_mid_10 is absorbed into DSP complexMult_164/mid_reg.
DSP Report: operator complexMult_164/_zz_mid0 is absorbed into DSP complexMult_164/mid_reg.
DSP Report: Generating DSP complexMult_164/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_164/biD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/biD2_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/data_real_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/arD1_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/mid_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/aiD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real_20 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real_10 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real0 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_164/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_164/aiD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/mid_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/brD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/brD2_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/arD1_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag_20 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag_10 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag0 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_165/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_165/coeff_imag_delay_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/arD1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/data_real_delay_2_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_57_port0_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/coeff_real_delay_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/mid_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/_zz_mid_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/_zz_mid_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: operator complexMult_165/_zz_mid_10 is absorbed into DSP complexMult_165/mid_reg.
DSP Report: operator complexMult_165/_zz_mid0 is absorbed into DSP complexMult_165/mid_reg.
DSP Report: Generating DSP complexMult_165/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_165/biD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/biD2_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/data_real_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/arD1_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/mid_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/aiD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real_20 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real_10 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real0 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_165/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_165/aiD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/mid_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/brD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/brD2_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/arD1_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag_20 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag_10 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag0 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_166/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_166/coeff_imag_delay_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/arD1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/data_real_delay_2_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_58_port0_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/coeff_real_delay_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/mid_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/_zz_mid_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/_zz_mid_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: operator complexMult_166/_zz_mid_10 is absorbed into DSP complexMult_166/mid_reg.
DSP Report: operator complexMult_166/_zz_mid0 is absorbed into DSP complexMult_166/mid_reg.
DSP Report: Generating DSP complexMult_166/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_166/biD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/biD2_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/data_real_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/arD1_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/mid_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/aiD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real_20 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real_10 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real0 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_166/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_166/aiD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/mid_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/brD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/brD2_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/arD1_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag_20 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag_10 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag0 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_167/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_167/coeff_imag_delay_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/arD1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/data_real_delay_2_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_59_port0_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/coeff_real_delay_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/mid_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/_zz_mid_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/_zz_mid_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: operator complexMult_167/_zz_mid_10 is absorbed into DSP complexMult_167/mid_reg.
DSP Report: operator complexMult_167/_zz_mid0 is absorbed into DSP complexMult_167/mid_reg.
DSP Report: Generating DSP complexMult_167/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_167/biD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/biD2_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/data_real_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/arD1_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/mid_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/aiD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real_20 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real_10 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real0 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_167/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_167/aiD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/mid_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/brD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/brD2_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/arD1_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag_20 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag_10 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag0 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_168/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_168/coeff_imag_delay_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/arD1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/data_real_delay_2_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_60_port0_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/coeff_real_delay_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/mid_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/_zz_mid_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/_zz_mid_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: operator complexMult_168/_zz_mid_10 is absorbed into DSP complexMult_168/mid_reg.
DSP Report: operator complexMult_168/_zz_mid0 is absorbed into DSP complexMult_168/mid_reg.
DSP Report: Generating DSP complexMult_168/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_168/biD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/biD2_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/data_real_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/arD1_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/mid_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/aiD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real_20 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real_10 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real0 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_168/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_168/aiD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/mid_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/brD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/brD2_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/arD1_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag_20 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag_10 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag0 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_169/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_169/coeff_imag_delay_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/arD1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/data_real_delay_2_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_61_port0_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/coeff_real_delay_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/mid_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/_zz_mid_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/_zz_mid_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: operator complexMult_169/_zz_mid_10 is absorbed into DSP complexMult_169/mid_reg.
DSP Report: operator complexMult_169/_zz_mid0 is absorbed into DSP complexMult_169/mid_reg.
DSP Report: Generating DSP complexMult_169/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_169/biD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/biD2_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/data_real_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/arD1_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/mid_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/aiD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real_20 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real_10 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real0 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_169/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_169/aiD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/mid_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/brD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/brD2_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/arD1_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag_20 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag_10 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag0 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_170/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_170/coeff_imag_delay_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/arD1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/data_real_delay_2_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_62_port0_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/coeff_real_delay_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/mid_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/_zz_mid_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/_zz_mid_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: operator complexMult_170/_zz_mid_10 is absorbed into DSP complexMult_170/mid_reg.
DSP Report: operator complexMult_170/_zz_mid0 is absorbed into DSP complexMult_170/mid_reg.
DSP Report: Generating DSP complexMult_170/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_170/biD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/biD2_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/data_real_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/arD1_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/mid_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/aiD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real_20 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real_10 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real0 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_170/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_170/aiD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/mid_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/brD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/brD2_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/arD1_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag_20 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag_10 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag0 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_171/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_171/coeff_imag_delay_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/arD1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/data_real_delay_2_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_63_port0_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/coeff_real_delay_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/mid_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/_zz_mid_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/_zz_mid_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: operator complexMult_171/_zz_mid_10 is absorbed into DSP complexMult_171/mid_reg.
DSP Report: operator complexMult_171/_zz_mid0 is absorbed into DSP complexMult_171/mid_reg.
DSP Report: Generating DSP complexMult_171/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_171/biD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/biD2_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/data_real_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/arD1_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/mid_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/aiD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real_20 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real_10 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real0 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_171/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_171/aiD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/mid_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/brD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/brD2_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/arD1_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag_20 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag_10 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag0 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_63_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_63_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_63_port0_reg[6]' (FD) to '_zz_twiddleFactorROMs_63_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_63_port0_reg[11]' (FD) to '_zz_twiddleFactorROMs_63_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_61_port0_reg[12]' (FD) to '_zz_twiddleFactorROMs_61_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_61_port0_reg[13]' (FD) to '_zz_twiddleFactorROMs_61_port0_reg[22]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_59_port0_reg[1] )
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_59_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_59_port0_reg[19]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_59_port0_reg[11]' (FD) to '_zz_twiddleFactorROMs_59_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_58_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_58_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_57_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_57_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_57_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_57_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_57_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_57_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_56_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_56_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_55_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_55_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_54_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_53_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_53_port0_reg[20]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_53_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_53_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_53_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_53_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_52_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_52_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_52_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_52_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_51_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_51_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_51_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_51_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_50_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_50_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_49_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_49_port0_reg[20]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_49_port0_reg[11] )
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_48_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_48_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_48_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_48_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_48_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_48_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_47_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_47_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_47_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_47_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_47_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_47_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_46_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_46_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_46_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_46_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_45_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_16_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_45_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_45_port0_reg[20]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_45_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_45_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_45_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_45_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_44_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_16_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_44_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_44_port0_reg[20]'
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_44_port0_reg[8] )
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_43_port0_reg[6]' (FD) to '_zz_twiddleFactorROMs_43_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_43_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_43_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_43_port0_reg[10]' (FD) to '_zz_twiddleFactorROMs_43_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_42_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_42_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_42_port0_reg[6]' (FD) to '_zz_twiddleFactorROMs_42_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_42_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_42_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_42_port0_reg[12]' (FD) to '_zz_twiddleFactorROMs_42_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_42_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_41_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_16_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_41_port0_reg[19]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_41_port0_reg[20]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[10]' (FD) to '_zz_twiddleFactorROMs_41_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_41_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_40_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_40_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_40_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_40_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_40_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_40_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_40_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_39_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_5_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_39_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_38_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_37_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_37_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_37_port0_reg[13]' (FD) to '_zz_twiddleFactorROMs_37_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_37_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_36_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_36_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_36_port0_reg[13]' (FD) to '_zz_twiddleFactorROMs_36_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_36_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_35_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_35_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_35_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_34_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_33_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_33_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_33_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[3]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[4]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_32_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_32_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[9]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_31_port0_reg[10]' (FD) to '_zz_twiddleFactorROMs_31_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_30_port0_reg[2]' (FD) to '_zz_twiddleFactorROMs_30_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_30_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_30_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_29_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_29_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_29_port0_reg[7]' (FD) to '_zz_twiddleFactorROMs_29_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_28_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_16_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_28_port0_reg[1]' (FD) to '_zz_twiddleFactorROMs_28_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_28_port0_reg[6]' (FD) to '_zz_twiddleFactorROMs_28_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_27_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_27_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_27_port0_reg[5]' (FD) to '_zz_twiddleFactorROMs_27_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_27_port0_reg[10]' (FD) to '_zz_twiddleFactorROMs_27_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_26_port0_reg[6]' (FD) to '_zz_twiddleFactorROMs_26_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_26_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_26_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_25_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_25_port0_reg[15]' (FD) to '_zz_twiddleFactorROMs_25_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_24_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_24_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_24_port0_reg[4]' (FD) to '_zz_twiddleFactorROMs_24_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_24_port0_reg[12]' (FD) to '_zz_twiddleFactorROMs_24_port0_reg[21]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_23_port0_reg[0]' (FD) to '_zz_twiddleFactorROMs_23_port0_reg[18]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_23_port0_reg[3]' (FD) to '_zz_twiddleFactorROMs_7_port0_reg[22]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_23_port0_reg[8]' (FD) to '_zz_twiddleFactorROMs_23_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_twiddleFactorROMs_22_port0_reg[6]' (FD) to '_zz_twiddleFactorROMs_22_port0_reg[20]'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_18_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_17_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_16_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_15_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_14_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_13_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_12_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_11_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_10_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_9_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_8_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_7_port0_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_7_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_6_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_5_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_4_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_3_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_2_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_1_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[13] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_45_port0_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_37_port0_reg[28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_32_port0_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_5_port0_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[16] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[18] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[22] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[27] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[28] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[29] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_167/coeff_real_delay_1_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_157/coeff_real_delay_1_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_153/coeff_imag_delay_1_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_152/coeff_real_delay_1_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_145/coeff_imag_delay_1_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_140/coeff_imag_delay_1_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_126/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_125/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_124/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_123/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_122/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_121/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_120/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_119/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_118/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_117/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_116/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_115/coeff_real_delay_1_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_115/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_114/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_113/coeff_imag_delay_1_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_113/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_112/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_111/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_110/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_109/coeff_real_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_108/coeff_imag_delay_1_reg[15] )
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6904] The RAM "core/p2s/_zz_14_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core/p2s/_zz_12_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
WARNING: [Synth 8-3917] design rvFftPre_dut has port dataOut_valid driven by constant 1
WARNING: [Synth 8-7129] Port validIn in module unamed_103 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module anon is either unconnected or has no load
INFO: [Synth 8-6904] The RAM "core/p2s/_zz_14_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "core/p2s/_zz_12_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:01 ; elapsed = 00:01:23 . Memory (MB): peak = 6331.730 ; gain = 1056.199 ; free physical = 26655 ; free virtual = 63238
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+--------------+------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+--------------+------------+-----------+----------------------+-----------------+
|core/p2s | _zz_14_reg | Implied | 4 x 2304 | RAM32M16 x 165 |
|core/p2s | _zz_12_reg | Implied | 4 x 2304 | RAM32M16 x 165 |
|unamed__GBM0 | rams_3_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_4_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_5_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_6_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_1_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_2_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthRvFftFtn | rams_7_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthRvFftFtn | rams_0_reg | Implied | 16 x 288 | RAM32M16 x 21 |
+--------------+------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+--------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+--------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|ComplexMult | (((D:0x3fb1)'+(A:0xf9bb)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3ec5)'+(A:0xf384)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3d3e)'+(A:0xed6c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3b20)'+(A:0xe783)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3871)'+(A:0xe1d5)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3536)'+(A:0xdc72)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3179)'+(A:0xd767)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3ec5)'+(A:0xf384)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3b20)'+(A:0xe783)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3536)'+(A:0xdc72)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_31 | ((D'+A2)*(B:0x2d41))' | 18 | 15 | - | 16 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_31 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|ComplexMult | (((D:0x238e)'+(A:0xcaca)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x187d)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xc7c)'+(A:0xc13b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3d3e)'+(A:0xed6c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3536)'+(A:0xdc72)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xce87)'+(A:0xd767)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x2899)'+(A:0xce87)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x187d)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x645)'+(A:0xc04f)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xf384)'+(A:0xc13b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xe1d5)'+(A:0xc78f)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3b20)'+(A:0xe783)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|unamed_31 | ((D'+A2)*(B:0x2d41))' | 18 | 15 | - | 16 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_31 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|synthRvFftFtn | (((D:0x187d)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xe783)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|unamed_49 | ((D'+A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_49 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|synthRvFftFtn | (((D:0xe783)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3871)'+(A:0xe1d5)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x238e)'+(A:0xcaca)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x645)'+(A:0xc04f)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xe783)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xf384)'+(A:0xc13b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0xc2c2)'+(A:0x1294)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3536)'+(A:0xdc72)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x187d)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xf384)'+(A:0xc13b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|unamed_49 | ((D'+A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_49 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|synthRvFftFtn | (((D:0xf384)'+(A:0xc13b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x187d)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3536)'+(A:0xdc72)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3179)'+(A:0xd767)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xc7c)'+(A:0xc13b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xe1d5)'+(A:0xc78f)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xe783)'+(A:0xc4e0)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0xc2c2)'+(A:0x1294)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x3536)'+(A:0xdc72)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|synthRvFftFtn | (((D:0x645)'+(A:0x3fb1)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+(A:0x4000)'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
+--------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:11 ; elapsed = 00:01:34 . Memory (MB): peak = 6331.730 ; gain = 1056.199 ; free physical = 25983 ; free virtual = 62622
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:43 ; elapsed = 00:03:07 . Memory (MB): peak = 6993.465 ; gain = 1717.934 ; free physical = 25599 ; free virtual = 62245
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+--------------+------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+--------------+------------+-----------+----------------------+-----------------+
|core/p2s | _zz_14_reg | Implied | 4 x 2304 | RAM32M16 x 165 |
|core/p2s | _zz_12_reg | Implied | 4 x 2304 | RAM32M16 x 165 |
|unamed__GBM0 | rams_3_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_4_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_5_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_6_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_1_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_2_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthRvFftFtn | rams_7_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|synthRvFftFtn | rams_0_reg | Implied | 16 x 288 | RAM32M16 x 21 |
+--------------+------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `unamed__GBM1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM1' done
INFO: [Synth 8-5816] Retiming module `matintrlv_r64_c8_w36_sw64_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `matintrlv_r64_c8_w36_sw64_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `matintrlv_r8_c64_w36_sw64_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `matintrlv_r8_c64_w36_sw64_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `unamed_3`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3:/_zz_ret_1_real_17_reg[17]_bret
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__0__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__0__0__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__1
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__10
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__10__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__11
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__11__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__12
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__12__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__13
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__13__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__14
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__14__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__15
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__15__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__16
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__17
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__18
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__19
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__1__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__2
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__20
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__21
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__22
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__23
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__24
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__25
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__26
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__27
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__28
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__29
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__2__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__3
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__30
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__31
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__32
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__33
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__34
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__3__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__4
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__4__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__5
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__5__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__6
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__6__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__7
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__7__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__8
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__8__0
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__9
unamed_3:/_zz_ret_1_real_17_reg[17]_bret__9__0
unamed_3:/_zz_ret_5_real_reg[17]_bret
unamed_3:/_zz_ret_5_real_reg[17]_bret__0
unamed_3:/_zz_ret_5_real_reg[17]_bret__1
unamed_3:/_zz_ret_5_real_reg[17]_bret__10
unamed_3:/_zz_ret_5_real_reg[17]_bret__11
unamed_3:/_zz_ret_5_real_reg[17]_bret__12
unamed_3:/_zz_ret_5_real_reg[17]_bret__13
unamed_3:/_zz_ret_5_real_reg[17]_bret__14
unamed_3:/_zz_ret_5_real_reg[17]_bret__15
unamed_3:/_zz_ret_5_real_reg[17]_bret__16
unamed_3:/_zz_ret_5_real_reg[17]_bret__17
unamed_3:/_zz_ret_5_real_reg[17]_bret__18
unamed_3:/_zz_ret_5_real_reg[17]_bret__19
unamed_3:/_zz_ret_5_real_reg[17]_bret__2
unamed_3:/_zz_ret_5_real_reg[17]_bret__20
unamed_3:/_zz_ret_5_real_reg[17]_bret__21
unamed_3:/_zz_ret_5_real_reg[17]_bret__22
unamed_3:/_zz_ret_5_real_reg[17]_bret__23
unamed_3:/_zz_ret_5_real_reg[17]_bret__24
unamed_3:/_zz_ret_5_real_reg[17]_bret__25
unamed_3:/_zz_ret_5_real_reg[17]_bret__26
unamed_3:/_zz_ret_5_real_reg[17]_bret__27
unamed_3:/_zz_ret_5_real_reg[17]_bret__28
unamed_3:/_zz_ret_5_real_reg[17]_bret__29
unamed_3:/_zz_ret_5_real_reg[17]_bret__3
unamed_3:/_zz_ret_5_real_reg[17]_bret__30
unamed_3:/_zz_ret_5_real_reg[17]_bret__31
unamed_3:/_zz_ret_5_real_reg[17]_bret__32
unamed_3:/_zz_ret_5_real_reg[17]_bret__33
unamed_3:/_zz_ret_5_real_reg[17]_bret__34
unamed_3:/_zz_ret_5_real_reg[17]_bret__35
unamed_3:/_zz_ret_5_real_reg[17]_bret__36
unamed_3:/_zz_ret_5_real_reg[17]_bret__37
unamed_3:/_zz_ret_5_real_reg[17]_bret__38
unamed_3:/_zz_ret_5_real_reg[17]_bret__39
unamed_3:/_zz_ret_5_real_reg[17]_bret__4
unamed_3:/_zz_ret_5_real_reg[17]_bret__40
unamed_3:/_zz_ret_5_real_reg[17]_bret__41
unamed_3:/_zz_ret_5_real_reg[17]_bret__42
unamed_3:/_zz_ret_5_real_reg[17]_bret__43
unamed_3:/_zz_ret_5_real_reg[17]_bret__44
unamed_3:/_zz_ret_5_real_reg[17]_bret__45
unamed_3:/_zz_ret_5_real_reg[17]_bret__46
unamed_3:/_zz_ret_5_real_reg[17]_bret__47
unamed_3:/_zz_ret_5_real_reg[17]_bret__48
unamed_3:/_zz_ret_5_real_reg[17]_bret__49
unamed_3:/_zz_ret_5_real_reg[17]_bret__5
unamed_3:/_zz_ret_5_real_reg[17]_bret__50
unamed_3:/_zz_ret_5_real_reg[17]_bret__51
unamed_3:/_zz_ret_5_real_reg[17]_bret__6
unamed_3:/_zz_ret_5_real_reg[17]_bret__7
unamed_3:/_zz_ret_5_real_reg[17]_bret__8
unamed_3:/_zz_ret_5_real_reg[17]_bret__9
INFO: [Synth 8-5816] Retiming module `unamed_3' done
INFO: [Synth 8-5816] Retiming module `unamed_3__1`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__0__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__0__0__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__1
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__10
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__10__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__11
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__11__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__12
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__12__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__13
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__13__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__14
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__14__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__15
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__15__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__16
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__17
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__18
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__19
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__1__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__2
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__20
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__21
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__22
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__23
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__24
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__25
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__26
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__27
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__28
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__29
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__2__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__3
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__30
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__31
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__32
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__33
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__34
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__3__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__4
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__4__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__5
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__5__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__6
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__6__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__7
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__7__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__8
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__8__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__9
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_1_real_17_reg[17]_bret__9__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__0
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__1
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__10
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__11
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__12
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__13
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__14
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__15
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__16
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__17
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__18
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__19
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__2
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__20
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__21
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__22
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__23
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__24
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__25
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__26
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__27
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__28
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__29
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__3
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__30
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__31
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__32
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__33
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__34
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__35
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__36
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__37
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__38
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__39
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__4
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__40
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__41
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__42
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__43
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__44
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__45
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__46
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__47
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__48
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__49
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__5
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__50
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__51
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__6
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__7
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__8
core/core0/core/core1/core/core0/core/unamed_179/_zz_ret_5_real_reg[17]_bret__9
INFO: [Synth 8-5816] Retiming module `unamed_3__1' done
INFO: [Synth 8-5816] Retiming module `unamed_3__2`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__0__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__0__0__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__1
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__10
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__10__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__11
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__11__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__12
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__12__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__13
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__13__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__14
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__14__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__15
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__15__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__16
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__17
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__18
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__19
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__1__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__2
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__20
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__21
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__22
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__23
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__24
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__25
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__26
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__27
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__28
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__29
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__2__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__3
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__30
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__31
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__32
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__33
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__34
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__3__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__4
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__4__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__5
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__5__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__6
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__6__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__7
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__7__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__8
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__8__0
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__9
unamed_3__2:/_zz_ret_1_real_17_reg[17]_bret__9__0
unamed_3__2:/_zz_ret_5_real_reg[17]_bret
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__0
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__1
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__10
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__11
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__12
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__13
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__14
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__15
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__16
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__17
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__18
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__19
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__2
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__20
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__21
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__22
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__23
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__24
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__25
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__26
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__27
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__28
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__29
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__3
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__30
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__31
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__32
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__33
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__34
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__35
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__36
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__37
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__38
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__39
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__4
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__40
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__41
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__42
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__43
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__44
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__45
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__46
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__47
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__48
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__49
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__5
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__50
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__51
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__6
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__7
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__8
unamed_3__2:/_zz_ret_5_real_reg[17]_bret__9
INFO: [Synth 8-5816] Retiming module `unamed_3__2' done
INFO: [Synth 8-5816] Retiming module `unamed_3__3`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__0__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__0__0__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__1
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__10
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__10__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__11
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__11__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__12
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__12__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__13
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__13__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__14
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__14__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__15
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__15__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__16
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__17
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__18
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__19
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__1__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__2
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__20
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__21
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__22
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__23
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__24
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__25
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__26
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__27
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__28
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__29
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__2__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__3
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__30
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__31
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__32
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__33
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__34
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__3__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__4
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__4__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__5
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__5__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__6
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__6__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__7
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__7__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__8
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__8__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__9
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_1_real_17_reg[17]_bret__9__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__0
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__1
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core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__11
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__12
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core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__14
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__15
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__16
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__17
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__18
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__19
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__2
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__20
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__21
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__22
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__23
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__24
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__25
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__26
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__27
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__28
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__29
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__3
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__30
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__31
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__32
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__33
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__34
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__35
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__36
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__37
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__38
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__39
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__4
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__40
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__41
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__42
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__43
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__44
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__45
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__46
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__47
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__48
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__49
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__5
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__50
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__51
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__6
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__7
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__8
core/core0/core/core1/core/core0/core/unamed_183/_zz_ret_5_real_reg[17]_bret__9
INFO: [Synth 8-5816] Retiming module `unamed_3__3' done
INFO: [Synth 8-5816] Retiming module `fft_n64_factors_8_8_scales_2_2_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `fft_n64_factors_8_8_scales_2_2_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `unamed_3__4`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__0__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__0__0__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__1
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__10
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__10__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__11
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__11__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__12
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__12__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__13
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__13__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__14
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__14__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__15
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__15__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__16
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__17
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__18
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__19
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__1__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__2
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__20
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__21
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__22
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__23
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__24
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__25
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__26
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__27
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__28
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__29
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__2__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__3
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__30
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__31
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__32
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__33
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__34
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__3__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__4
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__4__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__5
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__5__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__6
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__6__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__7
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__7__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__8
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__8__0
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__9
unamed_3__4:/_zz_ret_1_real_17_reg[17]_bret__9__0
unamed_3__4:/_zz_ret_5_real_reg[17]_bret
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__0
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__1
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__10
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__11
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__12
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__13
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__14
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__15
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__16
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__17
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__18
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__19
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__2
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__20
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__21
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__22
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__23
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__24
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__25
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__26
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__27
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__28
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__29
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__3
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__30
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__31
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__32
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__33
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__34
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__35
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__36
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__37
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__38
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__39
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__4
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__40
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__41
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__42
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__43
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__44
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__45
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__46
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__47
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__48
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__49
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__5
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__50
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__51
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__6
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__7
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__8
unamed_3__4:/_zz_ret_5_real_reg[17]_bret__9
INFO: [Synth 8-5816] Retiming module `unamed_3__4' done
INFO: [Synth 8-5816] Retiming module `fft_n8_factors_8_scales_1_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `fft_n8_factors_8_scales_1_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `rvFftPre_fft_n512_sw64_factors_8_8_8_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `rvFftPre_fft_n512_sw64_factors_8_8_8_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `anon_1__GB2`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_1__GB2' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn_GT1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn_GT1' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn__GC0' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn' done
INFO: [Synth 8-5816] Retiming module `unamed__GBM0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn' done
INFO: [Synth 8-5816] Retiming module `unamed_94__GC0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_94__GC0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GC0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GC0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn' done
INFO: [Synth 8-5816] Retiming module `rvFftPre_dut_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `rvFftPre_dut_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn' done
INFO: [Synth 8-5816] Retiming module `anon_1__GB0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_1__GB0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn' done
INFO: [Synth 8-5816] Retiming module `anon_1__GB5_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_1__GB5_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn_GT2_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn_GT2_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftFtn' done
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[286] along load instance corei_7/i_2233 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[286] along load instance corei_7/i_2234 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[286] along load instance corei_7/i_2994 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[286] along load instance corei_7/i_2995 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[285] along load instance corei_7/i_2238 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[285] along load instance corei_7/i_2241 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[285] along load instance corei_7/i_3001 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[285] along load instance corei_7/i_3002 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[284] along load instance corei_7/i_2246 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[284] along load instance corei_7/i_2251 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[284] along load instance corei_7/i_3006 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[284] along load instance corei_7/i_3009 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[283] along load instance corei_7/i_2254 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[283] along load instance corei_7/i_2257 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[283] along load instance corei_7/i_3017 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[283] along load instance corei_7/i_3018 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[282] along load instance corei_7/i_2265 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[282] along load instance corei_7/i_2266 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[282] along load instance corei_7/i_3025 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[282] along load instance corei_7/i_3026 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[281] along load instance corei_7/i_2274 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[281] along load instance corei_7/i_2275 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[281] along load instance corei_7/i_3030 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[281] along load instance corei_7/i_3033 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[280] along load instance corei_7/i_2282 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[280] along load instance corei_7/i_2283 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[280] along load instance corei_7/i_3041 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[280] along load instance corei_7/i_3042 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[279] along load instance corei_7/i_2290 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[279] along load instance corei_7/i_2291 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[279] along load instance corei_7/i_3050 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[279] along load instance corei_7/i_3051 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[278] along load instance corei_7/i_2166 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[278] along load instance corei_7/i_2171 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[278] along load instance corei_7/i_3058 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[278] along load instance corei_7/i_3059 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[277] along load instance corei_7/i_2174 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[277] along load instance corei_7/i_2179 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[277] along load instance corei_7/i_3066 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[277] along load instance corei_7/i_3067 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[276] along load instance corei_7/i_2186 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[276] along load instance corei_7/i_2187 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[276] along load instance corei_7/i_3070 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[276] along load instance corei_7/i_3073 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[275] along load instance corei_7/i_2194 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[275] along load instance corei_7/i_2195 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[275] along load instance corei_7/i_3082 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[275] along load instance corei_7/i_3083 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[274] along load instance corei_7/i_2198 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[274] along load instance corei_7/i_2201 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[274] along load instance corei_7/i_3086 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[274] along load instance corei_7/i_3091 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[273] along load instance corei_7/i_2206 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[273] along load instance corei_7/i_2209 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[273] along load instance corei_7/i_3097 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[273] along load instance corei_7/i_3098 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[272] along load instance corei_7/i_2218 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[272] along load instance corei_7/i_2219 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[272] along load instance corei_7/i_3102 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[272] along load instance corei_7/i_3107 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[271] along load instance corei_7/i_2222 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[271] along load instance corei_7/i_2227 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[271] along load instance corei_7/i_3114 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[271] along load instance corei_7/i_3115 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[270] along load instance corei_7/i_3122 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[270] along load instance corei_7/i_3123 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[270] along load instance corei_7/i_4786 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[270] along load instance corei_7/i_4787 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[250] along load instance corei_7/i_4946 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[250] along load instance corei_7/i_4947 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[249] along load instance corei_7/i_4954 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[249] along load instance corei_7/i_4955 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[248] along load instance corei_7/i_4962 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[248] along load instance corei_7/i_4963 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[247] along load instance corei_7/i_4966 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[247] along load instance corei_7/i_4969 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[246] along load instance corei_7/i_4978 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[246] along load instance corei_7/i_4979 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[245] along load instance corei_7/i_4986 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[245] along load instance corei_7/i_4987 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[244] along load instance corei_7/i_4990 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[244] along load instance corei_7/i_4993 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[243] along load instance corei_7/i_5002 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[243] along load instance corei_7/i_5003 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[242] along load instance corei_7/i_5010 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[242] along load instance corei_7/i_5011 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[241] along load instance corei_7/i_5014 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[241] along load instance corei_7/i_5019 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[240] along load instance corei_7/i_5022 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[240] along load instance corei_7/i_5025 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[239] along load instance corei_7/i_5030 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[239] along load instance corei_7/i_5033 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[238] along load instance corei_7/i_5042 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[238] along load instance corei_7/i_5043 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[237] along load instance corei_7/i_5050 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[237] along load instance corei_7/i_5051 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[236] along load instance corei_7/i_5054 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[236] along load instance corei_7/i_5057 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[235] along load instance corei_7/i_5062 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[235] along load instance corei_7/i_5065 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[234] along load instance corei_7/i_5070 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[234] along load instance corei_7/i_5075 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[214] along load instance corei_7/i_2370 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[214] along load instance corei_7/i_2371 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[214] along load instance corei_7/i_5235 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[213] along load instance corei_7/i_2374 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[213] along load instance corei_7/i_2377 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[213] along load instance corei_7/i_5243 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[212] along load instance corei_7/i_2386 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[212] along load instance corei_7/i_2387 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[212] along load instance corei_7/i_5246 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[211] along load instance corei_7/i_2394 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[211] along load instance corei_7/i_2395 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[211] along load instance corei_7/i_5259 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[210] along load instance corei_7/i_2398 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[210] along load instance corei_7/i_2401 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[210] along load instance corei_7/i_5267 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[209] along load instance corei_7/i_2409 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[209] along load instance corei_7/i_2410 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[209] along load instance corei_7/i_5275 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[208] along load instance corei_7/i_2414 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[208] along load instance corei_7/i_2417 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[208] along load instance corei_7/i_5278 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[207] along load instance corei_7/i_2422 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[207] along load instance corei_7/i_2425 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[207] along load instance corei_7/i_5286 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[206] along load instance corei_7/i_2302 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[206] along load instance corei_7/i_2305 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[206] along load instance corei_7/i_5299 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[205] along load instance corei_7/i_2313 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[205] along load instance corei_7/i_2314 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[205] along load instance corei_7/i_5307 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[204] along load instance corei_7/i_2322 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[204] along load instance corei_7/i_2323 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[204] along load instance corei_7/i_5310 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[203] along load instance corei_7/i_2330 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[203] along load instance corei_7/i_2331 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[203] along load instance corei_7/i_5318 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[202] along load instance corei_7/i_2334 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[202] along load instance corei_7/i_2337 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[202] along load instance corei_7/i_5331 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[201] along load instance corei_7/i_2345 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[201] along load instance corei_7/i_2346 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[201] along load instance corei_7/i_5339 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[200] along load instance corei_7/i_2350 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[200] along load instance corei_7/i_2353 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[200] along load instance corei_7/i_5347 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[199] along load instance corei_7/i_2362 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[199] along load instance corei_7/i_2363 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[199] along load instance corei_7/i_5350 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[198] along load instance corei_7/i_3466 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[198] along load instance corei_7/i_3467 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[198] along load instance corei_7/i_5363 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[142] along load instance corei_7/i_2642 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[142] along load instance corei_7/i_2643 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[142] along load instance corei_7/i_3779 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[141] along load instance corei_7/i_2650 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[141] along load instance corei_7/i_2651 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[141] along load instance corei_7/i_3782 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[140] along load instance corei_7/i_2654 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[140] along load instance corei_7/i_2657 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[140] along load instance corei_7/i_3790 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[139] along load instance corei_7/i_2662 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[139] along load instance corei_7/i_2665 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[139] along load instance corei_7/i_3798 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[138] along load instance corei_7/i_2670 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[138] along load instance corei_7/i_2673 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[138] along load instance corei_7/i_3809 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[137] along load instance corei_7/i_2681 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[137] along load instance corei_7/i_2682 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[137] along load instance corei_7/i_3814 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[136] along load instance corei_7/i_2689 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[136] along load instance corei_7/i_2690 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[136] along load instance corei_7/i_3822 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[135] along load instance corei_7/i_2694 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[135] along load instance corei_7/i_2697 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[135] along load instance corei_7/i_3835 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[134] along load instance corei_7/i_2578 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[134] along load instance corei_7/i_2579 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[134] along load instance corei_7/i_3843 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[133] along load instance corei_7/i_2586 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[133] along load instance corei_7/i_2587 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[133] along load instance corei_7/i_3851 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[132] along load instance corei_7/i_2590 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[132] along load instance corei_7/i_2593 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[132] along load instance corei_7/i_3854 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[131] along load instance corei_7/i_2598 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[131] along load instance corei_7/i_2601 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[131] along load instance corei_7/i_3867 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[130] along load instance corei_7/i_2606 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[130] along load instance corei_7/i_2609 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[130] along load instance corei_7/i_3875 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[129] along load instance corei_7/i_2618 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[129] along load instance corei_7/i_2619 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[129] along load instance corei_7/i_3883 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[128] along load instance corei_7/i_2626 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[128] along load instance corei_7/i_2627 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[128] along load instance corei_7/i_3886 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[127] along load instance corei_7/i_2630 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[127] along load instance corei_7/i_2633 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[127] along load instance corei_7/i_3894 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[126] along load instance corei_7/i_3905 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[126] along load instance corei_7/i_5665 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[126] along load instance corei_7/i_5666 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[70] along load instance corei_7/i_2915 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[70] along load instance corei_7/i_6002 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[70] along load instance corei_7/i_6007 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[69] along load instance corei_7/i_2921 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[69] along load instance corei_7/i_6014 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[69] along load instance corei_7/i_6015 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[68] along load instance corei_7/i_2931 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[68] along load instance corei_7/i_6021 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[68] along load instance corei_7/i_6022 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[67] along load instance corei_7/i_2939 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[67] along load instance corei_7/i_6026 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[67] along load instance corei_7/i_6029 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[66] along load instance corei_7/i_2947 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[66] along load instance corei_7/i_6038 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[66] along load instance corei_7/i_6039 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[65] along load instance corei_7/i_2955 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[65] along load instance corei_7/i_6046 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[65] along load instance corei_7/i_6047 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[64] along load instance corei_7/i_2963 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[64] along load instance corei_7/i_6053 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[64] along load instance corei_7/i_6054 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[63] along load instance corei_7/i_2971 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[63] along load instance corei_7/i_6058 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[63] along load instance corei_7/i_6063 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[62] along load instance corei_7/i_2851 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[62] along load instance corei_7/i_6066 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[62] along load instance corei_7/i_6071 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[61] along load instance corei_7/i_2854 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[61] along load instance corei_7/i_6078 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[61] along load instance corei_7/i_6079 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[60] along load instance corei_7/i_2867 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[60] along load instance corei_7/i_6086 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[60] along load instance corei_7/i_6087 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[59] along load instance corei_7/i_2875 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[59] along load instance corei_7/i_6094 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[59] along load instance corei_7/i_6095 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[58] along load instance corei_7/i_2883 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[58] along load instance corei_7/i_6101 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[58] along load instance corei_7/i_6102 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[57] along load instance corei_7/i_2891 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[57] along load instance corei_7/i_6106 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[57] along load instance corei_7/i_6111 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[56] along load instance corei_7/i_2894 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[56] along load instance corei_7/i_6118 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[56] along load instance corei_7/i_6119 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[55] along load instance corei_7/i_2907 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[55] along load instance corei_7/i_6126 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[55] along load instance corei_7/i_6127 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[54] along load instance corei_7/i_4342 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[54] along load instance corei_7/i_6134 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_3_delay_1_reg[54] along load instance corei_7/i_6135 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[286] along load instance corei_7/i_2234
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[286] along load instance corei_7/i_2994
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[286] along load instance corei_7/i_2995
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[285] along load instance corei_7/i_2241
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[285] along load instance corei_7/i_3001
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[285] along load instance corei_7/i_3002
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[284] along load instance corei_7/i_2246
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[284] along load instance corei_7/i_3006
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[284] along load instance corei_7/i_3009
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[283] along load instance corei_7/i_2257
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[283] along load instance corei_7/i_3017
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[283] along load instance corei_7/i_3018
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[282] along load instance corei_7/i_2266
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[282] along load instance corei_7/i_3025
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[282] along load instance corei_7/i_3026
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[281] along load instance corei_7/i_2274
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[281] along load instance corei_7/i_3030
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[281] along load instance corei_7/i_3033
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[280] along load instance corei_7/i_2282
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[280] along load instance corei_7/i_3041
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[280] along load instance corei_7/i_3042
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[279] along load instance corei_7/i_2290
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[279] along load instance corei_7/i_3050
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[279] along load instance corei_7/i_3051
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[278] along load instance corei_7/i_2166
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[278] along load instance corei_7/i_3058
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[278] along load instance corei_7/i_3059
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[277] along load instance corei_7/i_2174
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[277] along load instance corei_7/i_3066
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[277] along load instance corei_7/i_3067
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[276] along load instance corei_7/i_2186
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[276] along load instance corei_7/i_3070
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[276] along load instance corei_7/i_3073
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[275] along load instance corei_7/i_2194
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[275] along load instance corei_7/i_3082
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[275] along load instance corei_7/i_3083
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[274] along load instance corei_7/i_2201
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[274] along load instance corei_7/i_3086
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[274] along load instance corei_7/i_3091
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[273] along load instance corei_7/i_2209
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[273] along load instance corei_7/i_3097
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[273] along load instance corei_7/i_3098
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[272] along load instance corei_7/i_2218
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[272] along load instance corei_7/i_3102
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[272] along load instance corei_7/i_3107
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[271] along load instance corei_7/i_2222
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[271] along load instance corei_7/i_3114
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[271] along load instance corei_7/i_3115
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[270] along load instance corei_7/i_3122
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[270] along load instance corei_7/i_3123
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[270] along load instance corei_7/i_4786
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[250] along load instance corei_7/i_4942 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[250] along load instance corei_7/i_4946 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[249] along load instance corei_7/i_4950 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[249] along load instance corei_7/i_4954 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[248] along load instance corei_7/i_4958 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[248] along load instance corei_7/i_4962 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[247] along load instance corei_7/i_4969
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[247] along load instance corei_7/i_4971 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[246] along load instance corei_7/i_4974 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[246] along load instance corei_7/i_4978 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[245] along load instance corei_7/i_4982 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[245] along load instance corei_7/i_4986 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[244] along load instance corei_7/i_4993
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[244] along load instance corei_7/i_4995 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[243] along load instance corei_7/i_4998 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[243] along load instance corei_7/i_5002 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[242] along load instance corei_7/i_5006 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[242] along load instance corei_7/i_5010 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[241] along load instance corei_7/i_5014
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[241] along load instance corei_7/i_5017 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[240] along load instance corei_7/i_5025
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[240] along load instance corei_7/i_5027 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[239] along load instance corei_7/i_5033
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[239] along load instance corei_7/i_5035 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[238] along load instance corei_7/i_5038 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[238] along load instance corei_7/i_5042 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[237] along load instance corei_7/i_5046 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[237] along load instance corei_7/i_5050 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[236] along load instance corei_7/i_5057
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[236] along load instance corei_7/i_5059 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[235] along load instance corei_7/i_5065
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[235] along load instance corei_7/i_5067 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[234] along load instance corei_7/i_5070
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[234] along load instance corei_7/i_5073 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[214] along load instance corei_7/i_2370
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[214] along load instance corei_7/i_2371
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[214] along load instance corei_7/i_5230 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[213] along load instance corei_7/i_2374
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[213] along load instance corei_7/i_2377
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[213] along load instance corei_7/i_5238 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[212] along load instance corei_7/i_2386
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[212] along load instance corei_7/i_2387
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[212] along load instance corei_7/i_5251 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[211] along load instance corei_7/i_2394
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[211] along load instance corei_7/i_2395
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[211] along load instance corei_7/i_5254 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[210] along load instance corei_7/i_2398
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[210] along load instance corei_7/i_2401
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[210] along load instance corei_7/i_5262 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[209] along load instance corei_7/i_2409
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[209] along load instance corei_7/i_2410
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[209] along load instance corei_7/i_5273 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[208] along load instance corei_7/i_2414
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[208] along load instance corei_7/i_2417
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[208] along load instance corei_7/i_5283 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[207] along load instance corei_7/i_2422
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[207] along load instance corei_7/i_2425
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[207] along load instance corei_7/i_5291 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[206] along load instance corei_7/i_2302
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[206] along load instance corei_7/i_2305
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[206] along load instance corei_7/i_5294 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[205] along load instance corei_7/i_2313
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[205] along load instance corei_7/i_2314
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[205] along load instance corei_7/i_5302 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[204] along load instance corei_7/i_2322
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[204] along load instance corei_7/i_2323
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[204] along load instance corei_7/i_5315 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[203] along load instance corei_7/i_2330
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[203] along load instance corei_7/i_2331
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[203] along load instance corei_7/i_5323 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[202] along load instance corei_7/i_2334
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[202] along load instance corei_7/i_2337
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[202] along load instance corei_7/i_5329 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[201] along load instance corei_7/i_2345
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[201] along load instance corei_7/i_2346
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[201] along load instance corei_7/i_5337 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[200] along load instance corei_7/i_2350
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[200] along load instance corei_7/i_2353
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[200] along load instance corei_7/i_5345 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[199] along load instance corei_7/i_2362
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[199] along load instance corei_7/i_2363
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[199] along load instance corei_7/i_5355 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[198] along load instance corei_7/i_3466
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[198] along load instance corei_7/i_3467
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[198] along load instance corei_7/i_5358 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[142] along load instance corei_7/i_2638 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[142] along load instance corei_7/i_2642 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[142] along load instance corei_7/i_3779 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[141] along load instance corei_7/i_2646 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[141] along load instance corei_7/i_2650 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[141] along load instance corei_7/i_3782 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[140] along load instance corei_7/i_2657
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[140] along load instance corei_7/i_2659 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[140] along load instance corei_7/i_3790 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[139] along load instance corei_7/i_2665
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[139] along load instance corei_7/i_2667 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[139] along load instance corei_7/i_3798 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[138] along load instance corei_7/i_2673
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[138] along load instance corei_7/i_2675 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[138] along load instance corei_7/i_3809 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[137] along load instance corei_7/i_2682
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[137] along load instance corei_7/i_2683 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[137] along load instance corei_7/i_3814 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[136] along load instance corei_7/i_2690
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[136] along load instance corei_7/i_2691 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[136] along load instance corei_7/i_3822 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[135] along load instance corei_7/i_2697
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[135] along load instance corei_7/i_2699 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[135] along load instance corei_7/i_3835 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[134] along load instance corei_7/i_2574 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[134] along load instance corei_7/i_2578 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[134] along load instance corei_7/i_3843 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[133] along load instance corei_7/i_2582 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[133] along load instance corei_7/i_2586 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[133] along load instance corei_7/i_3851 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[132] along load instance corei_7/i_2593
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[132] along load instance corei_7/i_2595 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[132] along load instance corei_7/i_3854 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[131] along load instance corei_7/i_2601
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[131] along load instance corei_7/i_2603 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[131] along load instance corei_7/i_3867 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[130] along load instance corei_7/i_2609
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[130] along load instance corei_7/i_2611 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[130] along load instance corei_7/i_3875 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[129] along load instance corei_7/i_2614 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[129] along load instance corei_7/i_2618 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[129] along load instance corei_7/i_3883 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[128] along load instance corei_7/i_2622 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[128] along load instance corei_7/i_2626 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[128] along load instance corei_7/i_3886 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[127] along load instance corei_7/i_2633
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[127] along load instance corei_7/i_2635 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[127] along load instance corei_7/i_3894 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[126] along load instance corei_7/i_3905
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[126] along load instance corei_7/i_5666
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[126] along load instance corei_7/i_5667 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[70] along load instance corei_7/i_2910 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[70] along load instance corei_7/i_2915 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[70] along load instance corei_7/i_6002 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[70] along load instance corei_7/i_6005 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[69] along load instance corei_7/i_2921
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[69] along load instance corei_7/i_2922 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[69] along load instance corei_7/i_6010 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[69] along load instance corei_7/i_6014 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[68] along load instance corei_7/i_2926 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[68] along load instance corei_7/i_2931 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[68] along load instance corei_7/i_6022 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[68] along load instance corei_7/i_6023 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[67] along load instance corei_7/i_2938 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[67] along load instance corei_7/i_2939 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[67] along load instance corei_7/i_6029 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[67] along load instance corei_7/i_6031 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[66] along load instance corei_7/i_2942 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[66] along load instance corei_7/i_2947 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[66] along load instance corei_7/i_6034 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[66] along load instance corei_7/i_6038 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[65] along load instance corei_7/i_2954 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[65] along load instance corei_7/i_2955 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[65] along load instance corei_7/i_6042 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[65] along load instance corei_7/i_6046 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[64] along load instance corei_7/i_2962 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[64] along load instance corei_7/i_2963 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[64] along load instance corei_7/i_6054 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[64] along load instance corei_7/i_6055 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[63] along load instance corei_7/i_2970 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[63] along load instance corei_7/i_2971 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[63] along load instance corei_7/i_6058 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[63] along load instance corei_7/i_6061 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[62] along load instance corei_7/i_2846 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[62] along load instance corei_7/i_2851 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[62] along load instance corei_7/i_6066 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[62] along load instance corei_7/i_6069 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[61] along load instance corei_7/i_2854
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[61] along load instance corei_7/i_2857 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[61] along load instance corei_7/i_6074 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[61] along load instance corei_7/i_6078 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[60] along load instance corei_7/i_2866 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[60] along load instance corei_7/i_2867 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[60] along load instance corei_7/i_6082 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[60] along load instance corei_7/i_6086 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[59] along load instance corei_7/i_2874 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[59] along load instance corei_7/i_2875 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[59] along load instance corei_7/i_6090 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[59] along load instance corei_7/i_6094 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[58] along load instance corei_7/i_2882 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[58] along load instance corei_7/i_2883 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[58] along load instance corei_7/i_6102 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[58] along load instance corei_7/i_6103 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[57] along load instance corei_7/i_2886 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[57] along load instance corei_7/i_2891 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[57] along load instance corei_7/i_6106 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[57] along load instance corei_7/i_6109 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[56] along load instance corei_7/i_2894
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[56] along load instance corei_7/i_2897 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[56] along load instance corei_7/i_6114 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[56] along load instance corei_7/i_6118 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[55] along load instance corei_7/i_2906 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[55] along load instance corei_7/i_2907 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[55] along load instance corei_7/i_6122 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[55] along load instance corei_7/i_6126 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[54] along load instance corei_7/i_4342
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[54] along load instance corei_7/i_4345 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[54] along load instance corei_7/i_6130 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_4_delay_1_reg[54] along load instance corei_7/i_6134 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[286] along load instance corei_7/i_2234
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[286] along load instance corei_7/i_2235 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[286] along load instance corei_7/i_2990 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[286] along load instance corei_7/i_2994 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[285] along load instance corei_7/i_2241
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[285] along load instance corei_7/i_2243 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[285] along load instance corei_7/i_3002 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[285] along load instance corei_7/i_3003 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[284] along load instance corei_7/i_2246
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[284] along load instance corei_7/i_2249 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[284] along load instance corei_7/i_3009 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[284] along load instance corei_7/i_3011 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[283] along load instance corei_7/i_2257
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[283] along load instance corei_7/i_2259 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[283] along load instance corei_7/i_3018 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[283] along load instance corei_7/i_3019 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[282] along load instance corei_7/i_2266
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[282] along load instance corei_7/i_2267 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[282] along load instance corei_7/i_3026 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[282] along load instance corei_7/i_3027 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[281] along load instance corei_7/i_2270 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[281] along load instance corei_7/i_2274 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[281] along load instance corei_7/i_3033 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[281] along load instance corei_7/i_3035 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[280] along load instance corei_7/i_2278 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[280] along load instance corei_7/i_2282 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[280] along load instance corei_7/i_3042 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[280] along load instance corei_7/i_3043 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[279] along load instance corei_7/i_2286 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[279] along load instance corei_7/i_2290 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[279] along load instance corei_7/i_3046 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[279] along load instance corei_7/i_3050 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[278] along load instance corei_7/i_2166
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[278] along load instance corei_7/i_2169 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[278] along load instance corei_7/i_3054 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[278] along load instance corei_7/i_3058 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[277] along load instance corei_7/i_2174
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[277] along load instance corei_7/i_2177 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[277] along load instance corei_7/i_3062 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[277] along load instance corei_7/i_3066 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[276] along load instance corei_7/i_2182 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[276] along load instance corei_7/i_2186 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[276] along load instance corei_7/i_3073 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[276] along load instance corei_7/i_3075 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[275] along load instance corei_7/i_2190 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[275] along load instance corei_7/i_2194 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[275] along load instance corei_7/i_3078 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[275] along load instance corei_7/i_3082 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[274] along load instance corei_7/i_2201
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[274] along load instance corei_7/i_2203 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[274] along load instance corei_7/i_3086 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[274] along load instance corei_7/i_3089 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[273] along load instance corei_7/i_2209
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[273] along load instance corei_7/i_2211 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[273] along load instance corei_7/i_3098 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[273] along load instance corei_7/i_3099 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[272] along load instance corei_7/i_2214 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[272] along load instance corei_7/i_2218 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[272] along load instance corei_7/i_3102 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[272] along load instance corei_7/i_3105 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[271] along load instance corei_7/i_2222
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[271] along load instance corei_7/i_2225 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[271] along load instance corei_7/i_3110 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[271] along load instance corei_7/i_3114 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[270] along load instance corei_7/i_3118 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[270] along load instance corei_7/i_3122 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[270] along load instance corei_7/i_4782 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[270] along load instance corei_7/i_4786 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[250] along load instance corei_7/i_4942
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[250] along load instance corei_7/i_4946
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[249] along load instance corei_7/i_4950
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[249] along load instance corei_7/i_4954
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[248] along load instance corei_7/i_4958
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[248] along load instance corei_7/i_4962
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[247] along load instance corei_7/i_4969
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[247] along load instance corei_7/i_4971
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[246] along load instance corei_7/i_4974
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[246] along load instance corei_7/i_4978
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[245] along load instance corei_7/i_4982
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[245] along load instance corei_7/i_4986
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[244] along load instance corei_7/i_4993
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[244] along load instance corei_7/i_4995
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[243] along load instance corei_7/i_4998
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[243] along load instance corei_7/i_5002
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[242] along load instance corei_7/i_5006
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[242] along load instance corei_7/i_5010
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[241] along load instance corei_7/i_5014
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[241] along load instance corei_7/i_5017
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[240] along load instance corei_7/i_5025
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[240] along load instance corei_7/i_5027
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[239] along load instance corei_7/i_5033
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[239] along load instance corei_7/i_5035
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[238] along load instance corei_7/i_5038
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[238] along load instance corei_7/i_5042
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[237] along load instance corei_7/i_5046
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[237] along load instance corei_7/i_5050
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[236] along load instance corei_7/i_5057
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[236] along load instance corei_7/i_5059
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[235] along load instance corei_7/i_5065
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[235] along load instance corei_7/i_5067
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[234] along load instance corei_7/i_5070
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[234] along load instance corei_7/i_5073
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[214] along load instance corei_7/i_2366 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[214] along load instance corei_7/i_2370 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[214] along load instance corei_7/i_5230 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[213] along load instance corei_7/i_2377
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[213] along load instance corei_7/i_2379 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[213] along load instance corei_7/i_5238 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[212] along load instance corei_7/i_2382 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[212] along load instance corei_7/i_2386 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[212] along load instance corei_7/i_5251 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[211] along load instance corei_7/i_2390 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[211] along load instance corei_7/i_2394 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[211] along load instance corei_7/i_5254 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[210] along load instance corei_7/i_2401
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[210] along load instance corei_7/i_2403 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[210] along load instance corei_7/i_5262 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[209] along load instance corei_7/i_2410
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[209] along load instance corei_7/i_2411 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[209] along load instance corei_7/i_5273 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[208] along load instance corei_7/i_2417
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[208] along load instance corei_7/i_2419 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[208] along load instance corei_7/i_5283 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[207] along load instance corei_7/i_2425
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[207] along load instance corei_7/i_2427 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[207] along load instance corei_7/i_5291 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[206] along load instance corei_7/i_2305
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[206] along load instance corei_7/i_2307 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[206] along load instance corei_7/i_5294 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[205] along load instance corei_7/i_2314
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[205] along load instance corei_7/i_2315 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[205] along load instance corei_7/i_5302 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[204] along load instance corei_7/i_2318 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[204] along load instance corei_7/i_2322 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[204] along load instance corei_7/i_5315 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[203] along load instance corei_7/i_2326 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[203] along load instance corei_7/i_2330 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[203] along load instance corei_7/i_5323 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[202] along load instance corei_7/i_2337
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[202] along load instance corei_7/i_2339 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[202] along load instance corei_7/i_5329 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[201] along load instance corei_7/i_2346
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[201] along load instance corei_7/i_2347 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[201] along load instance corei_7/i_5337 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[200] along load instance corei_7/i_2353
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[200] along load instance corei_7/i_2355 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[200] along load instance corei_7/i_5345 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[199] along load instance corei_7/i_2358 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[199] along load instance corei_7/i_2362 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[199] along load instance corei_7/i_5355 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[198] along load instance corei_7/i_3462 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[198] along load instance corei_7/i_3466 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[198] along load instance corei_7/i_5358 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[142] along load instance corei_7/i_2638
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[142] along load instance corei_7/i_2642
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[142] along load instance corei_7/i_3774 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[141] along load instance corei_7/i_2646
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[141] along load instance corei_7/i_2650
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[141] along load instance corei_7/i_3787 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[140] along load instance corei_7/i_2657
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[140] along load instance corei_7/i_2659
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[140] along load instance corei_7/i_3795 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[139] along load instance corei_7/i_2665
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[139] along load instance corei_7/i_2667
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[139] along load instance corei_7/i_3803 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[138] along load instance corei_7/i_2673
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[138] along load instance corei_7/i_2675
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[138] along load instance corei_7/i_3811 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[137] along load instance corei_7/i_2682
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[137] along load instance corei_7/i_2683
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[137] along load instance corei_7/i_3819 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[136] along load instance corei_7/i_2690
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[136] along load instance corei_7/i_2691
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[136] along load instance corei_7/i_3827 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[135] along load instance corei_7/i_2697
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[135] along load instance corei_7/i_2699
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[135] along load instance corei_7/i_3830 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[134] along load instance corei_7/i_2574
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[134] along load instance corei_7/i_2578
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[134] along load instance corei_7/i_3838 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[133] along load instance corei_7/i_2582
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[133] along load instance corei_7/i_2586
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[133] along load instance corei_7/i_3846 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[132] along load instance corei_7/i_2593
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[132] along load instance corei_7/i_2595
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[132] along load instance corei_7/i_3859 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[131] along load instance corei_7/i_2601
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[131] along load instance corei_7/i_2603
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[131] along load instance corei_7/i_3862 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[130] along load instance corei_7/i_2609
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[130] along load instance corei_7/i_2611
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[130] along load instance corei_7/i_3873 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[129] along load instance corei_7/i_2614
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[129] along load instance corei_7/i_2618
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[129] along load instance corei_7/i_3878 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[128] along load instance corei_7/i_2622
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[128] along load instance corei_7/i_2626
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[128] along load instance corei_7/i_3891 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[127] along load instance corei_7/i_2633
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[127] along load instance corei_7/i_2635
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[127] along load instance corei_7/i_3899 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[126] along load instance corei_7/i_3907 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[126] along load instance corei_7/i_5666 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[126] along load instance corei_7/i_5667 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[70] along load instance corei_7/i_2910
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[70] along load instance corei_7/i_2913 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[70] along load instance corei_7/i_6002 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[70] along load instance corei_7/i_6005 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[69] along load instance corei_7/i_2922
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[69] along load instance corei_7/i_2923 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[69] along load instance corei_7/i_6010 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[69] along load instance corei_7/i_6014 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[68] along load instance corei_7/i_2926
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[68] along load instance corei_7/i_2929 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[68] along load instance corei_7/i_6022 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[68] along load instance corei_7/i_6023 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[67] along load instance corei_7/i_2934 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[67] along load instance corei_7/i_2938 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[67] along load instance corei_7/i_6029 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[67] along load instance corei_7/i_6031 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[66] along load instance corei_7/i_2942
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[66] along load instance corei_7/i_2945 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[66] along load instance corei_7/i_6034 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[66] along load instance corei_7/i_6038 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[65] along load instance corei_7/i_2950 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[65] along load instance corei_7/i_2954 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[65] along load instance corei_7/i_6042 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[65] along load instance corei_7/i_6046 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[64] along load instance corei_7/i_2958 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[64] along load instance corei_7/i_2962 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[64] along load instance corei_7/i_6054 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[64] along load instance corei_7/i_6055 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[63] along load instance corei_7/i_2966 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[63] along load instance corei_7/i_2970 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[63] along load instance corei_7/i_6058 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[63] along load instance corei_7/i_6061 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[62] along load instance corei_7/i_2846
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[62] along load instance corei_7/i_2849 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[62] along load instance corei_7/i_6066 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[62] along load instance corei_7/i_6069 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[61] along load instance corei_7/i_2857
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[61] along load instance corei_7/i_2859 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[61] along load instance corei_7/i_6074 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[61] along load instance corei_7/i_6078 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[60] along load instance corei_7/i_2862 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[60] along load instance corei_7/i_2866 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[60] along load instance corei_7/i_6082 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[60] along load instance corei_7/i_6086 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[59] along load instance corei_7/i_2870 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[59] along load instance corei_7/i_2874 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[59] along load instance corei_7/i_6090 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[59] along load instance corei_7/i_6094 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[58] along load instance corei_7/i_2878 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[58] along load instance corei_7/i_2882 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[58] along load instance corei_7/i_6102 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[58] along load instance corei_7/i_6103 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[57] along load instance corei_7/i_2886
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[57] along load instance corei_7/i_2889 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[57] along load instance corei_7/i_6106 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[57] along load instance corei_7/i_6109 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[56] along load instance corei_7/i_2897
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[56] along load instance corei_7/i_2899 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[56] along load instance corei_7/i_6114 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[56] along load instance corei_7/i_6118 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[55] along load instance corei_7/i_2902 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[55] along load instance corei_7/i_2906 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[55] along load instance corei_7/i_6122 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[55] along load instance corei_7/i_6126 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[54] along load instance corei_7/i_4345
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[54] along load instance corei_7/i_4347 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[54] along load instance corei_7/i_6130 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_5_delay_1_reg[54] along load instance corei_7/i_6134 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[286] along load instance corei_7/i_2235
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[286] along load instance corei_7/i_2990
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[286] along load instance corei_7/i_2994
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[285] along load instance corei_7/i_2243
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[285] along load instance corei_7/i_3002
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[285] along load instance corei_7/i_3003
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[284] along load instance corei_7/i_2249
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[284] along load instance corei_7/i_3009
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[284] along load instance corei_7/i_3011
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[283] along load instance corei_7/i_2259
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[283] along load instance corei_7/i_3018
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[283] along load instance corei_7/i_3019
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[282] along load instance corei_7/i_2267
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[282] along load instance corei_7/i_3026
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[282] along load instance corei_7/i_3027
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[281] along load instance corei_7/i_2270
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[281] along load instance corei_7/i_3033
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[281] along load instance corei_7/i_3035
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[280] along load instance corei_7/i_2278
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[280] along load instance corei_7/i_3042
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[280] along load instance corei_7/i_3043
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[279] along load instance corei_7/i_2286
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[279] along load instance corei_7/i_3046
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[279] along load instance corei_7/i_3050
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[278] along load instance corei_7/i_2169
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[278] along load instance corei_7/i_3054
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[278] along load instance corei_7/i_3058
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[277] along load instance corei_7/i_2177
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[277] along load instance corei_7/i_3062
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[277] along load instance corei_7/i_3066
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[276] along load instance corei_7/i_2182
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[276] along load instance corei_7/i_3073
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[276] along load instance corei_7/i_3075
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[275] along load instance corei_7/i_2190
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[275] along load instance corei_7/i_3078
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[275] along load instance corei_7/i_3082
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[274] along load instance corei_7/i_2203
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[274] along load instance corei_7/i_3086
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[274] along load instance corei_7/i_3089
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[273] along load instance corei_7/i_2211
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[273] along load instance corei_7/i_3098
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[273] along load instance corei_7/i_3099
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[272] along load instance corei_7/i_2214
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[272] along load instance corei_7/i_3102
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[272] along load instance corei_7/i_3105
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[271] along load instance corei_7/i_2225
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[271] along load instance corei_7/i_3110
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[271] along load instance corei_7/i_3114
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[270] along load instance corei_7/i_3118
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[270] along load instance corei_7/i_3122
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[270] along load instance corei_7/i_4782
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[250] along load instance corei_7/i_4942
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[250] along load instance corei_7/i_4945 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[249] along load instance corei_7/i_4950
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[249] along load instance corei_7/i_4953 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[248] along load instance corei_7/i_4958
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[248] along load instance corei_7/i_4961 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[247] along load instance corei_7/i_4970 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[247] along load instance corei_7/i_4971 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[246] along load instance corei_7/i_4974
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[246] along load instance corei_7/i_4977 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[245] along load instance corei_7/i_4982
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[245] along load instance corei_7/i_4985 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[244] along load instance corei_7/i_4994 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[244] along load instance corei_7/i_4995 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[243] along load instance corei_7/i_4998
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[243] along load instance corei_7/i_5001 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[242] along load instance corei_7/i_5006
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[242] along load instance corei_7/i_5009 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[241] along load instance corei_7/i_5017
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[241] along load instance corei_7/i_5018 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[240] along load instance corei_7/i_5026 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[240] along load instance corei_7/i_5027 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[239] along load instance corei_7/i_5034 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[239] along load instance corei_7/i_5035 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[238] along load instance corei_7/i_5038
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[238] along load instance corei_7/i_5041 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[237] along load instance corei_7/i_5046
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[237] along load instance corei_7/i_5049 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[236] along load instance corei_7/i_5058 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[236] along load instance corei_7/i_5059 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[235] along load instance corei_7/i_5066 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[235] along load instance corei_7/i_5067 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[234] along load instance corei_7/i_5073
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[234] along load instance corei_7/i_5074 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[214] along load instance corei_7/i_2366
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[214] along load instance corei_7/i_2370
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[214] along load instance corei_7/i_5230
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[213] along load instance corei_7/i_2377
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[213] along load instance corei_7/i_2379
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[213] along load instance corei_7/i_5238
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[212] along load instance corei_7/i_2382
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[212] along load instance corei_7/i_2386
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[212] along load instance corei_7/i_5251
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[211] along load instance corei_7/i_2390
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[211] along load instance corei_7/i_2394
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[211] along load instance corei_7/i_5254
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[210] along load instance corei_7/i_2401
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[210] along load instance corei_7/i_2403
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[210] along load instance corei_7/i_5262
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[209] along load instance corei_7/i_2410
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[209] along load instance corei_7/i_2411
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[209] along load instance corei_7/i_5273
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[208] along load instance corei_7/i_2417
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[208] along load instance corei_7/i_2419
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[208] along load instance corei_7/i_5283
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[207] along load instance corei_7/i_2425
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[207] along load instance corei_7/i_2427
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[207] along load instance corei_7/i_5291
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[206] along load instance corei_7/i_2305
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[206] along load instance corei_7/i_2307
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[206] along load instance corei_7/i_5294
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[205] along load instance corei_7/i_2314
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[205] along load instance corei_7/i_2315
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[205] along load instance corei_7/i_5302
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[204] along load instance corei_7/i_2318
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[204] along load instance corei_7/i_2322
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[204] along load instance corei_7/i_5315
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[203] along load instance corei_7/i_2326
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[203] along load instance corei_7/i_2330
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[203] along load instance corei_7/i_5323
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[202] along load instance corei_7/i_2337
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[202] along load instance corei_7/i_2339
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[202] along load instance corei_7/i_5329
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[201] along load instance corei_7/i_2346
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[201] along load instance corei_7/i_2347
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[201] along load instance corei_7/i_5337
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[200] along load instance corei_7/i_2353
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[200] along load instance corei_7/i_2355
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[200] along load instance corei_7/i_5345
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[199] along load instance corei_7/i_2358
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[199] along load instance corei_7/i_2362
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[199] along load instance corei_7/i_5355
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[198] along load instance corei_7/i_3462
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[198] along load instance corei_7/i_3466
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[198] along load instance corei_7/i_5358
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[142] along load instance corei_7/i_2638
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[142] along load instance corei_7/i_2641 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[142] along load instance corei_7/i_3774 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[141] along load instance corei_7/i_2646
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[141] along load instance corei_7/i_2649 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[141] along load instance corei_7/i_3787 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[140] along load instance corei_7/i_2658 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[140] along load instance corei_7/i_2659 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[140] along load instance corei_7/i_3795 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[139] along load instance corei_7/i_2666 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[139] along load instance corei_7/i_2667 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[139] along load instance corei_7/i_3803 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[138] along load instance corei_7/i_2674 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[138] along load instance corei_7/i_2675 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[138] along load instance corei_7/i_3811 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[137] along load instance corei_7/i_2678 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[137] along load instance corei_7/i_2683 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[137] along load instance corei_7/i_3819 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[136] along load instance corei_7/i_2686 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[136] along load instance corei_7/i_2691 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[136] along load instance corei_7/i_3827 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[135] along load instance corei_7/i_2698 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[135] along load instance corei_7/i_2699 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[135] along load instance corei_7/i_3830 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[134] along load instance corei_7/i_2574
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[134] along load instance corei_7/i_2577 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[134] along load instance corei_7/i_3838 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[133] along load instance corei_7/i_2582
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[133] along load instance corei_7/i_2585 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[133] along load instance corei_7/i_3846 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[132] along load instance corei_7/i_2594 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[132] along load instance corei_7/i_2595 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[132] along load instance corei_7/i_3859 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[131] along load instance corei_7/i_2602 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[131] along load instance corei_7/i_2603 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[131] along load instance corei_7/i_3862 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[130] along load instance corei_7/i_2610 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[130] along load instance corei_7/i_2611 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[130] along load instance corei_7/i_3873 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[129] along load instance corei_7/i_2614
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[129] along load instance corei_7/i_2617 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[129] along load instance corei_7/i_3878 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[128] along load instance corei_7/i_2622
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[128] along load instance corei_7/i_2625 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[128] along load instance corei_7/i_3891 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[127] along load instance corei_7/i_2634 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[127] along load instance corei_7/i_2635 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[127] along load instance corei_7/i_3899 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[126] along load instance corei_7/i_3907
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[126] along load instance corei_7/i_5662 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[126] along load instance corei_7/i_5667 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[70] along load instance corei_7/i_2910
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[70] along load instance corei_7/i_2913
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[70] along load instance corei_7/i_6005
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[70] along load instance corei_7/i_6006 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[69] along load instance corei_7/i_2922
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[69] along load instance corei_7/i_2923
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[69] along load instance corei_7/i_6010
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[69] along load instance corei_7/i_6013 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[68] along load instance corei_7/i_2926
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[68] along load instance corei_7/i_2929
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[68] along load instance corei_7/i_6018 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[68] along load instance corei_7/i_6023 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[67] along load instance corei_7/i_2934
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[67] along load instance corei_7/i_2938
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[67] along load instance corei_7/i_6030 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[67] along load instance corei_7/i_6031 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[66] along load instance corei_7/i_2942
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[66] along load instance corei_7/i_2945
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[66] along load instance corei_7/i_6034
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[66] along load instance corei_7/i_6037 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[65] along load instance corei_7/i_2950
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[65] along load instance corei_7/i_2954
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[65] along load instance corei_7/i_6042
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[65] along load instance corei_7/i_6045 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[64] along load instance corei_7/i_2958
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[64] along load instance corei_7/i_2962
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[64] along load instance corei_7/i_6050 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[64] along load instance corei_7/i_6055 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[63] along load instance corei_7/i_2966
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[63] along load instance corei_7/i_2970
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[63] along load instance corei_7/i_6061
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[63] along load instance corei_7/i_6062 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[62] along load instance corei_7/i_2846
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[62] along load instance corei_7/i_2849
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[62] along load instance corei_7/i_6069
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[62] along load instance corei_7/i_6070 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[61] along load instance corei_7/i_2857
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[61] along load instance corei_7/i_2859
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[61] along load instance corei_7/i_6074
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[61] along load instance corei_7/i_6077 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[60] along load instance corei_7/i_2862
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[60] along load instance corei_7/i_2866
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[60] along load instance corei_7/i_6082
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[60] along load instance corei_7/i_6085 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[59] along load instance corei_7/i_2870
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[59] along load instance corei_7/i_2874
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[59] along load instance corei_7/i_6090
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[59] along load instance corei_7/i_6093 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[58] along load instance corei_7/i_2878
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[58] along load instance corei_7/i_2882
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[58] along load instance corei_7/i_6098 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[58] along load instance corei_7/i_6103 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[57] along load instance corei_7/i_2886
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[57] along load instance corei_7/i_2889
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[57] along load instance corei_7/i_6109
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[57] along load instance corei_7/i_6110 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[56] along load instance corei_7/i_2897
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[56] along load instance corei_7/i_2899
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[56] along load instance corei_7/i_6114
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[56] along load instance corei_7/i_6117 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[55] along load instance corei_7/i_2902
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[55] along load instance corei_7/i_2906
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[55] along load instance corei_7/i_6122
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[55] along load instance corei_7/i_6125 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[54] along load instance corei_7/i_4345
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[54] along load instance corei_7/i_4347
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[54] along load instance corei_7/i_6130
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_6_delay_1_reg[54] along load instance corei_7/i_6133 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[286] along load instance corei_7/i_2230 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[286] along load instance corei_7/i_2233 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[286] along load instance corei_7/i_2993 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[286] along load instance corei_7/i_2995 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[285] along load instance corei_7/i_2238
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[285] along load instance corei_7/i_2242 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[285] along load instance corei_7/i_2998 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[285] along load instance corei_7/i_3001 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[284] along load instance corei_7/i_2250 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[284] along load instance corei_7/i_2251 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[284] along load instance corei_7/i_3006 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[284] along load instance corei_7/i_3010 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[283] along load instance corei_7/i_2254
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[283] along load instance corei_7/i_2258 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[283] along load instance corei_7/i_3014 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[283] along load instance corei_7/i_3017 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[282] along load instance corei_7/i_2262 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[282] along load instance corei_7/i_2265 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[282] along load instance corei_7/i_3022 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[282] along load instance corei_7/i_3025 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[281] along load instance corei_7/i_2273 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[281] along load instance corei_7/i_2275 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[281] along load instance corei_7/i_3030 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[281] along load instance corei_7/i_3034 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[280] along load instance corei_7/i_2281 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[280] along load instance corei_7/i_2283 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[280] along load instance corei_7/i_3038 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[280] along load instance corei_7/i_3041 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[279] along load instance corei_7/i_2289 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[279] along load instance corei_7/i_2291 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[279] along load instance corei_7/i_3049 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[279] along load instance corei_7/i_3051 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[278] along load instance corei_7/i_2170 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[278] along load instance corei_7/i_2171 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[278] along load instance corei_7/i_3057 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[278] along load instance corei_7/i_3059 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[277] along load instance corei_7/i_2178 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[277] along load instance corei_7/i_2179 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[277] along load instance corei_7/i_3065 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[277] along load instance corei_7/i_3067 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[276] along load instance corei_7/i_2185 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[276] along load instance corei_7/i_2187 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[276] along load instance corei_7/i_3070 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[276] along load instance corei_7/i_3074 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[275] along load instance corei_7/i_2193 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[275] along load instance corei_7/i_2195 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[275] along load instance corei_7/i_3081 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[275] along load instance corei_7/i_3083 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[274] along load instance corei_7/i_2198
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[274] along load instance corei_7/i_2202 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[274] along load instance corei_7/i_3090 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[274] along load instance corei_7/i_3091 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[273] along load instance corei_7/i_2206
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[273] along load instance corei_7/i_2210 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[273] along load instance corei_7/i_3094 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[273] along load instance corei_7/i_3097 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[272] along load instance corei_7/i_2217 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[272] along load instance corei_7/i_2219 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[272] along load instance corei_7/i_3106 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[272] along load instance corei_7/i_3107 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[271] along load instance corei_7/i_2226 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[271] along load instance corei_7/i_2227 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[271] along load instance corei_7/i_3113 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[271] along load instance corei_7/i_3115 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[270] along load instance corei_7/i_3121 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[270] along load instance corei_7/i_3123 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[270] along load instance corei_7/i_4785 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[270] along load instance corei_7/i_4787 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[250] along load instance corei_7/i_4945
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[250] along load instance corei_7/i_4947
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[249] along load instance corei_7/i_4953
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[249] along load instance corei_7/i_4955
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[248] along load instance corei_7/i_4961
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[248] along load instance corei_7/i_4963
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[247] along load instance corei_7/i_4966
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[247] along load instance corei_7/i_4970
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[246] along load instance corei_7/i_4977
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[246] along load instance corei_7/i_4979
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[245] along load instance corei_7/i_4985
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[245] along load instance corei_7/i_4987
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[244] along load instance corei_7/i_4990
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[244] along load instance corei_7/i_4994
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[243] along load instance corei_7/i_5001
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[243] along load instance corei_7/i_5003
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[242] along load instance corei_7/i_5009
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[242] along load instance corei_7/i_5011
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[241] along load instance corei_7/i_5018
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[241] along load instance corei_7/i_5019
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[240] along load instance corei_7/i_5022
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[240] along load instance corei_7/i_5026
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[239] along load instance corei_7/i_5030
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[239] along load instance corei_7/i_5034
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[238] along load instance corei_7/i_5041
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[238] along load instance corei_7/i_5043
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[237] along load instance corei_7/i_5049
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[237] along load instance corei_7/i_5051
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[236] along load instance corei_7/i_5054
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[236] along load instance corei_7/i_5058
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[235] along load instance corei_7/i_5062
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[235] along load instance corei_7/i_5066
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[234] along load instance corei_7/i_5074
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[234] along load instance corei_7/i_5075
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[214] along load instance corei_7/i_2369 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[214] along load instance corei_7/i_2371 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[214] along load instance corei_7/i_5235 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[213] along load instance corei_7/i_2374
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[213] along load instance corei_7/i_2378 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[213] along load instance corei_7/i_5243 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[212] along load instance corei_7/i_2385 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[212] along load instance corei_7/i_2387 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[212] along load instance corei_7/i_5246 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[211] along load instance corei_7/i_2393 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[211] along load instance corei_7/i_2395 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[211] along load instance corei_7/i_5259 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[210] along load instance corei_7/i_2398
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[210] along load instance corei_7/i_2402 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[210] along load instance corei_7/i_5267 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[209] along load instance corei_7/i_2406 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[209] along load instance corei_7/i_2409 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[209] along load instance corei_7/i_5275 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[208] along load instance corei_7/i_2414
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[208] along load instance corei_7/i_2418 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[208] along load instance corei_7/i_5278 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[207] along load instance corei_7/i_2422
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[207] along load instance corei_7/i_2426 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[207] along load instance corei_7/i_5286 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[206] along load instance corei_7/i_2302
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[206] along load instance corei_7/i_2306 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[206] along load instance corei_7/i_5299 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[205] along load instance corei_7/i_2310 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[205] along load instance corei_7/i_2313 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[205] along load instance corei_7/i_5307 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[204] along load instance corei_7/i_2321 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[204] along load instance corei_7/i_2323 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[204] along load instance corei_7/i_5310 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[203] along load instance corei_7/i_2329 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[203] along load instance corei_7/i_2331 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[203] along load instance corei_7/i_5318 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[202] along load instance corei_7/i_2334
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[202] along load instance corei_7/i_2338 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[202] along load instance corei_7/i_5331 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[201] along load instance corei_7/i_2342 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[201] along load instance corei_7/i_2345 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[201] along load instance corei_7/i_5339 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[200] along load instance corei_7/i_2350
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[200] along load instance corei_7/i_2354 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[200] along load instance corei_7/i_5347 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[199] along load instance corei_7/i_2361 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[199] along load instance corei_7/i_2363 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[199] along load instance corei_7/i_5350 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[198] along load instance corei_7/i_3465 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[198] along load instance corei_7/i_3467 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[198] along load instance corei_7/i_5363 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[142] along load instance corei_7/i_2641
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[142] along load instance corei_7/i_2643
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[142] along load instance corei_7/i_3779
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[141] along load instance corei_7/i_2649
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[141] along load instance corei_7/i_2651
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[141] along load instance corei_7/i_3782
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[140] along load instance corei_7/i_2654
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[140] along load instance corei_7/i_2658
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[140] along load instance corei_7/i_3790
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[139] along load instance corei_7/i_2662
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[139] along load instance corei_7/i_2666
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[139] along load instance corei_7/i_3798
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[138] along load instance corei_7/i_2670
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[138] along load instance corei_7/i_2674
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[138] along load instance corei_7/i_3809
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[137] along load instance corei_7/i_2678
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[137] along load instance corei_7/i_2681
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[137] along load instance corei_7/i_3814
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[136] along load instance corei_7/i_2686
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[136] along load instance corei_7/i_2689
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[136] along load instance corei_7/i_3822
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[135] along load instance corei_7/i_2694
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[135] along load instance corei_7/i_2698
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[135] along load instance corei_7/i_3835
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[134] along load instance corei_7/i_2577
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[134] along load instance corei_7/i_2579
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[134] along load instance corei_7/i_3843
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[133] along load instance corei_7/i_2585
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[133] along load instance corei_7/i_2587
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[133] along load instance corei_7/i_3851
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[132] along load instance corei_7/i_2590
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[132] along load instance corei_7/i_2594
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[132] along load instance corei_7/i_3854
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[131] along load instance corei_7/i_2598
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[131] along load instance corei_7/i_2602
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[131] along load instance corei_7/i_3867
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[130] along load instance corei_7/i_2606
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[130] along load instance corei_7/i_2610
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[130] along load instance corei_7/i_3875
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[129] along load instance corei_7/i_2617
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[129] along load instance corei_7/i_2619
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[129] along load instance corei_7/i_3883
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[128] along load instance corei_7/i_2625
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[128] along load instance corei_7/i_2627
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[128] along load instance corei_7/i_3886
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[127] along load instance corei_7/i_2630
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[127] along load instance corei_7/i_2634
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[127] along load instance corei_7/i_3894
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[126] along load instance corei_7/i_3905
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[126] along load instance corei_7/i_5662
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[126] along load instance corei_7/i_5665
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[70] along load instance corei_7/i_2914 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[70] along load instance corei_7/i_2915 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[70] along load instance corei_7/i_6006 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[70] along load instance corei_7/i_6007 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[69] along load instance corei_7/i_2918 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[69] along load instance corei_7/i_2921 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[69] along load instance corei_7/i_6013 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[69] along load instance corei_7/i_6015 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[68] along load instance corei_7/i_2930 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[68] along load instance corei_7/i_2931 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[68] along load instance corei_7/i_6018 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[68] along load instance corei_7/i_6021 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[67] along load instance corei_7/i_2937 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[67] along load instance corei_7/i_2939 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[67] along load instance corei_7/i_6026 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[67] along load instance corei_7/i_6030 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[66] along load instance corei_7/i_2946 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[66] along load instance corei_7/i_2947 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[66] along load instance corei_7/i_6037 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[66] along load instance corei_7/i_6039 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[65] along load instance corei_7/i_2953 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[65] along load instance corei_7/i_2955 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[65] along load instance corei_7/i_6045 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[65] along load instance corei_7/i_6047 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[64] along load instance corei_7/i_2961 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[64] along load instance corei_7/i_2963 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[64] along load instance corei_7/i_6050 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[64] along load instance corei_7/i_6053 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[63] along load instance corei_7/i_2969 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[63] along load instance corei_7/i_2971 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[63] along load instance corei_7/i_6062 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[63] along load instance corei_7/i_6063 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[62] along load instance corei_7/i_2850 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[62] along load instance corei_7/i_2851 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[62] along load instance corei_7/i_6070 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[62] along load instance corei_7/i_6071 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[61] along load instance corei_7/i_2854
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[61] along load instance corei_7/i_2858 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[61] along load instance corei_7/i_6077 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[61] along load instance corei_7/i_6079 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[60] along load instance corei_7/i_2865 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[60] along load instance corei_7/i_2867 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[60] along load instance corei_7/i_6085 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[60] along load instance corei_7/i_6087 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[59] along load instance corei_7/i_2873 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[59] along load instance corei_7/i_2875 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[59] along load instance corei_7/i_6093 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[59] along load instance corei_7/i_6095 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[58] along load instance corei_7/i_2881 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[58] along load instance corei_7/i_2883 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[58] along load instance corei_7/i_6098 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[58] along load instance corei_7/i_6101 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[57] along load instance corei_7/i_2890 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[57] along load instance corei_7/i_2891 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[57] along load instance corei_7/i_6110 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[57] along load instance corei_7/i_6111 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[56] along load instance corei_7/i_2894
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[56] along load instance corei_7/i_2898 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[56] along load instance corei_7/i_6117 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[56] along load instance corei_7/i_6119 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[55] along load instance corei_7/i_2905 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[55] along load instance corei_7/i_2907 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[55] along load instance corei_7/i_6125 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[55] along load instance corei_7/i_6127 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[54] along load instance corei_7/i_4342
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[54] along load instance corei_7/i_4346 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[54] along load instance corei_7/i_6133 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_1_delay_1_reg[54] along load instance corei_7/i_6135 due to (UNCOMPATIBLE REGISTERS)
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[286] along load instance corei_7/i_2233
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[286] along load instance corei_7/i_2234
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[286] along load instance corei_7/i_2993
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[286] along load instance corei_7/i_2995
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[285] along load instance corei_7/i_2238
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[285] along load instance corei_7/i_2241
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[285] along load instance corei_7/i_2998
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[285] along load instance corei_7/i_3001
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[284] along load instance corei_7/i_2246
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[284] along load instance corei_7/i_2251
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[284] along load instance corei_7/i_3006
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[284] along load instance corei_7/i_3010
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[283] along load instance corei_7/i_2254
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[283] along load instance corei_7/i_2257
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[283] along load instance corei_7/i_3014
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[283] along load instance corei_7/i_3017
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[282] along load instance corei_7/i_2265
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[282] along load instance corei_7/i_2266
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[282] along load instance corei_7/i_3022
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[282] along load instance corei_7/i_3025
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[281] along load instance corei_7/i_2274
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[281] along load instance corei_7/i_2275
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[281] along load instance corei_7/i_3030
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[281] along load instance corei_7/i_3034
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[280] along load instance corei_7/i_2282
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[280] along load instance corei_7/i_2283
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[280] along load instance corei_7/i_3038
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[280] along load instance corei_7/i_3041
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[279] along load instance corei_7/i_2290
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[279] along load instance corei_7/i_2291
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[279] along load instance corei_7/i_3049
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[279] along load instance corei_7/i_3051
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[278] along load instance corei_7/i_2166
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[278] along load instance corei_7/i_2171
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[278] along load instance corei_7/i_3057
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[278] along load instance corei_7/i_3059
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[277] along load instance corei_7/i_2174
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[277] along load instance corei_7/i_2179
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[277] along load instance corei_7/i_3065
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[277] along load instance corei_7/i_3067
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[276] along load instance corei_7/i_2186
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[276] along load instance corei_7/i_2187
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[276] along load instance corei_7/i_3070
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[276] along load instance corei_7/i_3074
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[275] along load instance corei_7/i_2194
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[275] along load instance corei_7/i_2195
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[275] along load instance corei_7/i_3081
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[275] along load instance corei_7/i_3083
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[274] along load instance corei_7/i_2198
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[274] along load instance corei_7/i_2201
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[274] along load instance corei_7/i_3090
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[274] along load instance corei_7/i_3091
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[273] along load instance corei_7/i_2206
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[273] along load instance corei_7/i_2209
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[273] along load instance corei_7/i_3094
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[273] along load instance corei_7/i_3097
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[272] along load instance corei_7/i_2218
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[272] along load instance corei_7/i_2219
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[272] along load instance corei_7/i_3106
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[272] along load instance corei_7/i_3107
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[271] along load instance corei_7/i_2222
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[271] along load instance corei_7/i_2227
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[271] along load instance corei_7/i_3113
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[271] along load instance corei_7/i_3115
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[270] along load instance corei_7/i_3121
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[270] along load instance corei_7/i_3123
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[270] along load instance corei_7/i_4786
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[270] along load instance corei_7/i_4787
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[250] along load instance corei_7/i_4946
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[250] along load instance corei_7/i_4947
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[249] along load instance corei_7/i_4954
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[249] along load instance corei_7/i_4955
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[248] along load instance corei_7/i_4962
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[248] along load instance corei_7/i_4963
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[247] along load instance corei_7/i_4966
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[247] along load instance corei_7/i_4969
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[246] along load instance corei_7/i_4978
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[246] along load instance corei_7/i_4979
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[245] along load instance corei_7/i_4986
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[245] along load instance corei_7/i_4987
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[244] along load instance corei_7/i_4990
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[244] along load instance corei_7/i_4993
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[243] along load instance corei_7/i_5002
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[243] along load instance corei_7/i_5003
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[242] along load instance corei_7/i_5010
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[242] along load instance corei_7/i_5011
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[241] along load instance corei_7/i_5014
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[241] along load instance corei_7/i_5019
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[240] along load instance corei_7/i_5022
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[240] along load instance corei_7/i_5025
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[239] along load instance corei_7/i_5030
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[239] along load instance corei_7/i_5033
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[238] along load instance corei_7/i_5042
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[238] along load instance corei_7/i_5043
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[237] along load instance corei_7/i_5050
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[237] along load instance corei_7/i_5051
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[236] along load instance corei_7/i_5054
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[236] along load instance corei_7/i_5057
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[235] along load instance corei_7/i_5062
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[235] along load instance corei_7/i_5065
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[234] along load instance corei_7/i_5070
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[234] along load instance corei_7/i_5075
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[214] along load instance corei_7/i_2369
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[214] along load instance corei_7/i_2371
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[214] along load instance corei_7/i_5235
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[213] along load instance corei_7/i_2374
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[213] along load instance corei_7/i_2378
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[213] along load instance corei_7/i_5243
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[212] along load instance corei_7/i_2385
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[212] along load instance corei_7/i_2387
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[212] along load instance corei_7/i_5246
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[211] along load instance corei_7/i_2393
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[211] along load instance corei_7/i_2395
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[211] along load instance corei_7/i_5259
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[210] along load instance corei_7/i_2398
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[210] along load instance corei_7/i_2402
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[210] along load instance corei_7/i_5267
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[209] along load instance corei_7/i_2406
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[209] along load instance corei_7/i_2409
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[209] along load instance corei_7/i_5275
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[208] along load instance corei_7/i_2414
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[208] along load instance corei_7/i_2418
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[208] along load instance corei_7/i_5278
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[207] along load instance corei_7/i_2422
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[207] along load instance corei_7/i_2426
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[207] along load instance corei_7/i_5286
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[206] along load instance corei_7/i_2302
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[206] along load instance corei_7/i_2306
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[206] along load instance corei_7/i_5299
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[205] along load instance corei_7/i_2310
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[205] along load instance corei_7/i_2313
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[205] along load instance corei_7/i_5307
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[204] along load instance corei_7/i_2321
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[204] along load instance corei_7/i_2323
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[204] along load instance corei_7/i_5310
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[203] along load instance corei_7/i_2329
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[203] along load instance corei_7/i_2331
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[203] along load instance corei_7/i_5318
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[202] along load instance corei_7/i_2334
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[202] along load instance corei_7/i_2338
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[202] along load instance corei_7/i_5331
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[201] along load instance corei_7/i_2342
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[201] along load instance corei_7/i_2345
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[201] along load instance corei_7/i_5339
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[200] along load instance corei_7/i_2350
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[200] along load instance corei_7/i_2354
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[200] along load instance corei_7/i_5347
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[199] along load instance corei_7/i_2361
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[199] along load instance corei_7/i_2363
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[199] along load instance corei_7/i_5350
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[198] along load instance corei_7/i_3465
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[198] along load instance corei_7/i_3467
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[198] along load instance corei_7/i_5363
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[142] along load instance corei_7/i_2642
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[142] along load instance corei_7/i_2643
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[142] along load instance corei_7/i_3779
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[141] along load instance corei_7/i_2650
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[141] along load instance corei_7/i_2651
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[141] along load instance corei_7/i_3782
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[140] along load instance corei_7/i_2654
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[140] along load instance corei_7/i_2657
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[140] along load instance corei_7/i_3790
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[139] along load instance corei_7/i_2662
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[139] along load instance corei_7/i_2665
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[139] along load instance corei_7/i_3798
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[138] along load instance corei_7/i_2670
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[138] along load instance corei_7/i_2673
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[138] along load instance corei_7/i_3809
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[137] along load instance corei_7/i_2681
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[137] along load instance corei_7/i_2682
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[137] along load instance corei_7/i_3814
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[136] along load instance corei_7/i_2689
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[136] along load instance corei_7/i_2690
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[136] along load instance corei_7/i_3822
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[135] along load instance corei_7/i_2694
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[135] along load instance corei_7/i_2697
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[135] along load instance corei_7/i_3835
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[134] along load instance corei_7/i_2578
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[134] along load instance corei_7/i_2579
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[134] along load instance corei_7/i_3843
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[133] along load instance corei_7/i_2586
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[133] along load instance corei_7/i_2587
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[133] along load instance corei_7/i_3851
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[132] along load instance corei_7/i_2590
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[132] along load instance corei_7/i_2593
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[132] along load instance corei_7/i_3854
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[131] along load instance corei_7/i_2598
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[131] along load instance corei_7/i_2601
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[131] along load instance corei_7/i_3867
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[130] along load instance corei_7/i_2606
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[130] along load instance corei_7/i_2609
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[130] along load instance corei_7/i_3875
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[129] along load instance corei_7/i_2618
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[129] along load instance corei_7/i_2619
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[129] along load instance corei_7/i_3883
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[128] along load instance corei_7/i_2626
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[128] along load instance corei_7/i_2627
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[128] along load instance corei_7/i_3886
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[127] along load instance corei_7/i_2630
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[127] along load instance corei_7/i_2633
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[127] along load instance corei_7/i_3894
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[126] along load instance corei_7/i_3905
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[126] along load instance corei_7/i_5665
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[126] along load instance corei_7/i_5666
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[70] along load instance corei_7/i_2914
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[70] along load instance corei_7/i_2915
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[70] along load instance corei_7/i_6007
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[69] along load instance corei_7/i_2918
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[69] along load instance corei_7/i_2921
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[69] along load instance corei_7/i_6015
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[68] along load instance corei_7/i_2930
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[68] along load instance corei_7/i_2931
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[68] along load instance corei_7/i_6021
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[67] along load instance corei_7/i_2937
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[67] along load instance corei_7/i_2939
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[67] along load instance corei_7/i_6026
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[66] along load instance corei_7/i_2946
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[66] along load instance corei_7/i_2947
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[66] along load instance corei_7/i_6039
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[65] along load instance corei_7/i_2953
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[65] along load instance corei_7/i_2955
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[65] along load instance corei_7/i_6047
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[64] along load instance corei_7/i_2961
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[64] along load instance corei_7/i_2963
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[64] along load instance corei_7/i_6053
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[63] along load instance corei_7/i_2969
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[63] along load instance corei_7/i_2971
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[63] along load instance corei_7/i_6063
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[62] along load instance corei_7/i_2850
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[62] along load instance corei_7/i_2851
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[62] along load instance corei_7/i_6071
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[61] along load instance corei_7/i_2854
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[61] along load instance corei_7/i_2858
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[61] along load instance corei_7/i_6079
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[60] along load instance corei_7/i_2865
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[60] along load instance corei_7/i_2867
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[60] along load instance corei_7/i_6087
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[59] along load instance corei_7/i_2873
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[59] along load instance corei_7/i_2875
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[59] along load instance corei_7/i_6095
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[58] along load instance corei_7/i_2881
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[58] along load instance corei_7/i_2883
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[58] along load instance corei_7/i_6101
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[57] along load instance corei_7/i_2890
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[57] along load instance corei_7/i_2891
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[57] along load instance corei_7/i_6111
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[56] along load instance corei_7/i_2894
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[56] along load instance corei_7/i_2898
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[56] along load instance corei_7/i_6119
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[55] along load instance corei_7/i_2905
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[55] along load instance corei_7/i_2907
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[55] along load instance corei_7/i_6127
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[54] along load instance corei_7/i_4342
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[54] along load instance corei_7/i_4346
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_2_delay_1_reg[54] along load instance corei_7/i_6135
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[286] along load instance corei_7/i_2230
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[286] along load instance corei_7/i_2235
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[286] along load instance corei_7/i_2990
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[285] along load instance corei_7/i_2242
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[285] along load instance corei_7/i_2243
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[285] along load instance corei_7/i_3003
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[284] along load instance corei_7/i_2249
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[284] along load instance corei_7/i_2250
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[284] along load instance corei_7/i_3011
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[283] along load instance corei_7/i_2258
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[283] along load instance corei_7/i_2259
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[283] along load instance corei_7/i_3019
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[282] along load instance corei_7/i_2262
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[282] along load instance corei_7/i_2267
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[282] along load instance corei_7/i_3027
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[281] along load instance corei_7/i_2270
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[281] along load instance corei_7/i_2273
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[281] along load instance corei_7/i_3035
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[280] along load instance corei_7/i_2278
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[280] along load instance corei_7/i_2281
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[280] along load instance corei_7/i_3043
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[279] along load instance corei_7/i_2286
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[279] along load instance corei_7/i_2289
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[279] along load instance corei_7/i_3046
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[278] along load instance corei_7/i_2169
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[278] along load instance corei_7/i_2170
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[278] along load instance corei_7/i_3054
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[277] along load instance corei_7/i_2177
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[277] along load instance corei_7/i_2178
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[277] along load instance corei_7/i_3062
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[276] along load instance corei_7/i_2182
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[276] along load instance corei_7/i_2185
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[276] along load instance corei_7/i_3075
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[275] along load instance corei_7/i_2190
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[275] along load instance corei_7/i_2193
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[275] along load instance corei_7/i_3078
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[274] along load instance corei_7/i_2202
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[274] along load instance corei_7/i_2203
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[274] along load instance corei_7/i_3089
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[273] along load instance corei_7/i_2210
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[273] along load instance corei_7/i_2211
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[273] along load instance corei_7/i_3099
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[272] along load instance corei_7/i_2214
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[272] along load instance corei_7/i_2217
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[272] along load instance corei_7/i_3105
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[271] along load instance corei_7/i_2225
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[271] along load instance corei_7/i_2226
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[271] along load instance corei_7/i_3110
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[270] along load instance corei_7/i_3118
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[270] along load instance corei_7/i_4782
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[270] along load instance corei_7/i_4785
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[250] along load instance corei_7/i_4942
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[250] along load instance corei_7/i_4945
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[249] along load instance corei_7/i_4950
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[249] along load instance corei_7/i_4953
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[248] along load instance corei_7/i_4958
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[248] along load instance corei_7/i_4961
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[247] along load instance corei_7/i_4970
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[247] along load instance corei_7/i_4971
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[246] along load instance corei_7/i_4974
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[246] along load instance corei_7/i_4977
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[245] along load instance corei_7/i_4982
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[245] along load instance corei_7/i_4985
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[244] along load instance corei_7/i_4994
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[244] along load instance corei_7/i_4995
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[243] along load instance corei_7/i_4998
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[243] along load instance corei_7/i_5001
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[242] along load instance corei_7/i_5006
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[242] along load instance corei_7/i_5009
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[241] along load instance corei_7/i_5017
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[241] along load instance corei_7/i_5018
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[240] along load instance corei_7/i_5026
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[240] along load instance corei_7/i_5027
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[239] along load instance corei_7/i_5034
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[239] along load instance corei_7/i_5035
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[238] along load instance corei_7/i_5038
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[238] along load instance corei_7/i_5041
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[237] along load instance corei_7/i_5046
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[237] along load instance corei_7/i_5049
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[236] along load instance corei_7/i_5058
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[236] along load instance corei_7/i_5059
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[235] along load instance corei_7/i_5066
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[235] along load instance corei_7/i_5067
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[234] along load instance corei_7/i_5073
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[234] along load instance corei_7/i_5074
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[214] along load instance corei_7/i_2366
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[214] along load instance corei_7/i_5230
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[213] along load instance corei_7/i_2379
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[213] along load instance corei_7/i_5238
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[212] along load instance corei_7/i_2382
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[212] along load instance corei_7/i_5251
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[211] along load instance corei_7/i_2390
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[211] along load instance corei_7/i_5254
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[210] along load instance corei_7/i_2403
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[210] along load instance corei_7/i_5262
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[209] along load instance corei_7/i_2411
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[209] along load instance corei_7/i_5273
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[208] along load instance corei_7/i_2419
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[208] along load instance corei_7/i_5283
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[207] along load instance corei_7/i_2427
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[207] along load instance corei_7/i_5291
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[206] along load instance corei_7/i_2307
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[206] along load instance corei_7/i_5294
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[205] along load instance corei_7/i_2315
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[205] along load instance corei_7/i_5302
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[204] along load instance corei_7/i_2318
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[204] along load instance corei_7/i_5315
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[203] along load instance corei_7/i_2326
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[203] along load instance corei_7/i_5323
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[202] along load instance corei_7/i_2339
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[202] along load instance corei_7/i_5329
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[201] along load instance corei_7/i_2347
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[201] along load instance corei_7/i_5337
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[200] along load instance corei_7/i_2355
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[200] along load instance corei_7/i_5345
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[199] along load instance corei_7/i_2358
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[199] along load instance corei_7/i_5355
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[198] along load instance corei_7/i_3462
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[198] along load instance corei_7/i_5358
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[142] along load instance corei_7/i_2638
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[142] along load instance corei_7/i_2641
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[142] along load instance corei_7/i_3774
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[141] along load instance corei_7/i_2646
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[141] along load instance corei_7/i_2649
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[141] along load instance corei_7/i_3787
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[140] along load instance corei_7/i_2658
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[140] along load instance corei_7/i_2659
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[140] along load instance corei_7/i_3795
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[139] along load instance corei_7/i_2666
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[139] along load instance corei_7/i_2667
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[139] along load instance corei_7/i_3803
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[138] along load instance corei_7/i_2674
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[138] along load instance corei_7/i_2675
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[138] along load instance corei_7/i_3811
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[137] along load instance corei_7/i_2678
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[137] along load instance corei_7/i_2683
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[137] along load instance corei_7/i_3819
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[136] along load instance corei_7/i_2686
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[136] along load instance corei_7/i_2691
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[136] along load instance corei_7/i_3827
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[135] along load instance corei_7/i_2698
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[135] along load instance corei_7/i_2699
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[135] along load instance corei_7/i_3830
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[134] along load instance corei_7/i_2574
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[134] along load instance corei_7/i_2577
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[134] along load instance corei_7/i_3838
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[133] along load instance corei_7/i_2582
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[133] along load instance corei_7/i_2585
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[133] along load instance corei_7/i_3846
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[132] along load instance corei_7/i_2594
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[132] along load instance corei_7/i_2595
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[132] along load instance corei_7/i_3859
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[131] along load instance corei_7/i_2602
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[131] along load instance corei_7/i_2603
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[131] along load instance corei_7/i_3862
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[130] along load instance corei_7/i_2610
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[130] along load instance corei_7/i_2611
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[130] along load instance corei_7/i_3873
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[129] along load instance corei_7/i_2614
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[129] along load instance corei_7/i_2617
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[129] along load instance corei_7/i_3878
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[128] along load instance corei_7/i_2622
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[128] along load instance corei_7/i_2625
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[128] along load instance corei_7/i_3891
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[127] along load instance corei_7/i_2634
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[127] along load instance corei_7/i_2635
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[127] along load instance corei_7/i_3899
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[126] along load instance corei_7/i_3907
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[126] along load instance corei_7/i_5662
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[126] along load instance corei_7/i_5667
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[70] along load instance corei_7/i_2913
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[70] along load instance corei_7/i_2914
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[70] along load instance corei_7/i_6005
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[70] along load instance corei_7/i_6006
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[69] along load instance corei_7/i_2918
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[69] along load instance corei_7/i_2923
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[69] along load instance corei_7/i_6010
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[69] along load instance corei_7/i_6013
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[68] along load instance corei_7/i_2929
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[68] along load instance corei_7/i_2930
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[68] along load instance corei_7/i_6018
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[68] along load instance corei_7/i_6023
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[67] along load instance corei_7/i_2934
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[67] along load instance corei_7/i_2937
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[67] along load instance corei_7/i_6030
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[67] along load instance corei_7/i_6031
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[66] along load instance corei_7/i_2945
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[66] along load instance corei_7/i_2946
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[66] along load instance corei_7/i_6034
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[66] along load instance corei_7/i_6037
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[65] along load instance corei_7/i_2950
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[65] along load instance corei_7/i_2953
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[65] along load instance corei_7/i_6042
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[65] along load instance corei_7/i_6045
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[64] along load instance corei_7/i_2958
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[64] along load instance corei_7/i_2961
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[64] along load instance corei_7/i_6050
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[64] along load instance corei_7/i_6055
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[63] along load instance corei_7/i_2966
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[63] along load instance corei_7/i_2969
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[63] along load instance corei_7/i_6061
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[63] along load instance corei_7/i_6062
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[62] along load instance corei_7/i_2849
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[62] along load instance corei_7/i_2850
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[62] along load instance corei_7/i_6069
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[62] along load instance corei_7/i_6070
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[61] along load instance corei_7/i_2858
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[61] along load instance corei_7/i_2859
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[61] along load instance corei_7/i_6074
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[61] along load instance corei_7/i_6077
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[60] along load instance corei_7/i_2862
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[60] along load instance corei_7/i_2865
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[60] along load instance corei_7/i_6082
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[60] along load instance corei_7/i_6085
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[59] along load instance corei_7/i_2870
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[59] along load instance corei_7/i_2873
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[59] along load instance corei_7/i_6090
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[59] along load instance corei_7/i_6093
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[58] along load instance corei_7/i_2878
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[58] along load instance corei_7/i_2881
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[58] along load instance corei_7/i_6098
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[58] along load instance corei_7/i_6103
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[57] along load instance corei_7/i_2889
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[57] along load instance corei_7/i_2890
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[57] along load instance corei_7/i_6109
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[57] along load instance corei_7/i_6110
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[56] along load instance corei_7/i_2898
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[56] along load instance corei_7/i_2899
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[56] along load instance corei_7/i_6114
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[56] along load instance corei_7/i_6117
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[55] along load instance corei_7/i_2902
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[55] along load instance corei_7/i_2905
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[55] along load instance corei_7/i_6122
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[55] along load instance corei_7/i_6125
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[54] along load instance corei_7/i_4346
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[54] along load instance corei_7/i_4347
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[54] along load instance corei_7/i_6130
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_7_delay_1_reg[54] along load instance corei_7/i_6133
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[286] along load instance corei_7/i_2230
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[286] along load instance corei_7/i_2233
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[286] along load instance corei_7/i_2990
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[286] along load instance corei_7/i_2993
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[285] along load instance corei_7/i_2238
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[285] along load instance corei_7/i_2242
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[285] along load instance corei_7/i_2998
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[285] along load instance corei_7/i_3003
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[284] along load instance corei_7/i_2250
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[284] along load instance corei_7/i_2251
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[284] along load instance corei_7/i_3010
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[284] along load instance corei_7/i_3011
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[283] along load instance corei_7/i_2254
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[283] along load instance corei_7/i_2258
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[283] along load instance corei_7/i_3014
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[283] along load instance corei_7/i_3019
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[282] along load instance corei_7/i_2262
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[282] along load instance corei_7/i_2265
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[282] along load instance corei_7/i_3022
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[282] along load instance corei_7/i_3027
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[281] along load instance corei_7/i_2273
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[281] along load instance corei_7/i_2275
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[281] along load instance corei_7/i_3034
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[281] along load instance corei_7/i_3035
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[280] along load instance corei_7/i_2281
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[280] along load instance corei_7/i_2283
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[280] along load instance corei_7/i_3038
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[280] along load instance corei_7/i_3043
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[279] along load instance corei_7/i_2289
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[279] along load instance corei_7/i_2291
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[279] along load instance corei_7/i_3046
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[279] along load instance corei_7/i_3049
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[278] along load instance corei_7/i_2170
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[278] along load instance corei_7/i_2171
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[278] along load instance corei_7/i_3054
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[278] along load instance corei_7/i_3057
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[277] along load instance corei_7/i_2178
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[277] along load instance corei_7/i_2179
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[277] along load instance corei_7/i_3062
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[277] along load instance corei_7/i_3065
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[276] along load instance corei_7/i_2185
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[276] along load instance corei_7/i_2187
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[276] along load instance corei_7/i_3074
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[276] along load instance corei_7/i_3075
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[275] along load instance corei_7/i_2193
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[275] along load instance corei_7/i_2195
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[275] along load instance corei_7/i_3078
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[275] along load instance corei_7/i_3081
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[274] along load instance corei_7/i_2198
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[274] along load instance corei_7/i_2202
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[274] along load instance corei_7/i_3089
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[274] along load instance corei_7/i_3090
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[273] along load instance corei_7/i_2206
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[273] along load instance corei_7/i_2210
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[273] along load instance corei_7/i_3094
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[273] along load instance corei_7/i_3099
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[272] along load instance corei_7/i_2217
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[272] along load instance corei_7/i_2219
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[272] along load instance corei_7/i_3105
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[272] along load instance corei_7/i_3106
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[271] along load instance corei_7/i_2226
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[271] along load instance corei_7/i_2227
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[271] along load instance corei_7/i_3110
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[271] along load instance corei_7/i_3113
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[270] along load instance corei_7/i_3118
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[270] along load instance corei_7/i_3121
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[270] along load instance corei_7/i_4785
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[270] along load instance corei_7/i_4787
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[250] along load instance corei_7/i_4945
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[250] along load instance corei_7/i_4947
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[249] along load instance corei_7/i_4953
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[249] along load instance corei_7/i_4955
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[248] along load instance corei_7/i_4961
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[248] along load instance corei_7/i_4963
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[247] along load instance corei_7/i_4966
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[247] along load instance corei_7/i_4970
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[246] along load instance corei_7/i_4977
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[246] along load instance corei_7/i_4979
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[245] along load instance corei_7/i_4985
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[245] along load instance corei_7/i_4987
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[244] along load instance corei_7/i_4990
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[244] along load instance corei_7/i_4994
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[243] along load instance corei_7/i_5001
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[243] along load instance corei_7/i_5003
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[242] along load instance corei_7/i_5009
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[242] along load instance corei_7/i_5011
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[241] along load instance corei_7/i_5018
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[241] along load instance corei_7/i_5019
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[240] along load instance corei_7/i_5022
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[240] along load instance corei_7/i_5026
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[239] along load instance corei_7/i_5030
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[239] along load instance corei_7/i_5034
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[238] along load instance corei_7/i_5041
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[238] along load instance corei_7/i_5043
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[237] along load instance corei_7/i_5049
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[237] along load instance corei_7/i_5051
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[236] along load instance corei_7/i_5054
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[236] along load instance corei_7/i_5058
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[235] along load instance corei_7/i_5062
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[235] along load instance corei_7/i_5066
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[234] along load instance corei_7/i_5074
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[234] along load instance corei_7/i_5075
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[214] along load instance corei_7/i_2366
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[214] along load instance corei_7/i_2369
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[214] along load instance corei_7/i_5235
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[213] along load instance corei_7/i_2378
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[213] along load instance corei_7/i_2379
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[213] along load instance corei_7/i_5243
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[212] along load instance corei_7/i_2382
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[212] along load instance corei_7/i_2385
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[212] along load instance corei_7/i_5246
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[211] along load instance corei_7/i_2390
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[211] along load instance corei_7/i_2393
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[211] along load instance corei_7/i_5259
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[210] along load instance corei_7/i_2402
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[210] along load instance corei_7/i_2403
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[210] along load instance corei_7/i_5267
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[209] along load instance corei_7/i_2406
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[209] along load instance corei_7/i_2411
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[209] along load instance corei_7/i_5275
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[208] along load instance corei_7/i_2418
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[208] along load instance corei_7/i_2419
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[208] along load instance corei_7/i_5278
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[207] along load instance corei_7/i_2426
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[207] along load instance corei_7/i_2427
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[207] along load instance corei_7/i_5286
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[206] along load instance corei_7/i_2306
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[206] along load instance corei_7/i_2307
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[206] along load instance corei_7/i_5299
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[205] along load instance corei_7/i_2310
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[205] along load instance corei_7/i_2315
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[205] along load instance corei_7/i_5307
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[204] along load instance corei_7/i_2318
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[204] along load instance corei_7/i_2321
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[204] along load instance corei_7/i_5310
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[203] along load instance corei_7/i_2326
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[203] along load instance corei_7/i_2329
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[203] along load instance corei_7/i_5318
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[202] along load instance corei_7/i_2338
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[202] along load instance corei_7/i_2339
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[202] along load instance corei_7/i_5331
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[201] along load instance corei_7/i_2342
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[201] along load instance corei_7/i_2347
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[201] along load instance corei_7/i_5339
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[200] along load instance corei_7/i_2354
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[200] along load instance corei_7/i_2355
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[200] along load instance corei_7/i_5347
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[199] along load instance corei_7/i_2358
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[199] along load instance corei_7/i_2361
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[199] along load instance corei_7/i_5350
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[198] along load instance corei_7/i_3462
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[198] along load instance corei_7/i_3465
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[198] along load instance corei_7/i_5363
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[142] along load instance corei_7/i_2641
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[142] along load instance corei_7/i_3774
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[141] along load instance corei_7/i_2649
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[141] along load instance corei_7/i_3787
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[140] along load instance corei_7/i_2658
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[140] along load instance corei_7/i_3795
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[139] along load instance corei_7/i_2666
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[139] along load instance corei_7/i_3803
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[138] along load instance corei_7/i_2674
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[138] along load instance corei_7/i_3811
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[137] along load instance corei_7/i_2678
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[137] along load instance corei_7/i_3819
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[136] along load instance corei_7/i_2686
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[136] along load instance corei_7/i_3827
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[135] along load instance corei_7/i_2698
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[135] along load instance corei_7/i_3830
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[134] along load instance corei_7/i_2577
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[134] along load instance corei_7/i_3838
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[133] along load instance corei_7/i_2585
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[133] along load instance corei_7/i_3846
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[132] along load instance corei_7/i_2594
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[132] along load instance corei_7/i_3859
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[131] along load instance corei_7/i_2602
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[131] along load instance corei_7/i_3862
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[130] along load instance corei_7/i_2610
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[130] along load instance corei_7/i_3873
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[129] along load instance corei_7/i_2617
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[129] along load instance corei_7/i_3878
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[128] along load instance corei_7/i_2625
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[128] along load instance corei_7/i_3891
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[127] along load instance corei_7/i_2634
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[127] along load instance corei_7/i_3899
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[126] along load instance corei_7/i_3907
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[126] along load instance corei_7/i_5662
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[70] along load instance corei_7/i_2913
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[70] along load instance corei_7/i_2914
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[70] along load instance corei_7/i_6006
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[70] along load instance corei_7/i_6007
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[69] along load instance corei_7/i_2918
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[69] along load instance corei_7/i_2923
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[69] along load instance corei_7/i_6013
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[69] along load instance corei_7/i_6015
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[68] along load instance corei_7/i_2929
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[68] along load instance corei_7/i_2930
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[68] along load instance corei_7/i_6018
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[68] along load instance corei_7/i_6021
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[67] along load instance corei_7/i_2934
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[67] along load instance corei_7/i_2937
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[67] along load instance corei_7/i_6026
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[67] along load instance corei_7/i_6030
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[66] along load instance corei_7/i_2945
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[66] along load instance corei_7/i_2946
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[66] along load instance corei_7/i_6037
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[66] along load instance corei_7/i_6039
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[65] along load instance corei_7/i_2950
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[65] along load instance corei_7/i_2953
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[65] along load instance corei_7/i_6045
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[65] along load instance corei_7/i_6047
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[64] along load instance corei_7/i_2958
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[64] along load instance corei_7/i_2961
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[64] along load instance corei_7/i_6050
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[64] along load instance corei_7/i_6053
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[63] along load instance corei_7/i_2966
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[63] along load instance corei_7/i_2969
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[63] along load instance corei_7/i_6062
RETIMING: forward move fails for register corei_7/core/core0/core/core1/core/inter2/core/core/dataOutShifted_0_delay_1_reg[63] along load instance corei_7/i_6063
-
[INFO ]
-
: binary adder cost = 12275
-
[INFO ]
-
: ternary adder cost = 15984
-
[INFO ]
-
: reg cost = 133473
-
[INFO ]
-
:
LUT: 82956
FF: 95531
DSP: 428
BRAM: 0
CARRY8: 5520
-
[INFO ]
-
:
fmax = 580.046403712297 MHz
-
1 m 41 s
passedshould synth for rvFftPre
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:44:21
[Progress] at 2705.460 : Elaborate components
[Progress] at 2705.506 : Checks and transforms
[Progress] at 2705.593 : Generate Verilog
[Warning] 9 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 2705.624
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog unamed.v
# read_verilog synthRvFftPre.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthRvFftPre -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthRvFftPre -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 29426
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5612.348 ; gain = 337.793 ; free physical = 34735 ; free virtual = 71300
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthRvFftPre' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:6]
INFO: [Synth 8-6157] synthesizing module 'unamed' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/unamed.v:6]
INFO: [Synth 8-6155] done synthesizing module 'unamed' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/unamed.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthRvFftPre' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:6]
WARNING: [Synth 8-6014] Unused sequential element part0_0_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:4551]
WARNING: [Synth 8-6014] Unused sequential element part0_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:4552]
WARNING: [Synth 8-6014] Unused sequential element part0_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:4553]
WARNING: [Synth 8-6014] Unused sequential element part0_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:4554]
WARNING: [Synth 8-6014] Unused sequential element part0_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:4555]
WARNING: [Synth 8-6014] Unused sequential element part0_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:4556]
WARNING: [Synth 8-6014] Unused sequential element part0_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:4557]
WARNING: [Synth 8-6014] Unused sequential element part0_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:4558]
WARNING: [Synth 8-3848] Net p2s_validIn in module/entity synthRvFftPre does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre.v:337]
WARNING: [Synth 8-7129] Port validIn in module unamed is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module synthRvFftPre is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 5698.285 ; gain = 423.730 ; free physical = 35811 ; free virtual = 72377
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5716.098 ; gain = 441.543 ; free physical = 35810 ; free virtual = 72376
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5716.098 ; gain = 441.543 ; free physical = 35810 ; free virtual = 72376
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.08 . Memory (MB): peak = 5716.098 ; gain = 0.000 ; free physical = 35793 ; free virtual = 72359
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 5895.691 ; gain = 0.000 ; free physical = 35651 ; free virtual = 72217
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.1 . Memory (MB): peak = 5895.691 ; gain = 0.000 ; free physical = 35648 ; free virtual = 72214
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 5895.691 ; gain = 621.137 ; free physical = 35792 ; free virtual = 72358
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 5895.691 ; gain = 621.137 ; free physical = 35792 ; free virtual = 72358
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:14 ; elapsed = 00:00:14 . Memory (MB): peak = 5895.691 ; gain = 621.137 ; free physical = 35792 ; free virtual = 72358
---------------------------------------------------------------------------------
INFO: [Synth 8-6904] The RAM "unamed:/_zz_14_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/_zz_12_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 5895.691 ; gain = 621.137 ; free physical = 35784 ; free virtual = 72351
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 3 Bit Adders := 1
2 Input 2 Bit Adders := 2
2 Input 1 Bit Adders := 1
+---Registers :
2304 Bit Registers := 2
18 Bit Registers := 636
1 Bit Registers := 9
+---RAMs :
9K Bit (4 X 2304 bit) RAMs := 2
+---Muxes :
2 Input 36 Bit Muxes := 64
4 Input 18 Bit Muxes := 128
2 Input 3 Bit Muxes := 1
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
INFO: [Synth 8-6904] The RAM "p2s/_zz_14_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "p2s/_zz_12_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
WARNING: [Synth 8-7129] Port validIn in module unamed is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module synthRvFftPre is either unconnected or has no load
INFO: [Synth 8-6904] The RAM "p2s/_zz_14_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "p2s/_zz_12_reg" of size (depth=4 x width=2304) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:23 ; elapsed = 00:00:23 . Memory (MB): peak = 5895.691 ; gain = 621.137 ; free physical = 35247 ; free virtual = 71826
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Preliminary Mapping Report (see note below)
+------------+------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+------------+-----------+----------------------+-----------------+
|p2s | _zz_14_reg | Implied | 4 x 2304 | RAM32M16 x 165 |
|p2s | _zz_12_reg | Implied | 4 x 2304 | RAM32M16 x 165 |
+------------+------------+-----------+----------------------+-----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:30 ; elapsed = 00:00:31 . Memory (MB): peak = 6091.988 ; gain = 817.434 ; free physical = 33275 ; free virtual = 69854
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 6228.145 ; gain = 953.590 ; free physical = 33146 ; free virtual = 69725
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+------------+------------+-----------+----------------------+-----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+------------+------------+-----------+----------------------+-----------------+
|p2s | _zz_14_reg | Implied | 4 x 2304 | RAM32M16 x 165 |
|p2s | _zz_12_reg | Implied | 4 x 2304 | RAM32M16 x 165 |
+------------+------------+-----------+----------------------+-----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `synthRvFftPre`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftPre' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:41 ; elapsed = 00:00:43 . Memory (MB): peak = 6254.637 ; gain = 980.082 ; free physical = 33151 ; free virtual = 69730
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 6254.637 ; gain = 980.082 ; free physical = 33155 ; free virtual = 69734
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 6254.637 ; gain = 980.082 ; free physical = 33155 ; free virtual = 69734
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 6254.637 ; gain = 980.082 ; free physical = 33163 ; free virtual = 69742
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 6254.637 ; gain = 980.082 ; free physical = 33163 ; free virtual = 69742
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 6254.637 ; gain = 980.082 ; free physical = 33165 ; free virtual = 69744
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:00:48 . Memory (MB): peak = 6254.637 ; gain = 980.082 ; free physical = 33165 ; free virtual = 69744
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+--------------+---------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+--------------+---------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|synthRvFftPre | paddedDelayed_0_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_1_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_2_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_3_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_4_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_5_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_6_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_7_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_8_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_9_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_10_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_11_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_12_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_13_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_14_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_15_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_16_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_17_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_18_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_19_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_20_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_21_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_22_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_23_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_24_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_25_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_26_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_27_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_28_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_29_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_30_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_31_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_32_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_33_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_34_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_35_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_36_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_37_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_38_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_39_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_40_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_41_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_42_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_43_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_44_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_45_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_46_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_47_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_48_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_49_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_50_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_51_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_52_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_53_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_54_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_55_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_56_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_57_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_58_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_59_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_60_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_61_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_62_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_63_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_64_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_65_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_66_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_67_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_68_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_69_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_70_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_71_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_72_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_73_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_74_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_75_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_76_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_77_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_78_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_79_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_80_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_81_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_82_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_83_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_84_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_85_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_86_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_87_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_88_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_89_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_90_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_91_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_92_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_93_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_94_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_95_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_96_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_97_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_98_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_99_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_100_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_101_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_102_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_103_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_104_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_105_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_106_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_107_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_108_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_109_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_110_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_111_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_112_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_113_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_114_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_115_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_116_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_117_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_118_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_119_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_120_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_121_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_122_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_123_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_124_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_125_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_126_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPre | paddedDelayed_127_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
+--------------+---------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |LUT1 | 1|
|2 |LUT2 | 21|
|3 |LUT3 | 2342|
|4 |LUT4 | 18|
|5 |LUT5 | 72|
|6 |LUT6 | 2232|
|7 |RAM32M16 | 330|
|8 |SRL16E | 2304|
|9 |FDCE | 84|
|10 |FDRE | 9145|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 6254.637 ; gain = 980.082 ; free physical = 33165 ; free virtual = 69744
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 3 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 6254.637 ; gain = 800.488 ; free physical = 33193 ; free virtual = 69772
Synthesis Optimization Complete : Time (s): cpu = 00:00:47 ; elapsed = 00:00:48 . Memory (MB): peak = 6254.645 ; gain = 980.082 ; free physical = 33193 ; free virtual = 69772
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.14 . Memory (MB): peak = 6266.605 ; gain = 0.000 ; free physical = 33283 ; free virtual = 69862
INFO: [Netlist 29-17] Analyzing 330 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 6348.152 ; gain = 0.000 ; free physical = 33187 ; free virtual = 69766
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 330 instances were transformed.
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 330 instances
Synth Design complete, checksum: 4fc45895
INFO: [Common 17-83] Releasing license: Synthesis
27 Infos, 14 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:04 ; elapsed = 00:01:02 . Memory (MB): peak = 6348.152 ; gain = 1180.355 ; free physical = 33428 ; free virtual = 70007
# write_checkpoint -force synthRvFftPre_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPre/synthRvFftPre_after_synth.dcp' has been generated.
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:45:34 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthRvFftPre
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| CLB LUTs* | 8478 | 0 | 0 | 1182240 | 0.72 |
| LUT as Logic | 3534 | 0 | 0 | 1182240 | 0.30 |
| LUT as Memory | 4944 | 0 | 0 | 591840 | 0.84 |
| LUT as Distributed RAM | 2640 | 0 | | | |
| LUT as Shift Register | 2304 | 0 | | | |
| CLB Registers | 9229 | 0 | 0 | 2364480 | 0.39 |
| Register as Flip Flop | 9229 | 0 | 0 | 2364480 | 0.39 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 147780 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 591120 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+----------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 84 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 9145 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 9145 | Register |
| RAMD32 | 4620 | CLB |
| LUT3 | 2342 | CLB |
| SRL16E | 2304 | CLB |
| LUT6 | 2232 | CLB |
| RAMS32 | 660 | CLB |
| FDCE | 84 | Register |
| LUT5 | 72 | CLB |
| LUT2 | 21 | CLB |
| LUT4 | 18 | CLB |
| LUT1 | 1 | CLB |
+----------+------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:45:57 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthRvFftPre
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (MET) : 0.377ns (required time - arrival time)
Source: p2s/_zz_4_reg[2]/C
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: p2s/_zz_12_reg_0_3_0_13/RAMA/WE
(rising edge-triggered cell RAMD32 clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 0.630ns (logic 0.115ns (18.254%) route 0.515ns (81.746%))
Logic Levels: 1 (LUT1=1)
Clock Path Skew: -0.028ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.000ns = ( 1.250 - 1.250 )
Source Clock Delay (SCD): 0.028ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=16812, unset) 0.028 0.028 p2s/clk
FDCE r p2s/_zz_4_reg[2]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_FDCE_C_Q) 0.077 0.105 f p2s/_zz_4_reg[2]/Q
net (fo=2, unplaced) 0.149 0.254 p2s/_zz_4[2]
LUT1 (Prop_LUT1_I0_O) 0.038 0.292 r p2s/_zz_14_reg_0_3_0_13_i_1/O
net (fo=5280, unplaced) 0.366 0.658 p2s/_zz_12_reg_0_3_0_13/WE
RAMD32 r p2s/_zz_12_reg_0_3_0_13/RAMA/WE
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=16812, unset) 0.000 1.250 p2s/_zz_12_reg_0_3_0_13/WCLK
RAMD32 r p2s/_zz_12_reg_0_3_0_13/RAMA/CLK
clock pessimism 0.000 1.250
clock uncertainty -0.035 1.215
RAMD32 (Setup_RAMD32_CLK_WE)
-0.180 1.035 p2s/_zz_12_reg_0_3_0_13/RAMA
-------------------------------------------------------------------
required time 1.035
arrival time -0.658
-------------------------------------------------------------------
slack 0.377
report_timing: Time (s): cpu = 00:00:24 ; elapsed = 00:00:23 . Memory (MB): peak = 7149.516 ; gain = 638.449 ; free physical = 30696 ; free virtual = 67275
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:45:58 2022...
-
[INFO ]
-
: binary adder cost = 8
-
[INFO ]
-
: ternary adder cost = 0
-
[INFO ]
-
: reg cost = 16065
-
[INFO ]
-
:
LUT: 8478
FF: 9229
DSP: 0
BRAM: 0
CARRY8: 0
-
[INFO ]
-
:
fmax = 1145.475372279496 MHz
-
2 m 41 s
passedshould synth for rvFftPost
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:46:02
[Progress] at 2806.465 : Elaborate components
[Progress] at 2806.536 : Checks and transforms
[Progress] at 2806.676 : Generate Verilog
[Done] at 2806.719
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog synthRvFftPost.v
read_verilog: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 5145.988 ; gain = 2.016 ; free physical = 32824 ; free virtual = 69389
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthRvFftPost -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthRvFftPost -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 30946
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5612.539 ; gain = 337.793 ; free physical = 32471 ; free virtual = 69036
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'synthRvFftPost' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPost/synthRvFftPost.v:6]
INFO: [Synth 8-6155] done synthesizing module 'synthRvFftPost' (0#1) [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPost/synthRvFftPost.v:6]
WARNING: [Synth 8-7129] Port validIn in module synthRvFftPost is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5733.477 ; gain = 458.730 ; free physical = 33547 ; free virtual = 70113
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5751.289 ; gain = 476.543 ; free physical = 33543 ; free virtual = 70110
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 5751.289 ; gain = 476.543 ; free physical = 33543 ; free virtual = 70110
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 5751.289 ; gain = 0.000 ; free physical = 33509 ; free virtual = 70076
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPost/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPost/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 5933.883 ; gain = 0.000 ; free physical = 33327 ; free virtual = 69894
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.26 . Memory (MB): peak = 5933.883 ; gain = 0.000 ; free physical = 33319 ; free virtual = 69886
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 5933.883 ; gain = 659.137 ; free physical = 33486 ; free virtual = 70053
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 5933.883 ; gain = 659.137 ; free physical = 33486 ; free virtual = 70053
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:17 . Memory (MB): peak = 5933.883 ; gain = 659.137 ; free physical = 33486 ; free virtual = 70053
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 5933.883 ; gain = 659.137 ; free physical = 33416 ; free virtual = 69984
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 18 Bit Adders := 128
3 Input 18 Bit Adders := 192
2 Input 3 Bit Adders := 1
+---Registers :
18 Bit Registers := 2176
1 Bit Registers := 8
+---Muxes :
2 Input 18 Bit Muxes := 128
5 Input 18 Bit Muxes := 128
2 Input 3 Bit Muxes := 1
5 Input 2 Bit Muxes := 128
2 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port validIn in module synthRvFftPost is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 5933.883 ; gain = 659.137 ; free physical = 35807 ; free virtual = 72401
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 6127.758 ; gain = 853.012 ; free physical = 35387 ; free virtual = 71981
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:14 ; elapsed = 00:01:16 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 35093 ; free virtual = 71688
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `synthRvFftPost__GB0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftPost__GB0' done
INFO: [Synth 8-5816] Retiming module `synthRvFftPost_GT0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftPost_GT0' done
INFO: [Synth 8-5816] Retiming module `synthRvFftPost_GT0__1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftPost_GT0__1' done
INFO: [Synth 8-5816] Retiming module `synthRvFftPost_GT1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftPost_GT1' done
INFO: [Synth 8-5816] Retiming module `synthRvFftPost`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRvFftPost' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:30 ; elapsed = 00:01:33 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 34771 ; free virtual = 71365
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:35 ; elapsed = 00:01:38 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 34734 ; free virtual = 71328
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:36 ; elapsed = 00:01:38 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 34729 ; free virtual = 71323
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:38 ; elapsed = 00:01:40 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 34711 ; free virtual = 71305
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:38 ; elapsed = 00:01:40 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 34808 ; free virtual = 71402
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:38 ; elapsed = 00:01:41 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 34748 ; free virtual = 71342
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 34749 ; free virtual = 71343
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+---------------+--------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+---------------+--------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|synthRvFftPost | conjugated_63_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_63_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_63_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_63_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_0_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_0_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_0_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_0_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_1_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_1_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_1_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_1_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_37_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_37_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_37_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_37_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_27_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_27_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_27_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_27_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_60_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_60_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_60_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_60_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_3_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_3_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_3_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_3_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_4_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_4_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_4_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_4_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_58_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_58_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_58_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_58_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_33_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_33_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_33_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_33_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_6_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_6_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_6_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_6_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_31_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_31_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_31_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_31_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_61_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_61_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_61_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_61_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_52_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_52_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_52_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_52_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_10_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_10_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_10_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_10_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_54_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_54_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_54_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_54_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_12_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_12_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_12_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_12_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_29_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_51_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_51_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_51_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_51_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_13_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_13_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_13_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_13_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_41_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_41_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_41_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_41_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_42_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_42_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_42_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_42_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_5_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_5_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_5_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_5_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_22_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_22_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_22_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_22_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_23_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_23_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_23_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_23_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_59_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_59_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_59_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_59_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_56_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_24_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_18_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_18_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_18_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_18_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_62_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_62_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_62_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_62_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_2_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_2_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_2_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_2_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_16_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_16_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_16_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_16_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_46_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_46_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_46_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_46_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_48_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_48_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_48_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_48_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_40_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_40_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_40_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_40_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_39_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_39_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_39_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_39_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_38_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_38_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_38_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_38_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_49_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_49_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_49_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_49_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_36_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_36_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_36_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_36_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_32_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_32_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_32_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_32_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_28_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_28_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_28_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_28_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_26_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_26_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_26_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_26_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_56_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_56_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_56_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_25_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_25_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_25_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_25_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_24_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | conjugated_24_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_24_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_15_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_15_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_15_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_15_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_8_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_8_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_8_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_8_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_34_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_34_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_34_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_34_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_57_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_57_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_57_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_57_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_35_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_35_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_35_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_35_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_20_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_20_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_20_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_20_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_50_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_50_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_50_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_50_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_14_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_14_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_29_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | conjugated_29_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_29_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_30_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_30_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_30_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_30_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_44_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_44_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_44_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_44_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_7_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_7_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_7_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_7_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_53_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_53_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_53_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_53_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_55_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_55_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_55_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_55_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_21_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_21_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_21_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_21_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_19_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_19_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_19_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_19_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_17_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_17_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_17_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_17_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_47_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_47_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_47_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_47_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_14_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_14_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_11_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_11_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_11_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_11_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_9_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_9_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_9_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_9_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_43_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_43_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_43_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_43_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_45_delay_4_imag_reg[17] | 4 | 18 | NO | YES | YES | 18 | 0 |
|synthRvFftPost | delayedInput_45_delay_4_imag_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | conjugated_45_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | delayedInput_45_delay_4_real_reg[17] | 4 | 18 | NO | NO | YES | 18 | 0 |
|synthRvFftPost | lastIn_delay_4_reg | 4 | 1 | YES | NO | YES | 1 | 0 |
|synthRvFftPost | lastIn_delay_8_reg | 4 | 1 | YES | NO | YES | 1 | 0 |
+---------------+--------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |CARRY8 | 1344|
|2 |LUT1 | 1152|
|3 |LUT2 | 4619|
|4 |LUT3 | 2333|
|5 |LUT4 | 1|
|6 |LUT6 | 3538|
|7 |SRL16E | 4610|
|8 |FDCE | 36|
|9 |FDRE | 26498|
+------+-------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 6312.648 ; gain = 1037.902 ; free physical = 34749 ; free virtual = 71343
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:31 ; elapsed = 00:01:34 . Memory (MB): peak = 6312.648 ; gain = 855.309 ; free physical = 34783 ; free virtual = 71377
Synthesis Optimization Complete : Time (s): cpu = 00:01:39 ; elapsed = 00:01:41 . Memory (MB): peak = 6312.656 ; gain = 1037.902 ; free physical = 34783 ; free virtual = 71377
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.52 . Memory (MB): peak = 6312.656 ; gain = 0.000 ; free physical = 34543 ; free virtual = 71137
INFO: [Netlist 29-17] Analyzing 1344 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
WARNING: [Netlist 29-101] Netlist 'synthRvFftPost' is not ideal for floorplanning, since the cellview 'synthRvFftPost' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPost/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPost/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 6349.305 ; gain = 0.000 ; free physical = 34381 ; free virtual = 70975
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete, checksum: ff8d8e66
INFO: [Common 17-83] Releasing license: Synthesis
27 Infos, 4 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:02:00 ; elapsed = 00:02:00 . Memory (MB): peak = 6349.305 ; gain = 1203.316 ; free physical = 34624 ; free virtual = 71219
# write_checkpoint -force synthRvFftPost_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRvFftPost/synthRvFftPost_after_synth.dcp' has been generated.
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:48:17 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthRvFftPost
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+----------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+-------+-------+------------+-----------+-------+
| CLB LUTs* | 16253 | 0 | 0 | 1182240 | 1.37 |
| LUT as Logic | 11643 | 0 | 0 | 1182240 | 0.98 |
| LUT as Memory | 4610 | 0 | 0 | 591840 | 0.78 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 4610 | 0 | | | |
| CLB Registers | 26534 | 0 | 0 | 2364480 | 1.12 |
| Register as Flip Flop | 26534 | 0 | 0 | 2364480 | 1.12 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 1344 | 0 | 0 | 147780 | 0.91 |
| F7 Muxes | 0 | 0 | 0 | 591120 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+----------------------------+-------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 36 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 26498 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+----------+-------+---------------------+
| FDRE | 26498 | Register |
| LUT2 | 4619 | CLB |
| SRL16E | 4610 | CLB |
| LUT6 | 3538 | CLB |
| LUT3 | 2333 | CLB |
| CARRY8 | 1344 | CLB |
| LUT1 | 1152 | CLB |
| FDCE | 36 | Register |
| LUT4 | 1 | CLB |
+----------+-------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:48:38 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthRvFftPost
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -0.307ns (required time - arrival time)
Source: localCounter_value_reg[0]_rep__1/C
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: sum_0_imag_reg[17]/D
(rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 1.539ns (logic 0.714ns (46.394%) route 0.825ns (53.606%))
Logic Levels: 7 (CARRY8=4 LUT2=1 LUT3=1 LUT6=1)
Clock Path Skew: -0.008ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.028ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=31143, unset) 0.028 0.028 clk
FDCE r localCounter_value_reg[0]_rep__1/C
------------------------------------------------------------------- -------------------
FDCE (Prop_FDCE_C_Q) 0.077 0.105 r localCounter_value_reg[0]_rep__1/Q
net (fo=142, unplaced) 0.243 0.348 localCounter_value_reg[0]_rep__1_n_0
LUT3 (Prop_LUT3_I2_O) 0.038 0.386 r conjugated_63_delay_3_real_reg[17]_srl3_i_2/O
net (fo=145, unplaced) 0.291 0.677 conjugated_63_delay_3_real_reg[17]_srl3_i_2_n_0
LUT6 (Prop_LUT6_I1_O) 0.037 0.714 r sum_0_imag[15]_i_18/O
net (fo=1, unplaced) 0.023 0.737 sum_0_imag[15]_i_18_n_0
CARRY8 (Prop_CARRY8_S[1]_CO[7])
0.197 0.934 r sum_0_imag_reg[15]_i_10/CO[7]
net (fo=1, unplaced) 0.005 0.939 sum_0_imag_reg[15]_i_10_n_0
CARRY8 (Prop_CARRY8_CI_O[4])
0.086 1.025 r sum_0_imag_reg[17]_i_5/O[4]
net (fo=1, unplaced) 0.204 1.229 sum_0_imag_reg[17]_i_5_n_11
LUT2 (Prop_LUT2_I1_O) 0.037 1.266 r sum_0_imag[15]_i_4/O
net (fo=1, unplaced) 0.029 1.295 sum_0_imag[15]_i_4_n_0
CARRY8 (Prop_CARRY8_S[5]_CO[7])
0.166 1.461 r sum_0_imag_reg[15]_i_1/CO[7]
net (fo=1, unplaced) 0.005 1.466 sum_0_imag_reg[15]_i_1_n_0
CARRY8 (Prop_CARRY8_CI_O[1])
0.076 1.542 r sum_0_imag_reg[17]_i_1/O[1]
net (fo=1, unplaced) 0.025 1.567 sum_0_imag_reg[17]_i_1_n_14
FDRE r sum_0_imag_reg[17]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=31143, unset) 0.020 1.270 clk
FDRE r sum_0_imag_reg[17]/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDRE (Setup_FDRE_C_D) 0.025 1.260 sum_0_imag_reg[17]
-------------------------------------------------------------------
required time 1.260
arrival time -1.567
-------------------------------------------------------------------
slack -0.307
report_timing: Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 7184.637 ; gain = 677.457 ; free physical = 33991 ; free virtual = 70585
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:48:39 2022...
-
[INFO ]
-
: binary adder cost = 2307
-
[INFO ]
-
: ternary adder cost = 3456
-
[INFO ]
-
: reg cost = 39176
-
[INFO ]
-
:
LUT: 16253
FF: 26534
DSP: 0
BRAM: 0
CARRY8: 1344
-
[INFO ]
-
:
fmax = 642.2607578676943 MHz
-
8 m 55 s
passedshould synth for tx
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:48:42
[Progress] at 2967.317 : Elaborate components
-
[INFO ]
-
:
----qammod with bit & power alloc----
bitAlloc for adaptive qammod: 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
powAlloc for adaptive qammod: 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
[Progress] at 2967.652 : Checks and transforms
[Progress] at 2969.984 : Generate Verilog
[Warning] 311 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 2971.072
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog ComplexMult.v
# read_verilog unamed.v
# read_verilog unamed_3.v
# read_verilog unamed_11.v
# read_verilog unamed_20.v
# read_verilog unamed_21.v
# read_verilog unamed_22.v
# read_verilog unamed_23.v
# read_verilog unamed_24.v
# read_verilog unamed_25.v
# read_verilog unamed_26.v
# read_verilog unamed_31.v
# read_verilog unamed_32.v
# read_verilog unamed_33.v
# read_verilog unamed_34.v
# read_verilog unamed_38.v
# read_verilog unamed_40.v
# read_verilog unamed_41.v
# read_verilog unamed_42.v
# read_verilog unamed_47.v
# read_verilog unamed_48.v
# read_verilog unamed_49.v
# read_verilog unamed_50.v
# read_verilog unamed_56.v
# read_verilog unamed_57.v
# read_verilog unamed_58.v
# read_verilog unamed_65.v
# read_verilog unamed_66.v
# read_verilog unamed_74.v
# read_verilog anon.v
# read_verilog unamed_91.v
# read_verilog unamed_92.v
# read_verilog unamed_93.v
# read_verilog unamed_95.v
# read_verilog unamed_96.v
# read_verilog convFtn_dut.v
# read_verilog intrlvFtn_dut.v
# read_verilog unamed_104.v
# read_verilog unamed_105.v
# read_verilog unamed_106.v
# read_verilog matintrlv_r64_c8_w36_sw64_dut.v
# read_verilog matintrlv_r8_c64_w36_sw64_dut.v
# read_verilog ifft_n64_factors_8_8_scales_2_2_dut.v
# read_verilog ifft_n8_factors_8_scales_1_dut.v
# read_verilog unamed_107.v
# read_verilog anon_1.v
# read_verilog anon_2.v
# read_verilog unamed_108.v
# read_verilog unamed_109.v
# read_verilog anon_3.v
# read_verilog unamed_110.v
# read_verilog convFtn_intrlvFtn_dut.v
# read_verilog QammodFtn_dut.v
# read_verilog hsIfftPre_dut.v
# read_verilog ifft_n512_sw64_factors_8_8_8_dut.v
# read_verilog S2P_s64_p512_dut.v
# read_verilog hsIfftPost_dut.v
# read_verilog P2S_s132_p528_bl1_bw18_dut.v
# read_verilog unamed_111.v
# read_verilog anon_4.v
# read_verilog convFtn_intrlvFtn_QammodFtn_dut.v
# read_verilog ifftFtn_dut.v
# read_verilog implTx.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top implTx -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top implTx -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 3221
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 5627.359 ; gain = 351.793 ; free physical = 33610 ; free virtual = 70180
---------------------------------------------------------------------------------
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1401]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1402]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1403]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1404]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1405]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1406]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1407]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1408]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1412]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1413]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1414]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1415]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1416]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1417]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1418]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1419]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1423]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1424]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1425]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1426]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1427]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1428]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1429]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1430]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1434]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1435]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1436]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1437]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1438]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1439]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1440]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1441]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1445]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1446]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1447]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1448]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1449]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1450]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1451]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1452]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1456]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1457]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1458]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1459]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1460]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1461]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1462]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1463]
WARNING: [Synth 8-6014] Unused sequential element dataIn_7_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1467]
WARNING: [Synth 8-6014] Unused sequential element dataIn_0_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1468]
WARNING: [Synth 8-6014] Unused sequential element dataIn_1_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1469]
WARNING: [Synth 8-6014] Unused sequential element dataIn_2_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1470]
WARNING: [Synth 8-6014] Unused sequential element dataIn_3_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1471]
WARNING: [Synth 8-6014] Unused sequential element dataIn_4_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1472]
WARNING: [Synth 8-6014] Unused sequential element dataIn_5_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1473]
WARNING: [Synth 8-6014] Unused sequential element dataIn_6_delay_1_7_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1474]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1489]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1490]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1491]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1492]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1493]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1494]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1495]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_1_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1496]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1500]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1501]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1502]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1503]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1504]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1505]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1506]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_2_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1507]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1511]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1512]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1513]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1514]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1515]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1516]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1517]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_3_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1518]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1522]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1523]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1524]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1525]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1526]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1527]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1528]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_4_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1529]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1533]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1534]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1535]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_2_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1536]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_1_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1537]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_0_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1538]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_7_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1539]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_5_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1540]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_6_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1544]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_5_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1545]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_4_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1546]
WARNING: [Synth 8-6014] Unused sequential element dataOutShifted_3_delay_1_6_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed.v:1547]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-4471] merging register 'merged_256_imag_reg[17:0]' into 'merged_256_real_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/anon_2.v:8446]
WARNING: [Synth 8-7129] Port validIn in module unamed_110 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module anon_3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_109 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module ComplexMult is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_11 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_49 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_47 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_31 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_106 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module anon_2 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_105 is either unconnected or has no load
WARNING: [Synth 8-7129] Port reset in module unamed_104 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_91 is either unconnected or has no load
WARNING: [Synth 8-7129] Port lastIn in module anon is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:36 . Memory (MB): peak = 6077.176 ; gain = 801.609 ; free physical = 25968 ; free virtual = 62549
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:37 . Memory (MB): peak = 6092.020 ; gain = 816.453 ; free physical = 25968 ; free virtual = 62549
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:37 . Memory (MB): peak = 6092.020 ; gain = 816.453 ; free physical = 25968 ; free virtual = 62549
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 6174.754 ; gain = 0.000 ; free physical = 25621 ; free virtual = 62199
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 6699.645 ; gain = 0.000 ; free physical = 25221 ; free virtual = 61800
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 6794.645 ; gain = 95.000 ; free physical = 25395 ; free virtual = 61973
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Finished Constraint Validation : Time (s): cpu = 00:00:47 ; elapsed = 00:01:06 . Memory (MB): peak = 6794.645 ; gain = 1519.078 ; free physical = 26165 ; free virtual = 62744
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Start Loading Part and Timing Information
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Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:47 ; elapsed = 00:01:06 . Memory (MB): peak = 6794.645 ; gain = 1519.078 ; free physical = 26165 ; free virtual = 62744
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---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:47 ; elapsed = 00:01:06 . Memory (MB): peak = 6794.645 ; gain = 1519.078 ; free physical = 26165 ; free virtual = 62744
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INFO: [Synth 8-6904] The RAM "unamed:/rams_0_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_1_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_2_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_3_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_4_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_5_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_6_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed:/rams_7_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:58 ; elapsed = 00:01:18 . Memory (MB): peak = 6794.645 ; gain = 1519.078 ; free physical = 25860 ; free virtual = 62446
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
3 Input 18 Bit Adders := 1462
2 Input 18 Bit Adders := 808
2 Input 7 Bit Adders := 1
2 Input 3 Bit Adders := 12
2 Input 2 Bit Adders := 2
+---XORs :
3 Input 1 Bit XORs := 81
4 Input 1 Bit XORs := 100
2 Input 1 Bit XORs := 200
+---Registers :
288 Bit Registers := 72
36 Bit Registers := 1726
32 Bit Registers := 64
18 Bit Registers := 5567
16 Bit Registers := 648
7 Bit Registers := 1
3 Bit Registers := 36
2 Bit Registers := 1
1 Bit Registers := 3167
+---RAMs :
4K Bit (16 X 288 bit) RAMs := 24
+---Muxes :
8 Input 288 Bit Muxes := 24
2 Input 254 Bit Muxes := 7
17 Input 36 Bit Muxes := 254
9 Input 32 Bit Muxes := 64
2 Input 18 Bit Muxes := 512
4 Input 18 Bit Muxes := 132
2 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 1
2 Input 3 Bit Muxes := 35
2 Input 2 Bit Muxes := 2
2 Input 1 Bit Muxes := 4
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-6904] The RAM "implTx/rams_7_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "implTx/rams_0_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_7_imag_5_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed_3.v:179]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_7_real_15_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed_3.v:181]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_7_imag_10_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed_3.v:182]
WARNING: [Synth 8-3936] Found unconnected internal register '_zz_ret_7_real_10_reg' and it is trimmed from '33' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed_3.v:180]
DSP Report: Generating DSP _zz_ret_7_real_15_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_7_real_14_reg is absorbed into DSP _zz_ret_7_real_15_reg.
DSP Report: register _zz_ret_7_real_15_reg is absorbed into DSP _zz_ret_7_real_15_reg.
DSP Report: operator _zz_ret_7_real_150 is absorbed into DSP _zz_ret_7_real_15_reg.
DSP Report: Generating DSP _zz_ret_7_real_10_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_7_real_9_reg is absorbed into DSP _zz_ret_7_real_10_reg.
DSP Report: register _zz_ret_7_real_10_reg is absorbed into DSP _zz_ret_7_real_10_reg.
DSP Report: operator _zz_ret_7_real_100 is absorbed into DSP _zz_ret_7_real_10_reg.
DSP Report: Generating DSP _zz_ret_7_imag_10_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_7_imag_9_reg is absorbed into DSP _zz_ret_7_imag_10_reg.
DSP Report: register _zz_ret_7_imag_10_reg is absorbed into DSP _zz_ret_7_imag_10_reg.
DSP Report: operator _zz_ret_7_imag_100 is absorbed into DSP _zz_ret_7_imag_10_reg.
DSP Report: Generating DSP _zz_ret_7_imag_5_reg, operation Mode is: (A2*(B:0x2d41))'.
DSP Report: register _zz_ret_7_imag_4_reg is absorbed into DSP _zz_ret_7_imag_5_reg.
DSP Report: register _zz_ret_7_imag_5_reg is absorbed into DSP _zz_ret_7_imag_5_reg.
DSP Report: operator _zz_ret_7_imag_50 is absorbed into DSP _zz_ret_7_imag_5_reg.
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_129/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_130/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_131/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_131/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_131/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_131/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_131/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_131/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_131/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_132/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_133/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_134/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_135/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_137/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_138/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_139/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_139/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_139/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_139/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_139/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_139/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_139/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_140/_zz_ret_real_4_reg' and it is trimmed from '34' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed_31.v:43]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_140/_zz_ret_imag_1_reg' and it is trimmed from '34' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/unamed_31.v:44]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_141/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_141/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_141/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_141/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_141/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_141/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_141/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_142/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_142/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_142/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_142/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_142/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_142/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_142/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_143/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_143/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_143/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_143/complexMult_108/_zz_product_imag_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:86]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_143/complexMult_108/mid_delay_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_143/complexMult_108/mid_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:78]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_143/complexMult_108/_zz_mid_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:77]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_145/complexMult_108/_zz_product_real_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:63]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_145/complexMult_108/_zz_product_real_1_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:95]
WARNING: [Synth 8-3936] Found unconnected internal register 'unamed_145/complexMult_108/_zz_product_imag_2_reg' and it is trimmed from '35' to '32' bits. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:62]
INFO: [Common 17-14] Message 'Synth 8-3936' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
DSP Report: Generating DSP unamed_129/complexMult_108/mid_reg, operation Mode is: (((D:0x3fb1)'+(A:0x645)')*B'')'.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/arD1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/mid_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_129/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_129/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_129/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/aiD2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_129/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_129/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_129/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_149/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_149/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_129/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/arD1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/mid_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_130/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_130/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/aiD2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_130/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_130/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_130/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_130/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_131/complexMult_108/mid_reg, operation Mode is: (((D:0x3d3e)'+(A:0x1294)')*B'')'.
DSP Report: register unamed_131/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/arD1_reg is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/mid_reg is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_mid0 is absorbed into DSP unamed_131/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_131/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_131/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/aiD2_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_131/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_131/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_131/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_131/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/arD1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/mid_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid0 is absorbed into DSP unamed_132/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_132/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_132/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_132/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_132/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_132/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/mid_reg, operation Mode is: (((D:0x3871)'+(A:0x1e2b)')*B'')'.
DSP Report: register unamed_133/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/arD1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/mid_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_mid0 is absorbed into DSP unamed_133/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_133/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/aiD2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_133/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_133/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_133/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_133/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_133/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_134/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/arD1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/mid_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid0 is absorbed into DSP unamed_134/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_134/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/aiD2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_134/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_134/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_134/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_134/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_135/complexMult_108/mid_reg, operation Mode is: (((D:0x3179)'+(A:0x2899)')*B'')'.
DSP Report: register unamed_135/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/arD1_reg is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/mid_reg is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_mid0 is absorbed into DSP unamed_135/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_135/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_135/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/aiD2_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_135/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_135/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_135/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_135/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_135/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_135/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_135/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_135/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_135/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_135/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_137/complexMult_108/arD1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/mid_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_137/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_137/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_137/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/aiD2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_137/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_137/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_137/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_137/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_137/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_137/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_138/complexMult_108/arD1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/mid_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_138/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid0 is absorbed into DSP unamed_138/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_138/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/aiD2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_138/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_138/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_138/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_138/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_138/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_138/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_139/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_139/complexMult_108/arD1_reg is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: register unamed_139/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: register unamed_139/complexMult_108/mid_reg is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: register unamed_139/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: operator unamed_139/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid0 is absorbed into DSP unamed_139/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_139/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_139/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_139/complexMult_108/aiD2_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_139/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_139/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_139/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_139/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_139/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_139/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_139/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_139/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_139/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_139/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_139/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_139/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_139/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_139/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_139/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_139/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_139/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_139/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_139/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_139/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_139/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_140/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_140/_zz_ret_real_1_reg is absorbed into DSP unamed_140/_zz_ret_real_4_reg.
DSP Report: register unamed_140/_zz_ret_real_reg is absorbed into DSP unamed_140/_zz_ret_real_4_reg.
DSP Report: register unamed_140/_zz_ret_real_4_reg is absorbed into DSP unamed_140/_zz_ret_real_4_reg.
DSP Report: register unamed_140/_zz_ret_real_3_reg is absorbed into DSP unamed_140/_zz_ret_real_4_reg.
DSP Report: operator unamed_140/_zz_ret_real_40 is absorbed into DSP unamed_140/_zz_ret_real_4_reg.
DSP Report: operator unamed_140/_zz_ret_real_30 is absorbed into DSP unamed_140/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_140/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_140/_zz_ret_real_1_reg is absorbed into DSP unamed_140/_zz_ret_imag_1_reg.
DSP Report: register unamed_140/_zz_ret_real_reg is absorbed into DSP unamed_140/_zz_ret_imag_1_reg.
DSP Report: register unamed_140/_zz_ret_imag_1_reg is absorbed into DSP unamed_140/_zz_ret_imag_1_reg.
DSP Report: register unamed_140/_zz_ret_imag_reg is absorbed into DSP unamed_140/_zz_ret_imag_1_reg.
DSP Report: operator unamed_140/_zz_ret_imag_10 is absorbed into DSP unamed_140/_zz_ret_imag_1_reg.
DSP Report: operator unamed_140/_zz_ret_imag0 is absorbed into DSP unamed_140/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_141/complexMult_108/arD1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/mid_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_141/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid0 is absorbed into DSP unamed_141/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_141/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_141/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_141/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_141/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_141/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_141/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_142/complexMult_108/arD1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/mid_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_142/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid0 is absorbed into DSP unamed_142/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_142/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/aiD2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_142/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_142/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_142/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_142/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_142/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_143/complexMult_108/arD1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/mid_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_143/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_143/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_143/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_143/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_143/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_143/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_143/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_143/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_143/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/mid_reg, operation Mode is: (((D:0x3d3e)'+(A:0x1294)')*B'')'.
DSP Report: register unamed_145/complexMult_108/arD1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/mid_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_145/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: register unamed_131/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: operator unamed_131/complexMult_108/_zz_mid0 is absorbed into DSP unamed_145/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_145/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/aiD2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_131/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_145/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_145/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_145/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_131/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_145/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_145/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_145/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_146/complexMult_108/arD1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/mid_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_146/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid0 is absorbed into DSP unamed_146/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_146/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/aiD2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_146/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_146/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_146/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_146/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_146/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_146/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_147/complexMult_108/mid_reg, operation Mode is: (((D:0x3179)'+(A:0x2899)')*B'')'.
DSP Report: register unamed_147/complexMult_108/arD1_reg is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: register unamed_147/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: register unamed_147/complexMult_108/mid_reg is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: register unamed_147/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: operator unamed_147/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_mid0 is absorbed into DSP unamed_147/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_147/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_147/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_147/complexMult_108/aiD2_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_147/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_147/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_147/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_147/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_147/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_147/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_147/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_147/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_147/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_147/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_147/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_147/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_135/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_135/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_147/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_147/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_147/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_147/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_148/complexMult_108/arD1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/mid_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_148/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid0 is absorbed into DSP unamed_148/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_148/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/aiD2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_148/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_148/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_148/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_148/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_148/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_148/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_149/complexMult_108/mid_reg, operation Mode is: (((D:0x3fb1)'+(A:0x645)')*B'')'.
DSP Report: register unamed_149/complexMult_108/arD1_reg is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: register unamed_149/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: register unamed_149/complexMult_108/mid_reg is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: register unamed_149/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: operator unamed_149/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_149/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_149/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_149/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/aiD2_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_149/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_149/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_149/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_149/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_149/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_149/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_149/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_149/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_149/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_149/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_149/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_149/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_149/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_149/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_149/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_149/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/mid_reg, operation Mode is: (((D:0xf384)'+(A:0x3ec5)')*B'')'.
DSP Report: register unamed_150/complexMult_108/arD1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/mid_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_mid0 is absorbed into DSP unamed_150/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_150/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_150/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_150/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_150/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_150/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_151/complexMult_108/mid_reg, operation Mode is: (((D:0xe1d5)'+(A:0x3871)')*B'')'.
DSP Report: register unamed_151/complexMult_108/arD1_reg is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: register unamed_151/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: register unamed_151/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: register unamed_151/complexMult_108/mid_reg is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: register unamed_151/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: register unamed_151/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_mid0 is absorbed into DSP unamed_151/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_151/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_151/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_151/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_151/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_151/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_151/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_153/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_153/complexMult_108/arD1_reg is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: register unamed_153/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: register unamed_153/complexMult_108/mid_reg is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: register unamed_153/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: operator unamed_153/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid0 is absorbed into DSP unamed_153/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_153/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_153/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_153/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_153/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_153/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_153/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_153/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_153/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_153/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_153/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_153/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_153/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_153/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_153/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_153/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_153/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_153/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_153/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_153/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_153/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_153/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_153/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_153/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_153/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_154/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_154/_zz_ret_real_1_reg is absorbed into DSP unamed_154/_zz_ret_real_4_reg.
DSP Report: register unamed_154/_zz_ret_real_reg is absorbed into DSP unamed_154/_zz_ret_real_4_reg.
DSP Report: register unamed_154/_zz_ret_real_4_reg is absorbed into DSP unamed_154/_zz_ret_real_4_reg.
DSP Report: register unamed_154/_zz_ret_real_3_reg is absorbed into DSP unamed_154/_zz_ret_real_4_reg.
DSP Report: operator unamed_154/_zz_ret_real_40 is absorbed into DSP unamed_154/_zz_ret_real_4_reg.
DSP Report: operator unamed_154/_zz_ret_real_30 is absorbed into DSP unamed_154/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_154/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_154/_zz_ret_real_1_reg is absorbed into DSP unamed_154/_zz_ret_imag_1_reg.
DSP Report: register unamed_154/_zz_ret_real_reg is absorbed into DSP unamed_154/_zz_ret_imag_1_reg.
DSP Report: register unamed_154/_zz_ret_imag_1_reg is absorbed into DSP unamed_154/_zz_ret_imag_1_reg.
DSP Report: register unamed_154/_zz_ret_imag_reg is absorbed into DSP unamed_154/_zz_ret_imag_1_reg.
DSP Report: operator unamed_154/_zz_ret_imag_10 is absorbed into DSP unamed_154/_zz_ret_imag_1_reg.
DSP Report: operator unamed_154/_zz_ret_imag0 is absorbed into DSP unamed_154/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_155/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_155/complexMult_108/arD1_reg is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: register unamed_155/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: register unamed_155/complexMult_108/mid_reg is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: register unamed_155/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: operator unamed_155/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid0 is absorbed into DSP unamed_155/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_155/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_155/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_155/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_155/complexMult_108/aiD2_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_155/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_155/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_155/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_155/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_155/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_155/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_155/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_155/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_155/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_155/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_155/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_155/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_155/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_155/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_155/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_155/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_155/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_155/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_155/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_155/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/mid_reg, operation Mode is: (((D:0xe783)'+(A:0x3b20)')*B'')'.
DSP Report: register unamed_157/complexMult_108/arD1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/mid_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_mid0 is absorbed into DSP unamed_157/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_157/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_157/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_157/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_157/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_157/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_157/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_158/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_158/_zz_ret_real_1_reg is absorbed into DSP unamed_158/_zz_ret_real_4_reg.
DSP Report: register unamed_158/_zz_ret_real_reg is absorbed into DSP unamed_158/_zz_ret_real_4_reg.
DSP Report: register unamed_158/_zz_ret_real_4_reg is absorbed into DSP unamed_158/_zz_ret_real_4_reg.
DSP Report: register unamed_158/_zz_ret_real_3_reg is absorbed into DSP unamed_158/_zz_ret_real_4_reg.
DSP Report: operator unamed_158/_zz_ret_real_40 is absorbed into DSP unamed_158/_zz_ret_real_4_reg.
DSP Report: operator unamed_158/_zz_ret_real_30 is absorbed into DSP unamed_158/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_158/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_158/_zz_ret_real_1_reg is absorbed into DSP unamed_158/_zz_ret_imag_1_reg.
DSP Report: register unamed_158/_zz_ret_real_reg is absorbed into DSP unamed_158/_zz_ret_imag_1_reg.
DSP Report: register unamed_158/_zz_ret_imag_1_reg is absorbed into DSP unamed_158/_zz_ret_imag_1_reg.
DSP Report: register unamed_158/_zz_ret_imag_reg is absorbed into DSP unamed_158/_zz_ret_imag_1_reg.
DSP Report: operator unamed_158/_zz_ret_imag_10 is absorbed into DSP unamed_158/_zz_ret_imag_1_reg.
DSP Report: operator unamed_158/_zz_ret_imag0 is absorbed into DSP unamed_158/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/mid_reg, operation Mode is: (((D:0xc4e0)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_159/complexMult_108/arD1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/mid_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_mid0 is absorbed into DSP unamed_159/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_159/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_159/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_159/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_159/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_159/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/mid_reg, operation Mode is: (((D:0x3871)'+(A:0x1e2b)')*B'')'.
DSP Report: register unamed_161/complexMult_108/arD1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/mid_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_161/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: operator unamed_133/complexMult_108/_zz_mid0 is absorbed into DSP unamed_161/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_161/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/aiD2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_133/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_161/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_161/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_161/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_161/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_161/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_161/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_162/complexMult_108/arD1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/mid_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_162/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid0 is absorbed into DSP unamed_162/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_162/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_162/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_162/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_162/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_162/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_162/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_162/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_163/complexMult_108/mid_reg, operation Mode is: (((D:0x3fb1)'+(A:0x645)')*B'')'.
DSP Report: register unamed_163/complexMult_108/arD1_reg is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: register unamed_163/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: register unamed_163/complexMult_108/mid_reg is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: register unamed_163/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: operator unamed_163/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: operator unamed_129/complexMult_108/_zz_mid0 is absorbed into DSP unamed_163/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_163/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_163/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_163/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_163/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_163/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_149/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_163/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_163/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_163/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_163/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_163/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_163/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_163/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_163/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_163/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_163/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_163/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_163/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_163/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_163/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_163/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_163/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_163/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_163/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/mid_reg, operation Mode is: (((D:0xe783)'+(A:0x3b20)')*B'')'.
DSP Report: register unamed_164/complexMult_108/arD1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/mid_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_164/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: operator unamed_157/complexMult_108/_zz_mid0 is absorbed into DSP unamed_164/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_164/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/aiD2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_164/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_164/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_164/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_164/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_164/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_164/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/mid_reg, operation Mode is: (((D:0xce87)'+(A:0x2899)')*B'')'.
DSP Report: register unamed_165/complexMult_108/arD1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/mid_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: register unamed_165/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_mid0 is absorbed into DSP unamed_165/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_165/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_165/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_165/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register unamed_165/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_165/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_165/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_165/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/mid_reg, operation Mode is: (((D:0xc13b)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_166/complexMult_108/arD1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/mid_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_mid0 is absorbed into DSP unamed_166/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_166/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_166/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_166/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_166/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_166/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_167/complexMult_108/mid_reg, operation Mode is: (((D:0xc2c2)'+(A:0xed6c)')*B'')'.
DSP Report: register unamed_167/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/arD1_reg is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/mid_reg is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_mid0 is absorbed into DSP unamed_167/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_167/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_167/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/aiD2_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_167/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_167/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_167/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_167/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/mid_reg, operation Mode is: (((D:0x3536)'+(A:0x238e)')*B'')'.
DSP Report: register unamed_169/complexMult_108/arD1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/mid_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_169/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: register unamed_134/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: operator unamed_134/complexMult_108/_zz_mid0 is absorbed into DSP unamed_169/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_169/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/aiD2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_134/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_169/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_169/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_169/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_141/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_169/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_169/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_169/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/mid_reg, operation Mode is: (((D:0x3b20)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_170/complexMult_108/arD1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/mid_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_170/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: operator unamed_132/complexMult_108/_zz_mid0 is absorbed into DSP unamed_170/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_170/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/aiD2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_142/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_170/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_170/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_170/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_170/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_170/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_170/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_171/complexMult_108/mid_reg, operation Mode is: (((D:0xf384)'+(A:0x3ec5)')*B'')'.
DSP Report: register unamed_171/complexMult_108/arD1_reg is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: register unamed_171/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: register unamed_171/complexMult_108/mid_reg is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: register unamed_171/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: register unamed_150/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: operator unamed_171/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: operator unamed_150/complexMult_108/_zz_mid0 is absorbed into DSP unamed_171/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_171/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_171/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_171/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_171/complexMult_108/aiD2_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_171/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_171/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_171/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_171/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_171/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_171/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_171/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_171/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_171/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_171/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_171/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_171/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_171/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_150/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_171/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_171/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_171/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_171/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_171/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_171/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_171/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_172/_zz_ret_real_4_reg, operation Mode is: ((D'+A2)*(B:0x2d41))'.
DSP Report: register unamed_172/_zz_ret_real_1_reg is absorbed into DSP unamed_172/_zz_ret_real_4_reg.
DSP Report: register unamed_172/_zz_ret_real_reg is absorbed into DSP unamed_172/_zz_ret_real_4_reg.
DSP Report: register unamed_172/_zz_ret_real_4_reg is absorbed into DSP unamed_172/_zz_ret_real_4_reg.
DSP Report: register unamed_172/_zz_ret_real_3_reg is absorbed into DSP unamed_172/_zz_ret_real_4_reg.
DSP Report: operator unamed_172/_zz_ret_real_40 is absorbed into DSP unamed_172/_zz_ret_real_4_reg.
DSP Report: operator unamed_172/_zz_ret_real_30 is absorbed into DSP unamed_172/_zz_ret_real_4_reg.
DSP Report: Generating DSP unamed_172/_zz_ret_imag_1_reg, operation Mode is: ((D'-A2)*(B:0x2d41))'.
DSP Report: register unamed_172/_zz_ret_real_1_reg is absorbed into DSP unamed_172/_zz_ret_imag_1_reg.
DSP Report: register unamed_172/_zz_ret_real_reg is absorbed into DSP unamed_172/_zz_ret_imag_1_reg.
DSP Report: register unamed_172/_zz_ret_imag_1_reg is absorbed into DSP unamed_172/_zz_ret_imag_1_reg.
DSP Report: register unamed_172/_zz_ret_imag_reg is absorbed into DSP unamed_172/_zz_ret_imag_1_reg.
DSP Report: operator unamed_172/_zz_ret_imag_10 is absorbed into DSP unamed_172/_zz_ret_imag_1_reg.
DSP Report: operator unamed_172/_zz_ret_imag0 is absorbed into DSP unamed_172/_zz_ret_imag_1_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/mid_reg, operation Mode is: (((D:0xc13b)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_173/complexMult_108/arD1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/mid_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_173/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: register unamed_166/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: operator unamed_166/complexMult_108/_zz_mid0 is absorbed into DSP unamed_173/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_173/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/aiD2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_173/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_173/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_173/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_166/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_173/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_173/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_173/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/mid_reg, operation Mode is: (((D:0xc4e0)'+(A:0xe783)')*B'')'.
DSP Report: register unamed_174/complexMult_108/arD1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_157/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/mid_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: register unamed_174/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_mid0 is absorbed into DSP unamed_174/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_174/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/aiD2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_174/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_174/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_174/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_174/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_174/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_174/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/mid_reg, operation Mode is: (((D:0xdc72)'+(A:0xcaca)')*B'')'.
DSP Report: register unamed_175/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/arD1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/mid_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_mid0 is absorbed into DSP unamed_175/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_175/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/aiD2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_175/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_175/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_175/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_175/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/mid_reg, operation Mode is: (((D:0x3179)'+(A:0x2899)')*B'')'.
DSP Report: register unamed_177/complexMult_108/arD1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/mid_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_177/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: register unamed_135/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: operator unamed_135/complexMult_108/_zz_mid0 is absorbed into DSP unamed_177/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_177/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/aiD2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_135/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_177/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_177/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_177/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_147/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_177/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_177/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_177/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/mid_reg, operation Mode is: (((D:0x3ec5)'+(A:0xc7c)')*B'')'.
DSP Report: register unamed_178/complexMult_108/arD1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/mid_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_178/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: register unamed_130/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: operator unamed_130/complexMult_108/_zz_mid0 is absorbed into DSP unamed_178/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_178/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_143/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_178/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_178/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_178/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_130/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_178/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_178/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_178/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_179/complexMult_108/mid_reg, operation Mode is: (((D:0xe1d5)'+(A:0x3871)')*B'')'.
DSP Report: register unamed_179/complexMult_108/arD1_reg is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: register unamed_179/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: register unamed_133/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: register unamed_151/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: register unamed_179/complexMult_108/mid_reg is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: register unamed_179/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: register unamed_151/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: operator unamed_179/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: operator unamed_151/complexMult_108/_zz_mid0 is absorbed into DSP unamed_179/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_179/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_179/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_179/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_179/complexMult_108/aiD2_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_179/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_151/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_179/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_179/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_179/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_179/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_179/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_179/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_179/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_179/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_179/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_179/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_179/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_179/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_151/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_179/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_179/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_179/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_179/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_179/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_179/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_179/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_180/complexMult_108/mid_reg, operation Mode is: (((D:0xc4e0)'+(A:0x187d)')*B'')'.
DSP Report: register unamed_180/complexMult_108/arD1_reg is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: register unamed_180/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: register unamed_132/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: register unamed_180/complexMult_108/mid_reg is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: register unamed_180/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: register unamed_159/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: operator unamed_180/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: operator unamed_159/complexMult_108/_zz_mid0 is absorbed into DSP unamed_180/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_180/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_180/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_180/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_180/complexMult_108/aiD2_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_180/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_132/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_180/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_180/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_180/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_180/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_180/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_180/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_180/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_180/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_180/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_180/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_180/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_180/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/brD2_delay_1_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_159/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_180/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_180/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_180/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_180/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_180/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_180/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_180/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_181/complexMult_108/mid_reg, operation Mode is: (((D:0xc2c2)'+(A:0xed6c)')*B'')'.
DSP Report: register unamed_181/complexMult_108/arD1_reg is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: register unamed_181/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: register unamed_181/complexMult_108/mid_reg is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: register unamed_181/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: register unamed_167/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: operator unamed_181/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: operator unamed_167/complexMult_108/_zz_mid0 is absorbed into DSP unamed_181/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_181/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_181/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_181/complexMult_108/aiD2_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_181/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_181/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_167/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_181/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_181/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_181/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_181/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_181/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_181/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_181/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_181/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_181/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_181/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_181/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_181/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_167/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_181/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_181/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_181/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_181/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_181/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_181/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_181/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_182/complexMult_108/mid_reg, operation Mode is: (((D:0xdc72)'+(A:0xcaca)')*B'')'.
DSP Report: register unamed_182/complexMult_108/arD1_reg is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: register unamed_182/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/coeff_real_delay_1_reg is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: register unamed_182/complexMult_108/mid_reg is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: register unamed_182/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: register unamed_175/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: operator unamed_182/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: operator unamed_175/complexMult_108/_zz_mid0 is absorbed into DSP unamed_182/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_182/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*BCIN2)')'.
DSP Report: register unamed_182/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_182/complexMult_108/aiD2_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_182/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_182/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_175/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_182/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_182/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_182/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_182/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_182/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_182/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_182/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_182/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*BCIN2)')'.
DSP Report: register unamed_182/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_182/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_182/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_182/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_175/complexMult_108/brD2_delay_2_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_182/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_182/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_182/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_182/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_182/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_182/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_182/complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP unamed_183/complexMult_108/mid_reg, operation Mode is: (((D:0x645)'+(A:0xc04f)')*B'')'.
DSP Report: register unamed_183/complexMult_108/arD1_reg is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: register unamed_183/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: register unamed_183/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: register unamed_129/complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: register unamed_183/complexMult_108/mid_reg is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: register unamed_183/complexMult_108/_zz_mid_1_reg is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: register unamed_183/complexMult_108/_zz_mid_reg is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: operator unamed_183/complexMult_108/_zz_mid_10 is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: operator unamed_183/complexMult_108/_zz_mid0 is absorbed into DSP unamed_183/complexMult_108/mid_reg.
DSP Report: Generating DSP unamed_183/complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register unamed_183/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_183/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_183/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_183/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_183/complexMult_108/aiD2_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_183/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_183/complexMult_108/_zz_product_real_2_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_183/complexMult_108/_zz_product_real_1_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: register unamed_183/complexMult_108/_zz_product_real_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_183/complexMult_108/_zz_product_real_20 is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_183/complexMult_108/_zz_product_real_10 is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: operator unamed_183/complexMult_108/_zz_product_real0 is absorbed into DSP unamed_183/complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP unamed_183/complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-A'')*B'')')'.
DSP Report: register unamed_183/complexMult_108/aiD2_delay_1_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_183/complexMult_108/mid_delay_1_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_183/complexMult_108/data_real_delay_2_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_183/complexMult_108/arD1_delay_2_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_1_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_129/complexMult_108/biD2_delay_2_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_183/complexMult_108/_zz_product_imag_2_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_183/complexMult_108/_zz_product_imag_1_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: register unamed_183/complexMult_108/_zz_product_imag_reg is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_183/complexMult_108/_zz_product_imag_20 is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_183/complexMult_108/_zz_product_imag_10 is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator unamed_183/complexMult_108/_zz_product_imag0 is absorbed into DSP unamed_183/complexMult_108/_zz_product_imag_2_reg.
INFO: [Synth 8-6904] The RAM "implTx/rams_7_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "implTx/rams_0_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[2]' (FD) to '_zz_qamLuts_57_port0_reg[7]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[3]' (FD) to '_zz_qamLuts_57_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[4]' (FD) to '_zz_qamLuts_57_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[5]' (FD) to '_zz_qamLuts_57_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[6]' (FD) to '_zz_qamLuts_57_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[7]' (FD) to '_zz_qamLuts_57_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[8]' (FD) to '_zz_qamLuts_57_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[11]' (FD) to '_zz_qamLuts_57_port0_reg[12]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[12]' (FD) to '_zz_qamLuts_57_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[13]' (FD) to '_zz_qamLuts_57_port0_reg[14]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[14]' (FD) to '_zz_qamLuts_57_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[15]' (FD) to '_zz_qamLuts_57_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[16]' (FD) to '_zz_qamLuts_57_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[20]' (FD) to '_zz_qamLuts_57_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[21]' (FD) to '_zz_qamLuts_57_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[22]' (FD) to '_zz_qamLuts_57_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[23]' (FD) to '_zz_qamLuts_57_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[24]' (FD) to '_zz_qamLuts_57_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[25]' (FD) to '_zz_qamLuts_57_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[26]' (FD) to '_zz_qamLuts_57_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[29]' (FD) to '_zz_qamLuts_57_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[30]' (FD) to '_zz_qamLuts_57_port0_reg[31]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[31]' (FD) to '_zz_qamLuts_57_port0_reg[32]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[32]' (FD) to '_zz_qamLuts_57_port0_reg[33]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[33]' (FD) to '_zz_qamLuts_57_port0_reg[34]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_57_port0_reg[34]' (FD) to '_zz_qamLuts_57_port0_reg[35]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[2]' (FD) to '_zz_qamLuts_58_port0_reg[7]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[3]' (FD) to '_zz_qamLuts_58_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[4]' (FD) to '_zz_qamLuts_58_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[5]' (FD) to '_zz_qamLuts_58_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[6]' (FD) to '_zz_qamLuts_58_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[7]' (FD) to '_zz_qamLuts_58_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[8]' (FD) to '_zz_qamLuts_58_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[11]' (FD) to '_zz_qamLuts_58_port0_reg[12]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[12]' (FD) to '_zz_qamLuts_58_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[13]' (FD) to '_zz_qamLuts_58_port0_reg[14]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[14]' (FD) to '_zz_qamLuts_58_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[15]' (FD) to '_zz_qamLuts_58_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[16]' (FD) to '_zz_qamLuts_58_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[20]' (FD) to '_zz_qamLuts_58_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[21]' (FD) to '_zz_qamLuts_58_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[22]' (FD) to '_zz_qamLuts_58_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[23]' (FD) to '_zz_qamLuts_58_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[24]' (FD) to '_zz_qamLuts_58_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[25]' (FD) to '_zz_qamLuts_58_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[26]' (FD) to '_zz_qamLuts_58_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[29]' (FD) to '_zz_qamLuts_58_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[30]' (FD) to '_zz_qamLuts_58_port0_reg[31]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[31]' (FD) to '_zz_qamLuts_58_port0_reg[32]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[32]' (FD) to '_zz_qamLuts_58_port0_reg[33]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[33]' (FD) to '_zz_qamLuts_58_port0_reg[34]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_58_port0_reg[34]' (FD) to '_zz_qamLuts_58_port0_reg[35]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[2]' (FD) to '_zz_qamLuts_59_port0_reg[7]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[3]' (FD) to '_zz_qamLuts_59_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[4]' (FD) to '_zz_qamLuts_59_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[5]' (FD) to '_zz_qamLuts_59_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[6]' (FD) to '_zz_qamLuts_59_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[7]' (FD) to '_zz_qamLuts_59_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[8]' (FD) to '_zz_qamLuts_59_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[11]' (FD) to '_zz_qamLuts_59_port0_reg[12]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[12]' (FD) to '_zz_qamLuts_59_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[13]' (FD) to '_zz_qamLuts_59_port0_reg[14]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[14]' (FD) to '_zz_qamLuts_59_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[15]' (FD) to '_zz_qamLuts_59_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[16]' (FD) to '_zz_qamLuts_59_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[20]' (FD) to '_zz_qamLuts_59_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[21]' (FD) to '_zz_qamLuts_59_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[22]' (FD) to '_zz_qamLuts_59_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[23]' (FD) to '_zz_qamLuts_59_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[24]' (FD) to '_zz_qamLuts_59_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[25]' (FD) to '_zz_qamLuts_59_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[26]' (FD) to '_zz_qamLuts_59_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[29]' (FD) to '_zz_qamLuts_59_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[30]' (FD) to '_zz_qamLuts_59_port0_reg[31]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[31]' (FD) to '_zz_qamLuts_59_port0_reg[32]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[32]' (FD) to '_zz_qamLuts_59_port0_reg[33]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[33]' (FD) to '_zz_qamLuts_59_port0_reg[34]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_59_port0_reg[34]' (FD) to '_zz_qamLuts_59_port0_reg[35]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[2]' (FD) to '_zz_qamLuts_60_port0_reg[7]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[3]' (FD) to '_zz_qamLuts_60_port0_reg[5]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[4]' (FD) to '_zz_qamLuts_60_port0_reg[8]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[5]' (FD) to '_zz_qamLuts_60_port0_reg[6]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[6]' (FD) to '_zz_qamLuts_60_port0_reg[11]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[7]' (FD) to '_zz_qamLuts_60_port0_reg[9]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[8]' (FD) to '_zz_qamLuts_60_port0_reg[10]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[11]' (FD) to '_zz_qamLuts_60_port0_reg[12]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[12]' (FD) to '_zz_qamLuts_60_port0_reg[13]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[13]' (FD) to '_zz_qamLuts_60_port0_reg[14]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[14]' (FD) to '_zz_qamLuts_60_port0_reg[15]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[15]' (FD) to '_zz_qamLuts_60_port0_reg[16]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[16]' (FD) to '_zz_qamLuts_60_port0_reg[17]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[20]' (FD) to '_zz_qamLuts_60_port0_reg[25]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[21]' (FD) to '_zz_qamLuts_60_port0_reg[23]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[22]' (FD) to '_zz_qamLuts_60_port0_reg[26]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[23]' (FD) to '_zz_qamLuts_60_port0_reg[24]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[24]' (FD) to '_zz_qamLuts_60_port0_reg[29]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[25]' (FD) to '_zz_qamLuts_60_port0_reg[27]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[26]' (FD) to '_zz_qamLuts_60_port0_reg[28]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[29]' (FD) to '_zz_qamLuts_60_port0_reg[30]'
INFO: [Synth 8-3886] merging instance '_zz_qamLuts_60_port0_reg[30]' (FD) to '_zz_qamLuts_60_port0_reg[31]'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-7129] Port validIn in module unamed_106 is either unconnected or has no load
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_3_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_4_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_5_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_6_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_1_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_2_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_3_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_4_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_5_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_6_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_1_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "unamed__GBM0/rams_2_reg" of size (depth=16 x width=288) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-4471] merging register 'complexMult_108/coeff_imag_delay_1_reg[15:0]' into 'complexMult_108/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_109/coeff_imag_delay_1_reg[15:0]' into 'complexMult_109/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_110/coeff_imag_delay_1_reg[15:0]' into 'complexMult_110/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_111/coeff_imag_delay_1_reg[15:0]' into 'complexMult_111/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_112/coeff_imag_delay_1_reg[15:0]' into 'complexMult_112/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_113/coeff_imag_delay_1_reg[15:0]' into 'complexMult_113/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_114/coeff_imag_delay_1_reg[15:0]' into 'complexMult_114/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_115/coeff_imag_delay_1_reg[15:0]' into 'complexMult_115/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_116/coeff_imag_delay_1_reg[15:0]' into 'complexMult_116/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_117/coeff_imag_delay_1_reg[15:0]' into 'complexMult_117/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_118/coeff_imag_delay_1_reg[15:0]' into 'complexMult_118/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_119/coeff_imag_delay_1_reg[15:0]' into 'complexMult_119/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_120/coeff_imag_delay_1_reg[15:0]' into 'complexMult_120/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_121/coeff_imag_delay_1_reg[15:0]' into 'complexMult_121/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_122/coeff_imag_delay_1_reg[15:0]' into 'complexMult_122/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_123/coeff_imag_delay_1_reg[15:0]' into 'complexMult_123/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_124/coeff_imag_delay_1_reg[15:0]' into 'complexMult_124/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_125/coeff_imag_delay_1_reg[15:0]' into 'complexMult_125/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_126/coeff_imag_delay_1_reg[15:0]' into 'complexMult_126/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_127/coeff_imag_delay_1_reg[15:0]' into 'complexMult_127/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_128/coeff_imag_delay_1_reg[15:0]' into 'complexMult_128/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_129/coeff_imag_delay_1_reg[15:0]' into 'complexMult_129/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_130/coeff_imag_delay_1_reg[15:0]' into 'complexMult_130/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_131/coeff_imag_delay_1_reg[15:0]' into 'complexMult_131/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_132/coeff_imag_delay_1_reg[15:0]' into 'complexMult_132/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_133/coeff_imag_delay_1_reg[15:0]' into 'complexMult_133/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_134/coeff_imag_delay_1_reg[15:0]' into 'complexMult_134/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_135/coeff_imag_delay_1_reg[15:0]' into 'complexMult_135/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_136/coeff_imag_delay_1_reg[15:0]' into 'complexMult_136/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_137/coeff_imag_delay_1_reg[15:0]' into 'complexMult_137/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_138/coeff_imag_delay_1_reg[15:0]' into 'complexMult_138/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_139/coeff_imag_delay_1_reg[15:0]' into 'complexMult_139/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_140/coeff_imag_delay_1_reg[15:0]' into 'complexMult_140/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_141/coeff_imag_delay_1_reg[15:0]' into 'complexMult_141/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_142/coeff_imag_delay_1_reg[15:0]' into 'complexMult_142/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_143/coeff_imag_delay_1_reg[15:0]' into 'complexMult_143/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_144/coeff_imag_delay_1_reg[15:0]' into 'complexMult_144/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_145/coeff_imag_delay_1_reg[15:0]' into 'complexMult_145/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_146/coeff_imag_delay_1_reg[15:0]' into 'complexMult_146/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_147/coeff_imag_delay_1_reg[15:0]' into 'complexMult_147/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_148/coeff_imag_delay_1_reg[15:0]' into 'complexMult_148/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_149/coeff_imag_delay_1_reg[15:0]' into 'complexMult_149/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_150/coeff_imag_delay_1_reg[15:0]' into 'complexMult_150/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_151/coeff_imag_delay_1_reg[15:0]' into 'complexMult_151/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_152/coeff_imag_delay_1_reg[15:0]' into 'complexMult_152/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_153/coeff_imag_delay_1_reg[15:0]' into 'complexMult_153/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_154/coeff_imag_delay_1_reg[15:0]' into 'complexMult_154/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_155/coeff_imag_delay_1_reg[15:0]' into 'complexMult_155/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_156/coeff_imag_delay_1_reg[15:0]' into 'complexMult_156/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_157/coeff_imag_delay_1_reg[15:0]' into 'complexMult_157/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_158/coeff_imag_delay_1_reg[15:0]' into 'complexMult_158/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_159/coeff_imag_delay_1_reg[15:0]' into 'complexMult_159/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_160/coeff_imag_delay_1_reg[15:0]' into 'complexMult_160/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_161/coeff_imag_delay_1_reg[15:0]' into 'complexMult_161/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_162/coeff_imag_delay_1_reg[15:0]' into 'complexMult_162/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_163/coeff_imag_delay_1_reg[15:0]' into 'complexMult_163/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_164/coeff_imag_delay_1_reg[15:0]' into 'complexMult_164/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_165/coeff_imag_delay_1_reg[15:0]' into 'complexMult_165/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_166/coeff_imag_delay_1_reg[15:0]' into 'complexMult_166/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_167/coeff_imag_delay_1_reg[15:0]' into 'complexMult_167/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_168/coeff_imag_delay_1_reg[15:0]' into 'complexMult_168/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_169/coeff_imag_delay_1_reg[15:0]' into 'complexMult_169/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_170/coeff_imag_delay_1_reg[15:0]' into 'complexMult_170/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_171/coeff_imag_delay_1_reg[15:0]' into 'complexMult_171/coeff_imag_delay_1_reg[15:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:57]
INFO: [Synth 8-4471] merging register 'complexMult_108/arD1_reg[17:0]' into 'complexMult_108/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_108/mid_delay_1_reg[34:0]' into 'complexMult_108/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_109/arD1_reg[17:0]' into 'complexMult_109/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_109/mid_delay_1_reg[34:0]' into 'complexMult_109/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_110/arD1_reg[17:0]' into 'complexMult_110/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_110/mid_delay_1_reg[34:0]' into 'complexMult_110/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_111/arD1_reg[17:0]' into 'complexMult_111/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_111/mid_delay_1_reg[34:0]' into 'complexMult_111/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_112/arD1_reg[17:0]' into 'complexMult_112/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_112/mid_delay_1_reg[34:0]' into 'complexMult_112/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_113/arD1_reg[17:0]' into 'complexMult_113/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_113/mid_delay_1_reg[34:0]' into 'complexMult_113/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_114/arD1_reg[17:0]' into 'complexMult_114/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_114/mid_delay_1_reg[34:0]' into 'complexMult_114/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_115/arD1_reg[17:0]' into 'complexMult_115/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_115/mid_delay_1_reg[34:0]' into 'complexMult_115/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_116/arD1_reg[17:0]' into 'complexMult_116/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_116/mid_delay_1_reg[34:0]' into 'complexMult_116/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_117/arD1_reg[17:0]' into 'complexMult_117/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_117/mid_delay_1_reg[34:0]' into 'complexMult_117/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_118/arD1_reg[17:0]' into 'complexMult_118/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_118/mid_delay_1_reg[34:0]' into 'complexMult_118/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_119/arD1_reg[17:0]' into 'complexMult_119/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_119/mid_delay_1_reg[34:0]' into 'complexMult_119/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_120/arD1_reg[17:0]' into 'complexMult_120/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_120/mid_delay_1_reg[34:0]' into 'complexMult_120/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_121/arD1_reg[17:0]' into 'complexMult_121/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_121/mid_delay_1_reg[34:0]' into 'complexMult_121/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_122/arD1_reg[17:0]' into 'complexMult_122/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_122/mid_delay_1_reg[34:0]' into 'complexMult_122/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_123/arD1_reg[17:0]' into 'complexMult_123/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_123/mid_delay_1_reg[34:0]' into 'complexMult_123/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_124/arD1_reg[17:0]' into 'complexMult_124/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Synth 8-4471] merging register 'complexMult_124/mid_delay_1_reg[34:0]' into 'complexMult_124/mid_delay_1_reg[34:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:79]
INFO: [Synth 8-4471] merging register 'complexMult_125/arD1_reg[17:0]' into 'complexMult_125/arD1_reg[17:0]' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/ComplexMult.v:65]
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3936' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
DSP Report: Generating DSP complexMult_108/mid_reg, operation Mode is: ((D'+(A:0x4000)'')*B'')'.
DSP Report: register complexMult_108/coeff_imag_delay_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/arD1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/data_real_delay_2_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_0_port0_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/coeff_real_delay_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/mid_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/_zz_mid_1_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: register complexMult_108/_zz_mid_reg is absorbed into DSP complexMult_108/mid_reg.
DSP Report: operator complexMult_108/_zz_mid_10 is absorbed into DSP complexMult_108/mid_reg.
DSP Report: operator complexMult_108/_zz_mid0 is absorbed into DSP complexMult_108/mid_reg.
DSP Report: Generating DSP complexMult_108/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_108/biD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/biD2_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/data_real_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/arD1_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/mid_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/aiD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_2_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_1_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: register complexMult_108/_zz_product_real_reg is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real_20 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real_10 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: operator complexMult_108/_zz_product_real0 is absorbed into DSP complexMult_108/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_108/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_108/aiD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/mid_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/brD2_delay_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/brD2_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/arD1_delay_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_2_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_1_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: register complexMult_108/_zz_product_imag_reg is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag_20 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag_10 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: operator complexMult_108/_zz_product_imag0 is absorbed into DSP complexMult_108/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_109/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_109/coeff_imag_delay_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/arD1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/data_real_delay_2_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_1_port0_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/coeff_real_delay_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/mid_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/_zz_mid_1_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: register complexMult_109/_zz_mid_reg is absorbed into DSP complexMult_109/mid_reg.
DSP Report: operator complexMult_109/_zz_mid_10 is absorbed into DSP complexMult_109/mid_reg.
DSP Report: operator complexMult_109/_zz_mid0 is absorbed into DSP complexMult_109/mid_reg.
DSP Report: Generating DSP complexMult_109/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_109/biD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/biD2_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/data_real_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/arD1_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/mid_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/aiD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_2_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_1_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: register complexMult_109/_zz_product_real_reg is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real_20 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real_10 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: operator complexMult_109/_zz_product_real0 is absorbed into DSP complexMult_109/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_109/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_109/aiD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/mid_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/brD2_delay_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/brD2_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/arD1_delay_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_2_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_1_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: register complexMult_109/_zz_product_imag_reg is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag_20 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag_10 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: operator complexMult_109/_zz_product_imag0 is absorbed into DSP complexMult_109/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_110/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_110/coeff_imag_delay_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/arD1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/data_real_delay_2_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_2_port0_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/coeff_real_delay_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/mid_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/_zz_mid_1_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: register complexMult_110/_zz_mid_reg is absorbed into DSP complexMult_110/mid_reg.
DSP Report: operator complexMult_110/_zz_mid_10 is absorbed into DSP complexMult_110/mid_reg.
DSP Report: operator complexMult_110/_zz_mid0 is absorbed into DSP complexMult_110/mid_reg.
DSP Report: Generating DSP complexMult_110/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_110/biD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/biD2_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/data_real_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/arD1_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/mid_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/aiD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_2_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_1_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: register complexMult_110/_zz_product_real_reg is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real_20 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real_10 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: operator complexMult_110/_zz_product_real0 is absorbed into DSP complexMult_110/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_110/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_110/aiD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/mid_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/brD2_delay_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/brD2_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/arD1_delay_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_2_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_1_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: register complexMult_110/_zz_product_imag_reg is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag_20 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag_10 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: operator complexMult_110/_zz_product_imag0 is absorbed into DSP complexMult_110/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_111/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_111/coeff_imag_delay_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/arD1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/data_real_delay_2_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_3_port0_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/coeff_real_delay_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/mid_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/_zz_mid_1_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: register complexMult_111/_zz_mid_reg is absorbed into DSP complexMult_111/mid_reg.
DSP Report: operator complexMult_111/_zz_mid_10 is absorbed into DSP complexMult_111/mid_reg.
DSP Report: operator complexMult_111/_zz_mid0 is absorbed into DSP complexMult_111/mid_reg.
DSP Report: Generating DSP complexMult_111/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_111/biD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/biD2_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/data_real_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/arD1_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/mid_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/aiD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_2_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_1_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: register complexMult_111/_zz_product_real_reg is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real_20 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real_10 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: operator complexMult_111/_zz_product_real0 is absorbed into DSP complexMult_111/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_111/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_111/aiD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/mid_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/brD2_delay_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/brD2_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/arD1_delay_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_2_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_1_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: register complexMult_111/_zz_product_imag_reg is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag_20 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag_10 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: operator complexMult_111/_zz_product_imag0 is absorbed into DSP complexMult_111/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_112/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_112/coeff_imag_delay_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/arD1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/data_real_delay_2_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_4_port0_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/coeff_real_delay_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/mid_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/_zz_mid_1_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: register complexMult_112/_zz_mid_reg is absorbed into DSP complexMult_112/mid_reg.
DSP Report: operator complexMult_112/_zz_mid_10 is absorbed into DSP complexMult_112/mid_reg.
DSP Report: operator complexMult_112/_zz_mid0 is absorbed into DSP complexMult_112/mid_reg.
DSP Report: Generating DSP complexMult_112/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_112/biD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/biD2_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/data_real_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/arD1_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/mid_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/aiD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_2_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_1_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: register complexMult_112/_zz_product_real_reg is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real_20 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real_10 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: operator complexMult_112/_zz_product_real0 is absorbed into DSP complexMult_112/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_112/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_112/aiD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/mid_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/brD2_delay_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/brD2_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/arD1_delay_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_2_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_1_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: register complexMult_112/_zz_product_imag_reg is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag_20 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag_10 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: operator complexMult_112/_zz_product_imag0 is absorbed into DSP complexMult_112/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_113/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_113/coeff_imag_delay_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/arD1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/data_real_delay_2_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_5_port0_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/coeff_real_delay_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/mid_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/_zz_mid_1_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: register complexMult_113/_zz_mid_reg is absorbed into DSP complexMult_113/mid_reg.
DSP Report: operator complexMult_113/_zz_mid_10 is absorbed into DSP complexMult_113/mid_reg.
DSP Report: operator complexMult_113/_zz_mid0 is absorbed into DSP complexMult_113/mid_reg.
DSP Report: Generating DSP complexMult_113/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_113/biD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/biD2_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/data_real_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/arD1_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/mid_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/aiD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_2_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_1_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: register complexMult_113/_zz_product_real_reg is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real_20 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real_10 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: operator complexMult_113/_zz_product_real0 is absorbed into DSP complexMult_113/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_113/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_113/aiD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/mid_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/brD2_delay_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/brD2_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/arD1_delay_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_2_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_1_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: register complexMult_113/_zz_product_imag_reg is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag_20 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag_10 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: operator complexMult_113/_zz_product_imag0 is absorbed into DSP complexMult_113/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_114/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_114/coeff_imag_delay_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/arD1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/data_real_delay_2_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_6_port0_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/coeff_real_delay_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/mid_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/_zz_mid_1_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: register complexMult_114/_zz_mid_reg is absorbed into DSP complexMult_114/mid_reg.
DSP Report: operator complexMult_114/_zz_mid_10 is absorbed into DSP complexMult_114/mid_reg.
DSP Report: operator complexMult_114/_zz_mid0 is absorbed into DSP complexMult_114/mid_reg.
DSP Report: Generating DSP complexMult_114/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_114/biD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/biD2_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/data_real_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/arD1_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/mid_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/aiD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_2_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_1_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: register complexMult_114/_zz_product_real_reg is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real_20 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real_10 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: operator complexMult_114/_zz_product_real0 is absorbed into DSP complexMult_114/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_114/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_114/aiD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/mid_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/brD2_delay_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/brD2_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/arD1_delay_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_2_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_1_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: register complexMult_114/_zz_product_imag_reg is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag_20 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag_10 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: operator complexMult_114/_zz_product_imag0 is absorbed into DSP complexMult_114/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_115/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_115/coeff_imag_delay_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/arD1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/data_real_delay_2_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_7_port0_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/coeff_real_delay_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/mid_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/_zz_mid_1_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: register complexMult_115/_zz_mid_reg is absorbed into DSP complexMult_115/mid_reg.
DSP Report: operator complexMult_115/_zz_mid_10 is absorbed into DSP complexMult_115/mid_reg.
DSP Report: operator complexMult_115/_zz_mid0 is absorbed into DSP complexMult_115/mid_reg.
DSP Report: Generating DSP complexMult_115/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_115/biD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/biD2_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/data_real_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/arD1_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/mid_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/aiD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_2_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_1_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: register complexMult_115/_zz_product_real_reg is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real_20 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real_10 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: operator complexMult_115/_zz_product_real0 is absorbed into DSP complexMult_115/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_115/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_115/aiD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/mid_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/brD2_delay_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/brD2_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/arD1_delay_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_2_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_1_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: register complexMult_115/_zz_product_imag_reg is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag_20 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag_10 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: operator complexMult_115/_zz_product_imag0 is absorbed into DSP complexMult_115/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_116/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_116/coeff_imag_delay_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/arD1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/data_real_delay_2_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_8_port0_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/coeff_real_delay_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/mid_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/_zz_mid_1_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: register complexMult_116/_zz_mid_reg is absorbed into DSP complexMult_116/mid_reg.
DSP Report: operator complexMult_116/_zz_mid_10 is absorbed into DSP complexMult_116/mid_reg.
DSP Report: operator complexMult_116/_zz_mid0 is absorbed into DSP complexMult_116/mid_reg.
DSP Report: Generating DSP complexMult_116/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_116/biD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/biD2_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/data_real_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/arD1_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/mid_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/aiD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_2_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_1_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: register complexMult_116/_zz_product_real_reg is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real_20 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real_10 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: operator complexMult_116/_zz_product_real0 is absorbed into DSP complexMult_116/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_116/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_116/aiD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/mid_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/brD2_delay_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/brD2_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/arD1_delay_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_2_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_1_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: register complexMult_116/_zz_product_imag_reg is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag_20 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag_10 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: operator complexMult_116/_zz_product_imag0 is absorbed into DSP complexMult_116/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_117/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_117/coeff_imag_delay_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/arD1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/data_real_delay_2_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_9_port0_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/coeff_real_delay_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/mid_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/_zz_mid_1_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: register complexMult_117/_zz_mid_reg is absorbed into DSP complexMult_117/mid_reg.
DSP Report: operator complexMult_117/_zz_mid_10 is absorbed into DSP complexMult_117/mid_reg.
DSP Report: operator complexMult_117/_zz_mid0 is absorbed into DSP complexMult_117/mid_reg.
DSP Report: Generating DSP complexMult_117/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_117/biD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/biD2_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/data_real_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/arD1_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/mid_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/aiD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_2_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_1_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: register complexMult_117/_zz_product_real_reg is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real_20 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real_10 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: operator complexMult_117/_zz_product_real0 is absorbed into DSP complexMult_117/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_117/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_117/aiD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/mid_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/brD2_delay_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/brD2_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/arD1_delay_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_2_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_1_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: register complexMult_117/_zz_product_imag_reg is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag_20 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag_10 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: operator complexMult_117/_zz_product_imag0 is absorbed into DSP complexMult_117/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_118/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_118/coeff_imag_delay_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/arD1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/data_real_delay_2_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_10_port0_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/coeff_real_delay_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/mid_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/_zz_mid_1_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: register complexMult_118/_zz_mid_reg is absorbed into DSP complexMult_118/mid_reg.
DSP Report: operator complexMult_118/_zz_mid_10 is absorbed into DSP complexMult_118/mid_reg.
DSP Report: operator complexMult_118/_zz_mid0 is absorbed into DSP complexMult_118/mid_reg.
DSP Report: Generating DSP complexMult_118/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_118/biD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/biD2_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/data_real_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/arD1_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/mid_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/aiD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_2_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_1_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: register complexMult_118/_zz_product_real_reg is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real_20 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real_10 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: operator complexMult_118/_zz_product_real0 is absorbed into DSP complexMult_118/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_118/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_118/aiD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/mid_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/brD2_delay_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/brD2_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/arD1_delay_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_2_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_1_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: register complexMult_118/_zz_product_imag_reg is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag_20 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag_10 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: operator complexMult_118/_zz_product_imag0 is absorbed into DSP complexMult_118/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_119/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_119/coeff_imag_delay_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/arD1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/data_real_delay_2_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_11_port0_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/coeff_real_delay_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/mid_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/_zz_mid_1_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: register complexMult_119/_zz_mid_reg is absorbed into DSP complexMult_119/mid_reg.
DSP Report: operator complexMult_119/_zz_mid_10 is absorbed into DSP complexMult_119/mid_reg.
DSP Report: operator complexMult_119/_zz_mid0 is absorbed into DSP complexMult_119/mid_reg.
DSP Report: Generating DSP complexMult_119/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_119/biD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/biD2_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/data_real_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/arD1_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/mid_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/aiD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_2_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_1_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: register complexMult_119/_zz_product_real_reg is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real_20 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real_10 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: operator complexMult_119/_zz_product_real0 is absorbed into DSP complexMult_119/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_119/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_119/aiD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/mid_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/brD2_delay_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/brD2_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/arD1_delay_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_2_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_1_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: register complexMult_119/_zz_product_imag_reg is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag_20 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag_10 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: operator complexMult_119/_zz_product_imag0 is absorbed into DSP complexMult_119/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_120/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_120/coeff_imag_delay_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/arD1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/data_real_delay_2_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_12_port0_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/coeff_real_delay_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/mid_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/_zz_mid_1_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: register complexMult_120/_zz_mid_reg is absorbed into DSP complexMult_120/mid_reg.
DSP Report: operator complexMult_120/_zz_mid_10 is absorbed into DSP complexMult_120/mid_reg.
DSP Report: operator complexMult_120/_zz_mid0 is absorbed into DSP complexMult_120/mid_reg.
DSP Report: Generating DSP complexMult_120/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_120/biD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/biD2_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/data_real_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/arD1_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/mid_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/aiD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_2_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_1_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: register complexMult_120/_zz_product_real_reg is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real_20 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real_10 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: operator complexMult_120/_zz_product_real0 is absorbed into DSP complexMult_120/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_120/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_120/aiD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/mid_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/brD2_delay_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/brD2_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/arD1_delay_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_2_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_1_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: register complexMult_120/_zz_product_imag_reg is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag_20 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag_10 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: operator complexMult_120/_zz_product_imag0 is absorbed into DSP complexMult_120/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_121/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_121/coeff_imag_delay_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/arD1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/data_real_delay_2_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_13_port0_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/coeff_real_delay_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/mid_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/_zz_mid_1_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: register complexMult_121/_zz_mid_reg is absorbed into DSP complexMult_121/mid_reg.
DSP Report: operator complexMult_121/_zz_mid_10 is absorbed into DSP complexMult_121/mid_reg.
DSP Report: operator complexMult_121/_zz_mid0 is absorbed into DSP complexMult_121/mid_reg.
DSP Report: Generating DSP complexMult_121/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_121/biD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/biD2_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/data_real_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/arD1_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/mid_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/aiD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_2_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_1_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: register complexMult_121/_zz_product_real_reg is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real_20 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real_10 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: operator complexMult_121/_zz_product_real0 is absorbed into DSP complexMult_121/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_121/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_121/aiD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/mid_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/brD2_delay_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/brD2_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/arD1_delay_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_2_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_1_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: register complexMult_121/_zz_product_imag_reg is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag_20 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag_10 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: operator complexMult_121/_zz_product_imag0 is absorbed into DSP complexMult_121/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_122/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_122/coeff_imag_delay_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/arD1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/data_real_delay_2_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_14_port0_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/coeff_real_delay_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/mid_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/_zz_mid_1_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: register complexMult_122/_zz_mid_reg is absorbed into DSP complexMult_122/mid_reg.
DSP Report: operator complexMult_122/_zz_mid_10 is absorbed into DSP complexMult_122/mid_reg.
DSP Report: operator complexMult_122/_zz_mid0 is absorbed into DSP complexMult_122/mid_reg.
DSP Report: Generating DSP complexMult_122/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_122/biD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/biD2_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/data_real_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/arD1_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/mid_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/aiD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_2_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_1_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: register complexMult_122/_zz_product_real_reg is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real_20 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real_10 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: operator complexMult_122/_zz_product_real0 is absorbed into DSP complexMult_122/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_122/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_122/aiD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/mid_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/brD2_delay_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/brD2_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/arD1_delay_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_2_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_1_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: register complexMult_122/_zz_product_imag_reg is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag_20 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag_10 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: operator complexMult_122/_zz_product_imag0 is absorbed into DSP complexMult_122/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_123/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_123/coeff_imag_delay_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/arD1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/data_real_delay_2_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_15_port0_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/coeff_real_delay_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/mid_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/_zz_mid_1_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: register complexMult_123/_zz_mid_reg is absorbed into DSP complexMult_123/mid_reg.
DSP Report: operator complexMult_123/_zz_mid_10 is absorbed into DSP complexMult_123/mid_reg.
DSP Report: operator complexMult_123/_zz_mid0 is absorbed into DSP complexMult_123/mid_reg.
DSP Report: Generating DSP complexMult_123/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_123/biD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/biD2_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/data_real_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/arD1_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/mid_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/aiD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_2_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_1_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: register complexMult_123/_zz_product_real_reg is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real_20 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real_10 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: operator complexMult_123/_zz_product_real0 is absorbed into DSP complexMult_123/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_123/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_123/aiD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/mid_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/brD2_delay_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/brD2_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/arD1_delay_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_2_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_1_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: register complexMult_123/_zz_product_imag_reg is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag_20 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag_10 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: operator complexMult_123/_zz_product_imag0 is absorbed into DSP complexMult_123/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_124/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_124/coeff_imag_delay_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/arD1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/data_real_delay_2_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_16_port0_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/coeff_real_delay_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/mid_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/_zz_mid_1_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: register complexMult_124/_zz_mid_reg is absorbed into DSP complexMult_124/mid_reg.
DSP Report: operator complexMult_124/_zz_mid_10 is absorbed into DSP complexMult_124/mid_reg.
DSP Report: operator complexMult_124/_zz_mid0 is absorbed into DSP complexMult_124/mid_reg.
DSP Report: Generating DSP complexMult_124/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_124/biD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/biD2_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/data_real_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/arD1_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/mid_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/aiD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_2_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_1_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: register complexMult_124/_zz_product_real_reg is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real_20 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real_10 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: operator complexMult_124/_zz_product_real0 is absorbed into DSP complexMult_124/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_124/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_124/aiD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/mid_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/brD2_delay_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/brD2_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/arD1_delay_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_2_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_1_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: register complexMult_124/_zz_product_imag_reg is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag_20 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag_10 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: operator complexMult_124/_zz_product_imag0 is absorbed into DSP complexMult_124/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_125/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_125/coeff_imag_delay_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/arD1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/data_real_delay_2_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_17_port0_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/coeff_real_delay_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/mid_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/_zz_mid_1_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: register complexMult_125/_zz_mid_reg is absorbed into DSP complexMult_125/mid_reg.
DSP Report: operator complexMult_125/_zz_mid_10 is absorbed into DSP complexMult_125/mid_reg.
DSP Report: operator complexMult_125/_zz_mid0 is absorbed into DSP complexMult_125/mid_reg.
DSP Report: Generating DSP complexMult_125/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_125/biD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/biD2_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/data_real_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/arD1_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/mid_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/aiD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_2_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_1_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: register complexMult_125/_zz_product_real_reg is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real_20 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real_10 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: operator complexMult_125/_zz_product_real0 is absorbed into DSP complexMult_125/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_125/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_125/aiD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/mid_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/brD2_delay_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/brD2_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/arD1_delay_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_2_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_1_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: register complexMult_125/_zz_product_imag_reg is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag_20 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag_10 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: operator complexMult_125/_zz_product_imag0 is absorbed into DSP complexMult_125/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_126/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_126/coeff_imag_delay_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/arD1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/data_real_delay_2_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_18_port0_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/coeff_real_delay_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/mid_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/_zz_mid_1_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: register complexMult_126/_zz_mid_reg is absorbed into DSP complexMult_126/mid_reg.
DSP Report: operator complexMult_126/_zz_mid_10 is absorbed into DSP complexMult_126/mid_reg.
DSP Report: operator complexMult_126/_zz_mid0 is absorbed into DSP complexMult_126/mid_reg.
DSP Report: Generating DSP complexMult_126/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_126/biD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/biD2_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/data_real_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/arD1_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/mid_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/aiD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_2_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_1_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: register complexMult_126/_zz_product_real_reg is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real_20 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real_10 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: operator complexMult_126/_zz_product_real0 is absorbed into DSP complexMult_126/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_126/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_126/aiD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/mid_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/brD2_delay_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/brD2_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/arD1_delay_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_2_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_1_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: register complexMult_126/_zz_product_imag_reg is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag_20 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag_10 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: operator complexMult_126/_zz_product_imag0 is absorbed into DSP complexMult_126/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_127/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_127/coeff_imag_delay_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/arD1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/data_real_delay_2_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_19_port0_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/coeff_real_delay_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/mid_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/_zz_mid_1_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: register complexMult_127/_zz_mid_reg is absorbed into DSP complexMult_127/mid_reg.
DSP Report: operator complexMult_127/_zz_mid_10 is absorbed into DSP complexMult_127/mid_reg.
DSP Report: operator complexMult_127/_zz_mid0 is absorbed into DSP complexMult_127/mid_reg.
DSP Report: Generating DSP complexMult_127/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_127/biD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/biD2_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/data_real_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/arD1_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/mid_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/aiD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_2_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_1_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: register complexMult_127/_zz_product_real_reg is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real_20 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real_10 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: operator complexMult_127/_zz_product_real0 is absorbed into DSP complexMult_127/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_127/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_127/aiD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/mid_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/brD2_delay_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/brD2_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/arD1_delay_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_2_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_1_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: register complexMult_127/_zz_product_imag_reg is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag_20 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag_10 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: operator complexMult_127/_zz_product_imag0 is absorbed into DSP complexMult_127/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_128/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_128/coeff_imag_delay_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/arD1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/data_real_delay_2_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_20_port0_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/coeff_real_delay_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/mid_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/_zz_mid_1_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: register complexMult_128/_zz_mid_reg is absorbed into DSP complexMult_128/mid_reg.
DSP Report: operator complexMult_128/_zz_mid_10 is absorbed into DSP complexMult_128/mid_reg.
DSP Report: operator complexMult_128/_zz_mid0 is absorbed into DSP complexMult_128/mid_reg.
DSP Report: Generating DSP complexMult_128/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_128/biD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/biD2_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/data_real_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/arD1_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/mid_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/aiD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_2_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_1_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: register complexMult_128/_zz_product_real_reg is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real_20 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real_10 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: operator complexMult_128/_zz_product_real0 is absorbed into DSP complexMult_128/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_128/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_128/aiD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/mid_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/brD2_delay_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/brD2_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/arD1_delay_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_2_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_1_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: register complexMult_128/_zz_product_imag_reg is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag_20 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag_10 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: operator complexMult_128/_zz_product_imag0 is absorbed into DSP complexMult_128/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_129/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_129/coeff_imag_delay_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/arD1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/data_real_delay_2_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_21_port0_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/coeff_real_delay_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/mid_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/_zz_mid_1_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: register complexMult_129/_zz_mid_reg is absorbed into DSP complexMult_129/mid_reg.
DSP Report: operator complexMult_129/_zz_mid_10 is absorbed into DSP complexMult_129/mid_reg.
DSP Report: operator complexMult_129/_zz_mid0 is absorbed into DSP complexMult_129/mid_reg.
DSP Report: Generating DSP complexMult_129/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_129/biD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/biD2_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/data_real_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/arD1_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/mid_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/aiD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_2_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_1_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: register complexMult_129/_zz_product_real_reg is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real_20 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real_10 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: operator complexMult_129/_zz_product_real0 is absorbed into DSP complexMult_129/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_129/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_129/aiD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/mid_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/brD2_delay_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/brD2_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/arD1_delay_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_2_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_1_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: register complexMult_129/_zz_product_imag_reg is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag_20 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag_10 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: operator complexMult_129/_zz_product_imag0 is absorbed into DSP complexMult_129/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_130/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_130/coeff_imag_delay_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/arD1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/data_real_delay_2_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_22_port0_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/coeff_real_delay_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/mid_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/_zz_mid_1_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: register complexMult_130/_zz_mid_reg is absorbed into DSP complexMult_130/mid_reg.
DSP Report: operator complexMult_130/_zz_mid_10 is absorbed into DSP complexMult_130/mid_reg.
DSP Report: operator complexMult_130/_zz_mid0 is absorbed into DSP complexMult_130/mid_reg.
DSP Report: Generating DSP complexMult_130/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_130/biD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/biD2_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/data_real_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/arD1_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/mid_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/aiD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_2_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_1_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: register complexMult_130/_zz_product_real_reg is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real_20 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real_10 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: operator complexMult_130/_zz_product_real0 is absorbed into DSP complexMult_130/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_130/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_130/aiD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/mid_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/brD2_delay_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/brD2_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/arD1_delay_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_2_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_1_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: register complexMult_130/_zz_product_imag_reg is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag_20 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag_10 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: operator complexMult_130/_zz_product_imag0 is absorbed into DSP complexMult_130/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_131/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_131/coeff_imag_delay_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/arD1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/data_real_delay_2_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_23_port0_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/coeff_real_delay_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/mid_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/_zz_mid_1_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: register complexMult_131/_zz_mid_reg is absorbed into DSP complexMult_131/mid_reg.
DSP Report: operator complexMult_131/_zz_mid_10 is absorbed into DSP complexMult_131/mid_reg.
DSP Report: operator complexMult_131/_zz_mid0 is absorbed into DSP complexMult_131/mid_reg.
DSP Report: Generating DSP complexMult_131/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_131/biD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/biD2_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/data_real_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/arD1_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/mid_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/aiD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_2_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_1_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: register complexMult_131/_zz_product_real_reg is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real_20 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real_10 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: operator complexMult_131/_zz_product_real0 is absorbed into DSP complexMult_131/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_131/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_131/aiD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/mid_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/brD2_delay_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/brD2_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/arD1_delay_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_2_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_1_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: register complexMult_131/_zz_product_imag_reg is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag_20 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag_10 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: operator complexMult_131/_zz_product_imag0 is absorbed into DSP complexMult_131/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_132/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_132/coeff_imag_delay_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/arD1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/data_real_delay_2_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_24_port0_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/coeff_real_delay_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/mid_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/_zz_mid_1_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: register complexMult_132/_zz_mid_reg is absorbed into DSP complexMult_132/mid_reg.
DSP Report: operator complexMult_132/_zz_mid_10 is absorbed into DSP complexMult_132/mid_reg.
DSP Report: operator complexMult_132/_zz_mid0 is absorbed into DSP complexMult_132/mid_reg.
DSP Report: Generating DSP complexMult_132/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_132/biD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/biD2_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/data_real_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/arD1_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/mid_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/aiD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_2_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_1_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: register complexMult_132/_zz_product_real_reg is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real_20 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real_10 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: operator complexMult_132/_zz_product_real0 is absorbed into DSP complexMult_132/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_132/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_132/aiD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/mid_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/brD2_delay_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/brD2_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/arD1_delay_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_2_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_1_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: register complexMult_132/_zz_product_imag_reg is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag_20 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag_10 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: operator complexMult_132/_zz_product_imag0 is absorbed into DSP complexMult_132/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_133/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_133/coeff_imag_delay_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/arD1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/data_real_delay_2_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_25_port0_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/coeff_real_delay_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/mid_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/_zz_mid_1_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: register complexMult_133/_zz_mid_reg is absorbed into DSP complexMult_133/mid_reg.
DSP Report: operator complexMult_133/_zz_mid_10 is absorbed into DSP complexMult_133/mid_reg.
DSP Report: operator complexMult_133/_zz_mid0 is absorbed into DSP complexMult_133/mid_reg.
DSP Report: Generating DSP complexMult_133/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_133/biD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/biD2_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/data_real_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/arD1_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/mid_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/aiD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_2_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_1_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: register complexMult_133/_zz_product_real_reg is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real_20 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real_10 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: operator complexMult_133/_zz_product_real0 is absorbed into DSP complexMult_133/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_133/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_133/aiD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/mid_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/brD2_delay_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/brD2_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/arD1_delay_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_2_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_1_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: register complexMult_133/_zz_product_imag_reg is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag_20 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag_10 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: operator complexMult_133/_zz_product_imag0 is absorbed into DSP complexMult_133/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_134/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_134/coeff_imag_delay_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/arD1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/data_real_delay_2_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_26_port0_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/coeff_real_delay_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/mid_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/_zz_mid_1_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: register complexMult_134/_zz_mid_reg is absorbed into DSP complexMult_134/mid_reg.
DSP Report: operator complexMult_134/_zz_mid_10 is absorbed into DSP complexMult_134/mid_reg.
DSP Report: operator complexMult_134/_zz_mid0 is absorbed into DSP complexMult_134/mid_reg.
DSP Report: Generating DSP complexMult_134/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_134/biD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/biD2_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/data_real_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/arD1_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/mid_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/aiD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_2_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_1_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: register complexMult_134/_zz_product_real_reg is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real_20 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real_10 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: operator complexMult_134/_zz_product_real0 is absorbed into DSP complexMult_134/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_134/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_134/aiD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/mid_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/brD2_delay_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/brD2_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/arD1_delay_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_2_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_1_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: register complexMult_134/_zz_product_imag_reg is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag_20 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag_10 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: operator complexMult_134/_zz_product_imag0 is absorbed into DSP complexMult_134/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_135/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_135/coeff_imag_delay_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/arD1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/data_real_delay_2_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_27_port0_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/coeff_real_delay_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/mid_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/_zz_mid_1_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: register complexMult_135/_zz_mid_reg is absorbed into DSP complexMult_135/mid_reg.
DSP Report: operator complexMult_135/_zz_mid_10 is absorbed into DSP complexMult_135/mid_reg.
DSP Report: operator complexMult_135/_zz_mid0 is absorbed into DSP complexMult_135/mid_reg.
DSP Report: Generating DSP complexMult_135/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_135/biD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/biD2_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/data_real_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/arD1_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/mid_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/aiD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_2_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_1_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: register complexMult_135/_zz_product_real_reg is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real_20 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real_10 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: operator complexMult_135/_zz_product_real0 is absorbed into DSP complexMult_135/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_135/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_135/aiD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/mid_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/brD2_delay_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/brD2_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/arD1_delay_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_2_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_1_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: register complexMult_135/_zz_product_imag_reg is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag_20 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag_10 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: operator complexMult_135/_zz_product_imag0 is absorbed into DSP complexMult_135/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_136/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_136/coeff_imag_delay_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/arD1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/data_real_delay_2_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_28_port0_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/coeff_real_delay_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/mid_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/_zz_mid_1_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: register complexMult_136/_zz_mid_reg is absorbed into DSP complexMult_136/mid_reg.
DSP Report: operator complexMult_136/_zz_mid_10 is absorbed into DSP complexMult_136/mid_reg.
DSP Report: operator complexMult_136/_zz_mid0 is absorbed into DSP complexMult_136/mid_reg.
DSP Report: Generating DSP complexMult_136/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_136/biD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/biD2_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/data_real_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/arD1_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/mid_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/aiD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_2_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_1_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: register complexMult_136/_zz_product_real_reg is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real_20 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real_10 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: operator complexMult_136/_zz_product_real0 is absorbed into DSP complexMult_136/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_136/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_136/aiD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/mid_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/brD2_delay_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/brD2_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/arD1_delay_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_2_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_1_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: register complexMult_136/_zz_product_imag_reg is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag_20 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag_10 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: operator complexMult_136/_zz_product_imag0 is absorbed into DSP complexMult_136/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_137/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_137/coeff_imag_delay_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/arD1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/data_real_delay_2_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_29_port0_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/coeff_real_delay_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/mid_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/_zz_mid_1_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: register complexMult_137/_zz_mid_reg is absorbed into DSP complexMult_137/mid_reg.
DSP Report: operator complexMult_137/_zz_mid_10 is absorbed into DSP complexMult_137/mid_reg.
DSP Report: operator complexMult_137/_zz_mid0 is absorbed into DSP complexMult_137/mid_reg.
DSP Report: Generating DSP complexMult_137/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_137/biD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/biD2_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/data_real_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/arD1_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/mid_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/aiD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_2_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_1_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: register complexMult_137/_zz_product_real_reg is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real_20 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real_10 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: operator complexMult_137/_zz_product_real0 is absorbed into DSP complexMult_137/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_137/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_137/aiD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/mid_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/brD2_delay_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/brD2_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/arD1_delay_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_2_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_1_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: register complexMult_137/_zz_product_imag_reg is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag_20 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag_10 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: operator complexMult_137/_zz_product_imag0 is absorbed into DSP complexMult_137/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_138/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_138/coeff_imag_delay_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/arD1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/data_real_delay_2_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_30_port0_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/coeff_real_delay_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/mid_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/_zz_mid_1_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: register complexMult_138/_zz_mid_reg is absorbed into DSP complexMult_138/mid_reg.
DSP Report: operator complexMult_138/_zz_mid_10 is absorbed into DSP complexMult_138/mid_reg.
DSP Report: operator complexMult_138/_zz_mid0 is absorbed into DSP complexMult_138/mid_reg.
DSP Report: Generating DSP complexMult_138/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_138/biD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/biD2_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/data_real_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/arD1_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/mid_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/aiD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_2_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_1_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: register complexMult_138/_zz_product_real_reg is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real_20 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real_10 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: operator complexMult_138/_zz_product_real0 is absorbed into DSP complexMult_138/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_138/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_138/aiD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/mid_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/brD2_delay_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/brD2_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/arD1_delay_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_2_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_1_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: register complexMult_138/_zz_product_imag_reg is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag_20 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag_10 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: operator complexMult_138/_zz_product_imag0 is absorbed into DSP complexMult_138/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_139/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_139/coeff_imag_delay_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/arD1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/data_real_delay_2_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_31_port0_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/coeff_real_delay_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/mid_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/_zz_mid_1_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: register complexMult_139/_zz_mid_reg is absorbed into DSP complexMult_139/mid_reg.
DSP Report: operator complexMult_139/_zz_mid_10 is absorbed into DSP complexMult_139/mid_reg.
DSP Report: operator complexMult_139/_zz_mid0 is absorbed into DSP complexMult_139/mid_reg.
DSP Report: Generating DSP complexMult_139/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_139/biD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/biD2_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/data_real_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/arD1_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/mid_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/aiD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_2_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_1_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: register complexMult_139/_zz_product_real_reg is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real_20 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real_10 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: operator complexMult_139/_zz_product_real0 is absorbed into DSP complexMult_139/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_139/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_139/aiD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/mid_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/brD2_delay_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/brD2_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/arD1_delay_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_2_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_1_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: register complexMult_139/_zz_product_imag_reg is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag_20 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag_10 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: operator complexMult_139/_zz_product_imag0 is absorbed into DSP complexMult_139/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_140/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_140/coeff_imag_delay_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/arD1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/data_real_delay_2_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_32_port0_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/coeff_real_delay_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/mid_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/_zz_mid_1_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: register complexMult_140/_zz_mid_reg is absorbed into DSP complexMult_140/mid_reg.
DSP Report: operator complexMult_140/_zz_mid_10 is absorbed into DSP complexMult_140/mid_reg.
DSP Report: operator complexMult_140/_zz_mid0 is absorbed into DSP complexMult_140/mid_reg.
DSP Report: Generating DSP complexMult_140/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_140/biD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/biD2_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/data_real_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/arD1_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/mid_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/aiD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_2_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_1_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: register complexMult_140/_zz_product_real_reg is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real_20 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real_10 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: operator complexMult_140/_zz_product_real0 is absorbed into DSP complexMult_140/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_140/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_140/aiD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/mid_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/brD2_delay_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/brD2_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/arD1_delay_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_2_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_1_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: register complexMult_140/_zz_product_imag_reg is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag_20 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag_10 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: operator complexMult_140/_zz_product_imag0 is absorbed into DSP complexMult_140/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_141/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_141/coeff_imag_delay_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/arD1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/data_real_delay_2_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_33_port0_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/coeff_real_delay_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/mid_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/_zz_mid_1_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: register complexMult_141/_zz_mid_reg is absorbed into DSP complexMult_141/mid_reg.
DSP Report: operator complexMult_141/_zz_mid_10 is absorbed into DSP complexMult_141/mid_reg.
DSP Report: operator complexMult_141/_zz_mid0 is absorbed into DSP complexMult_141/mid_reg.
DSP Report: Generating DSP complexMult_141/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_141/biD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/biD2_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/data_real_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/arD1_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/mid_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/aiD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_2_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_1_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: register complexMult_141/_zz_product_real_reg is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real_20 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real_10 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: operator complexMult_141/_zz_product_real0 is absorbed into DSP complexMult_141/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_141/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_141/aiD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/mid_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/brD2_delay_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/brD2_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/arD1_delay_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_2_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_1_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: register complexMult_141/_zz_product_imag_reg is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag_20 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag_10 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: operator complexMult_141/_zz_product_imag0 is absorbed into DSP complexMult_141/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_142/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_142/coeff_imag_delay_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/arD1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/data_real_delay_2_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_34_port0_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/coeff_real_delay_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/mid_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/_zz_mid_1_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: register complexMult_142/_zz_mid_reg is absorbed into DSP complexMult_142/mid_reg.
DSP Report: operator complexMult_142/_zz_mid_10 is absorbed into DSP complexMult_142/mid_reg.
DSP Report: operator complexMult_142/_zz_mid0 is absorbed into DSP complexMult_142/mid_reg.
DSP Report: Generating DSP complexMult_142/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_142/biD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/biD2_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/data_real_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/arD1_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/mid_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/aiD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_2_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_1_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: register complexMult_142/_zz_product_real_reg is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real_20 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real_10 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: operator complexMult_142/_zz_product_real0 is absorbed into DSP complexMult_142/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_142/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_142/aiD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/mid_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/brD2_delay_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/brD2_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/arD1_delay_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_2_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_1_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: register complexMult_142/_zz_product_imag_reg is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag_20 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag_10 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: operator complexMult_142/_zz_product_imag0 is absorbed into DSP complexMult_142/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_143/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_143/coeff_imag_delay_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/arD1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/data_real_delay_2_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_35_port0_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/coeff_real_delay_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/mid_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/_zz_mid_1_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: register complexMult_143/_zz_mid_reg is absorbed into DSP complexMult_143/mid_reg.
DSP Report: operator complexMult_143/_zz_mid_10 is absorbed into DSP complexMult_143/mid_reg.
DSP Report: operator complexMult_143/_zz_mid0 is absorbed into DSP complexMult_143/mid_reg.
DSP Report: Generating DSP complexMult_143/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_143/biD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/biD2_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/data_real_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/arD1_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/mid_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/aiD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_2_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_1_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: register complexMult_143/_zz_product_real_reg is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real_20 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real_10 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: operator complexMult_143/_zz_product_real0 is absorbed into DSP complexMult_143/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_143/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_143/aiD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/mid_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/brD2_delay_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/brD2_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/arD1_delay_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_2_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_1_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: register complexMult_143/_zz_product_imag_reg is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag_20 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag_10 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: operator complexMult_143/_zz_product_imag0 is absorbed into DSP complexMult_143/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_144/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_144/coeff_imag_delay_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/arD1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/data_real_delay_2_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_36_port0_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/coeff_real_delay_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/mid_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/_zz_mid_1_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: register complexMult_144/_zz_mid_reg is absorbed into DSP complexMult_144/mid_reg.
DSP Report: operator complexMult_144/_zz_mid_10 is absorbed into DSP complexMult_144/mid_reg.
DSP Report: operator complexMult_144/_zz_mid0 is absorbed into DSP complexMult_144/mid_reg.
DSP Report: Generating DSP complexMult_144/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_144/biD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/biD2_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/data_real_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/arD1_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/mid_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/aiD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_2_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_1_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: register complexMult_144/_zz_product_real_reg is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real_20 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real_10 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: operator complexMult_144/_zz_product_real0 is absorbed into DSP complexMult_144/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_144/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_144/aiD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/mid_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/brD2_delay_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/brD2_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/arD1_delay_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_2_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_1_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: register complexMult_144/_zz_product_imag_reg is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag_20 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag_10 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: operator complexMult_144/_zz_product_imag0 is absorbed into DSP complexMult_144/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_145/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_145/coeff_imag_delay_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/arD1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/data_real_delay_2_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_37_port0_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/coeff_real_delay_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/mid_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/_zz_mid_1_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: register complexMult_145/_zz_mid_reg is absorbed into DSP complexMult_145/mid_reg.
DSP Report: operator complexMult_145/_zz_mid_10 is absorbed into DSP complexMult_145/mid_reg.
DSP Report: operator complexMult_145/_zz_mid0 is absorbed into DSP complexMult_145/mid_reg.
DSP Report: Generating DSP complexMult_145/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_145/biD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/biD2_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/data_real_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/arD1_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/mid_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/aiD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_2_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_1_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: register complexMult_145/_zz_product_real_reg is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real_20 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real_10 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: operator complexMult_145/_zz_product_real0 is absorbed into DSP complexMult_145/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_145/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_145/aiD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/mid_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/brD2_delay_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/brD2_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/arD1_delay_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_2_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_1_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: register complexMult_145/_zz_product_imag_reg is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag_20 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag_10 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: operator complexMult_145/_zz_product_imag0 is absorbed into DSP complexMult_145/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_146/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_146/coeff_imag_delay_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/arD1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/data_real_delay_2_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_38_port0_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/coeff_real_delay_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/mid_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/_zz_mid_1_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: register complexMult_146/_zz_mid_reg is absorbed into DSP complexMult_146/mid_reg.
DSP Report: operator complexMult_146/_zz_mid_10 is absorbed into DSP complexMult_146/mid_reg.
DSP Report: operator complexMult_146/_zz_mid0 is absorbed into DSP complexMult_146/mid_reg.
DSP Report: Generating DSP complexMult_146/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_146/biD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/biD2_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/data_real_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/arD1_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/mid_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/aiD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_2_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_1_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: register complexMult_146/_zz_product_real_reg is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real_20 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real_10 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: operator complexMult_146/_zz_product_real0 is absorbed into DSP complexMult_146/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_146/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_146/aiD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/mid_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/brD2_delay_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/brD2_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/arD1_delay_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_2_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_1_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: register complexMult_146/_zz_product_imag_reg is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag_20 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag_10 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: operator complexMult_146/_zz_product_imag0 is absorbed into DSP complexMult_146/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_147/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_147/coeff_imag_delay_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/arD1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/data_real_delay_2_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_39_port0_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/coeff_real_delay_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/mid_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/_zz_mid_1_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: register complexMult_147/_zz_mid_reg is absorbed into DSP complexMult_147/mid_reg.
DSP Report: operator complexMult_147/_zz_mid_10 is absorbed into DSP complexMult_147/mid_reg.
DSP Report: operator complexMult_147/_zz_mid0 is absorbed into DSP complexMult_147/mid_reg.
DSP Report: Generating DSP complexMult_147/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_147/biD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/biD2_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/data_real_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/arD1_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/mid_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/aiD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_2_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_1_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: register complexMult_147/_zz_product_real_reg is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real_20 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real_10 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: operator complexMult_147/_zz_product_real0 is absorbed into DSP complexMult_147/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_147/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_147/aiD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/mid_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/brD2_delay_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/brD2_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/arD1_delay_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_2_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_1_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: register complexMult_147/_zz_product_imag_reg is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag_20 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag_10 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: operator complexMult_147/_zz_product_imag0 is absorbed into DSP complexMult_147/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_148/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_148/coeff_imag_delay_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/arD1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/data_real_delay_2_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_40_port0_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/coeff_real_delay_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/mid_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/_zz_mid_1_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: register complexMult_148/_zz_mid_reg is absorbed into DSP complexMult_148/mid_reg.
DSP Report: operator complexMult_148/_zz_mid_10 is absorbed into DSP complexMult_148/mid_reg.
DSP Report: operator complexMult_148/_zz_mid0 is absorbed into DSP complexMult_148/mid_reg.
DSP Report: Generating DSP complexMult_148/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_148/biD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/biD2_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/data_real_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/arD1_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/mid_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/aiD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_2_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_1_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: register complexMult_148/_zz_product_real_reg is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real_20 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real_10 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: operator complexMult_148/_zz_product_real0 is absorbed into DSP complexMult_148/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_148/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_148/aiD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/mid_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/brD2_delay_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/brD2_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/arD1_delay_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_2_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_1_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: register complexMult_148/_zz_product_imag_reg is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag_20 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag_10 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: operator complexMult_148/_zz_product_imag0 is absorbed into DSP complexMult_148/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_149/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_149/coeff_imag_delay_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/arD1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/data_real_delay_2_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_41_port0_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/coeff_real_delay_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/mid_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/_zz_mid_1_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: register complexMult_149/_zz_mid_reg is absorbed into DSP complexMult_149/mid_reg.
DSP Report: operator complexMult_149/_zz_mid_10 is absorbed into DSP complexMult_149/mid_reg.
DSP Report: operator complexMult_149/_zz_mid0 is absorbed into DSP complexMult_149/mid_reg.
DSP Report: Generating DSP complexMult_149/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_149/biD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/biD2_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/data_real_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/arD1_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/mid_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/aiD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_2_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_1_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: register complexMult_149/_zz_product_real_reg is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real_20 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real_10 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: operator complexMult_149/_zz_product_real0 is absorbed into DSP complexMult_149/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_149/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_149/aiD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/mid_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/brD2_delay_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/brD2_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/arD1_delay_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_2_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_1_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: register complexMult_149/_zz_product_imag_reg is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag_20 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag_10 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: operator complexMult_149/_zz_product_imag0 is absorbed into DSP complexMult_149/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_150/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_150/coeff_imag_delay_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/arD1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/data_real_delay_2_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_42_port0_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/coeff_real_delay_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/mid_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/_zz_mid_1_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: register complexMult_150/_zz_mid_reg is absorbed into DSP complexMult_150/mid_reg.
DSP Report: operator complexMult_150/_zz_mid_10 is absorbed into DSP complexMult_150/mid_reg.
DSP Report: operator complexMult_150/_zz_mid0 is absorbed into DSP complexMult_150/mid_reg.
DSP Report: Generating DSP complexMult_150/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_150/biD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/biD2_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/data_real_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/arD1_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/mid_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/aiD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_2_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_1_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: register complexMult_150/_zz_product_real_reg is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real_20 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real_10 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: operator complexMult_150/_zz_product_real0 is absorbed into DSP complexMult_150/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_150/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_150/aiD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/mid_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/brD2_delay_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/brD2_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/arD1_delay_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_2_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_1_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: register complexMult_150/_zz_product_imag_reg is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag_20 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag_10 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: operator complexMult_150/_zz_product_imag0 is absorbed into DSP complexMult_150/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_151/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_151/coeff_imag_delay_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/arD1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/data_real_delay_2_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_43_port0_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/coeff_real_delay_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/mid_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/_zz_mid_1_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: register complexMult_151/_zz_mid_reg is absorbed into DSP complexMult_151/mid_reg.
DSP Report: operator complexMult_151/_zz_mid_10 is absorbed into DSP complexMult_151/mid_reg.
DSP Report: operator complexMult_151/_zz_mid0 is absorbed into DSP complexMult_151/mid_reg.
DSP Report: Generating DSP complexMult_151/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_151/biD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/biD2_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/data_real_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/arD1_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/mid_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/aiD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_2_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_1_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: register complexMult_151/_zz_product_real_reg is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real_20 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real_10 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: operator complexMult_151/_zz_product_real0 is absorbed into DSP complexMult_151/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_151/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_151/aiD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/mid_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/brD2_delay_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/brD2_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/arD1_delay_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_2_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_1_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: register complexMult_151/_zz_product_imag_reg is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag_20 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag_10 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: operator complexMult_151/_zz_product_imag0 is absorbed into DSP complexMult_151/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_152/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_152/coeff_imag_delay_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/arD1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/data_real_delay_2_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_44_port0_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/coeff_real_delay_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/mid_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/_zz_mid_1_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: register complexMult_152/_zz_mid_reg is absorbed into DSP complexMult_152/mid_reg.
DSP Report: operator complexMult_152/_zz_mid_10 is absorbed into DSP complexMult_152/mid_reg.
DSP Report: operator complexMult_152/_zz_mid0 is absorbed into DSP complexMult_152/mid_reg.
DSP Report: Generating DSP complexMult_152/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_152/biD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/biD2_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/data_real_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/arD1_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/mid_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/aiD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_2_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_1_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: register complexMult_152/_zz_product_real_reg is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real_20 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real_10 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: operator complexMult_152/_zz_product_real0 is absorbed into DSP complexMult_152/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_152/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_152/aiD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/mid_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/brD2_delay_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/brD2_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/arD1_delay_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_2_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_1_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: register complexMult_152/_zz_product_imag_reg is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag_20 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag_10 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: operator complexMult_152/_zz_product_imag0 is absorbed into DSP complexMult_152/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_153/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_153/coeff_imag_delay_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/arD1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/data_real_delay_2_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_45_port0_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/coeff_real_delay_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/mid_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/_zz_mid_1_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: register complexMult_153/_zz_mid_reg is absorbed into DSP complexMult_153/mid_reg.
DSP Report: operator complexMult_153/_zz_mid_10 is absorbed into DSP complexMult_153/mid_reg.
DSP Report: operator complexMult_153/_zz_mid0 is absorbed into DSP complexMult_153/mid_reg.
DSP Report: Generating DSP complexMult_153/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_153/biD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/biD2_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/data_real_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/arD1_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/mid_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/aiD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_2_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_1_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: register complexMult_153/_zz_product_real_reg is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real_20 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real_10 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: operator complexMult_153/_zz_product_real0 is absorbed into DSP complexMult_153/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_153/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_153/aiD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/mid_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/brD2_delay_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/brD2_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/arD1_delay_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_2_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_1_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: register complexMult_153/_zz_product_imag_reg is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag_20 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag_10 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: operator complexMult_153/_zz_product_imag0 is absorbed into DSP complexMult_153/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_154/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_154/coeff_imag_delay_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/arD1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/data_real_delay_2_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_46_port0_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/coeff_real_delay_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/mid_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/_zz_mid_1_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: register complexMult_154/_zz_mid_reg is absorbed into DSP complexMult_154/mid_reg.
DSP Report: operator complexMult_154/_zz_mid_10 is absorbed into DSP complexMult_154/mid_reg.
DSP Report: operator complexMult_154/_zz_mid0 is absorbed into DSP complexMult_154/mid_reg.
DSP Report: Generating DSP complexMult_154/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_154/biD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/biD2_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/data_real_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/arD1_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/mid_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/aiD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_2_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_1_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: register complexMult_154/_zz_product_real_reg is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real_20 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real_10 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: operator complexMult_154/_zz_product_real0 is absorbed into DSP complexMult_154/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_154/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_154/aiD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/mid_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/brD2_delay_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/brD2_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/arD1_delay_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_2_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_1_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: register complexMult_154/_zz_product_imag_reg is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag_20 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag_10 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: operator complexMult_154/_zz_product_imag0 is absorbed into DSP complexMult_154/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_155/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_155/coeff_imag_delay_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/arD1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/data_real_delay_2_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_47_port0_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/coeff_real_delay_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/mid_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/_zz_mid_1_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: register complexMult_155/_zz_mid_reg is absorbed into DSP complexMult_155/mid_reg.
DSP Report: operator complexMult_155/_zz_mid_10 is absorbed into DSP complexMult_155/mid_reg.
DSP Report: operator complexMult_155/_zz_mid0 is absorbed into DSP complexMult_155/mid_reg.
DSP Report: Generating DSP complexMult_155/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_155/biD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/biD2_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/data_real_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/arD1_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/mid_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/aiD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_2_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_1_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: register complexMult_155/_zz_product_real_reg is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real_20 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real_10 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: operator complexMult_155/_zz_product_real0 is absorbed into DSP complexMult_155/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_155/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_155/aiD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/mid_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/brD2_delay_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/brD2_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/arD1_delay_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_2_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_1_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: register complexMult_155/_zz_product_imag_reg is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag_20 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag_10 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: operator complexMult_155/_zz_product_imag0 is absorbed into DSP complexMult_155/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_156/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_156/coeff_imag_delay_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/arD1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/data_real_delay_2_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_48_port0_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/coeff_real_delay_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/mid_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/_zz_mid_1_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: register complexMult_156/_zz_mid_reg is absorbed into DSP complexMult_156/mid_reg.
DSP Report: operator complexMult_156/_zz_mid_10 is absorbed into DSP complexMult_156/mid_reg.
DSP Report: operator complexMult_156/_zz_mid0 is absorbed into DSP complexMult_156/mid_reg.
DSP Report: Generating DSP complexMult_156/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_156/biD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/biD2_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/data_real_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/arD1_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/mid_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/aiD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_2_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_1_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: register complexMult_156/_zz_product_real_reg is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real_20 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real_10 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: operator complexMult_156/_zz_product_real0 is absorbed into DSP complexMult_156/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_156/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_156/aiD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/mid_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/brD2_delay_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/brD2_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/arD1_delay_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_2_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_1_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: register complexMult_156/_zz_product_imag_reg is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag_20 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag_10 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: operator complexMult_156/_zz_product_imag0 is absorbed into DSP complexMult_156/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_157/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_157/coeff_imag_delay_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/arD1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/data_real_delay_2_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_49_port0_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/coeff_real_delay_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/mid_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/_zz_mid_1_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: register complexMult_157/_zz_mid_reg is absorbed into DSP complexMult_157/mid_reg.
DSP Report: operator complexMult_157/_zz_mid_10 is absorbed into DSP complexMult_157/mid_reg.
DSP Report: operator complexMult_157/_zz_mid0 is absorbed into DSP complexMult_157/mid_reg.
DSP Report: Generating DSP complexMult_157/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_157/biD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/biD2_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/data_real_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/arD1_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/mid_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/aiD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_2_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_1_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: register complexMult_157/_zz_product_real_reg is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real_20 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real_10 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: operator complexMult_157/_zz_product_real0 is absorbed into DSP complexMult_157/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_157/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_157/aiD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/mid_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/brD2_delay_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/brD2_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/arD1_delay_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_2_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_1_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: register complexMult_157/_zz_product_imag_reg is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag_20 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag_10 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: operator complexMult_157/_zz_product_imag0 is absorbed into DSP complexMult_157/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_158/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_158/coeff_imag_delay_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/arD1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/data_real_delay_2_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_50_port0_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/coeff_real_delay_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/mid_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/_zz_mid_1_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: register complexMult_158/_zz_mid_reg is absorbed into DSP complexMult_158/mid_reg.
DSP Report: operator complexMult_158/_zz_mid_10 is absorbed into DSP complexMult_158/mid_reg.
DSP Report: operator complexMult_158/_zz_mid0 is absorbed into DSP complexMult_158/mid_reg.
DSP Report: Generating DSP complexMult_158/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_158/biD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/biD2_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/data_real_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/arD1_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/mid_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/aiD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_2_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_1_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: register complexMult_158/_zz_product_real_reg is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real_20 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real_10 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: operator complexMult_158/_zz_product_real0 is absorbed into DSP complexMult_158/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_158/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_158/aiD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/mid_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/brD2_delay_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/brD2_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/arD1_delay_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_2_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_1_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: register complexMult_158/_zz_product_imag_reg is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag_20 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag_10 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: operator complexMult_158/_zz_product_imag0 is absorbed into DSP complexMult_158/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_159/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_159/coeff_imag_delay_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/arD1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/data_real_delay_2_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_51_port0_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/coeff_real_delay_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/mid_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/_zz_mid_1_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: register complexMult_159/_zz_mid_reg is absorbed into DSP complexMult_159/mid_reg.
DSP Report: operator complexMult_159/_zz_mid_10 is absorbed into DSP complexMult_159/mid_reg.
DSP Report: operator complexMult_159/_zz_mid0 is absorbed into DSP complexMult_159/mid_reg.
DSP Report: Generating DSP complexMult_159/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_159/biD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/biD2_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/data_real_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/arD1_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/mid_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/aiD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_2_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_1_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: register complexMult_159/_zz_product_real_reg is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real_20 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real_10 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: operator complexMult_159/_zz_product_real0 is absorbed into DSP complexMult_159/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_159/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_159/aiD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/mid_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/brD2_delay_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/brD2_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/arD1_delay_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_2_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_1_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: register complexMult_159/_zz_product_imag_reg is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag_20 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag_10 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: operator complexMult_159/_zz_product_imag0 is absorbed into DSP complexMult_159/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_160/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_160/coeff_imag_delay_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/arD1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/data_real_delay_2_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_52_port0_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/coeff_real_delay_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/mid_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/_zz_mid_1_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: register complexMult_160/_zz_mid_reg is absorbed into DSP complexMult_160/mid_reg.
DSP Report: operator complexMult_160/_zz_mid_10 is absorbed into DSP complexMult_160/mid_reg.
DSP Report: operator complexMult_160/_zz_mid0 is absorbed into DSP complexMult_160/mid_reg.
DSP Report: Generating DSP complexMult_160/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_160/biD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/biD2_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/data_real_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/arD1_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/mid_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/aiD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_2_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_1_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: register complexMult_160/_zz_product_real_reg is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real_20 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real_10 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: operator complexMult_160/_zz_product_real0 is absorbed into DSP complexMult_160/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_160/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_160/aiD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/mid_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/brD2_delay_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/brD2_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/arD1_delay_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_2_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_1_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: register complexMult_160/_zz_product_imag_reg is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag_20 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag_10 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: operator complexMult_160/_zz_product_imag0 is absorbed into DSP complexMult_160/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_161/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_161/coeff_imag_delay_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/arD1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/data_real_delay_2_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_53_port0_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/coeff_real_delay_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/mid_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/_zz_mid_1_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: register complexMult_161/_zz_mid_reg is absorbed into DSP complexMult_161/mid_reg.
DSP Report: operator complexMult_161/_zz_mid_10 is absorbed into DSP complexMult_161/mid_reg.
DSP Report: operator complexMult_161/_zz_mid0 is absorbed into DSP complexMult_161/mid_reg.
DSP Report: Generating DSP complexMult_161/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_161/biD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/biD2_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/data_real_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/arD1_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/mid_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/aiD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_2_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_1_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: register complexMult_161/_zz_product_real_reg is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real_20 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real_10 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: operator complexMult_161/_zz_product_real0 is absorbed into DSP complexMult_161/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_161/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_161/aiD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/mid_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/brD2_delay_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/brD2_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/arD1_delay_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_2_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_1_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: register complexMult_161/_zz_product_imag_reg is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag_20 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag_10 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: operator complexMult_161/_zz_product_imag0 is absorbed into DSP complexMult_161/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_162/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_162/coeff_imag_delay_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/arD1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/data_real_delay_2_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_54_port0_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/coeff_real_delay_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/mid_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/_zz_mid_1_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: register complexMult_162/_zz_mid_reg is absorbed into DSP complexMult_162/mid_reg.
DSP Report: operator complexMult_162/_zz_mid_10 is absorbed into DSP complexMult_162/mid_reg.
DSP Report: operator complexMult_162/_zz_mid0 is absorbed into DSP complexMult_162/mid_reg.
DSP Report: Generating DSP complexMult_162/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_162/biD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/biD2_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/data_real_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/arD1_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/mid_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/aiD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_2_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_1_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: register complexMult_162/_zz_product_real_reg is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real_20 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real_10 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: operator complexMult_162/_zz_product_real0 is absorbed into DSP complexMult_162/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_162/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_162/aiD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/mid_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/brD2_delay_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/brD2_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/arD1_delay_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_2_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_1_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: register complexMult_162/_zz_product_imag_reg is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag_20 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag_10 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: operator complexMult_162/_zz_product_imag0 is absorbed into DSP complexMult_162/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_163/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_163/coeff_imag_delay_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/arD1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/data_real_delay_2_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_55_port0_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/coeff_real_delay_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/mid_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/_zz_mid_1_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: register complexMult_163/_zz_mid_reg is absorbed into DSP complexMult_163/mid_reg.
DSP Report: operator complexMult_163/_zz_mid_10 is absorbed into DSP complexMult_163/mid_reg.
DSP Report: operator complexMult_163/_zz_mid0 is absorbed into DSP complexMult_163/mid_reg.
DSP Report: Generating DSP complexMult_163/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_163/biD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/biD2_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/data_real_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/arD1_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/mid_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/aiD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_2_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_1_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: register complexMult_163/_zz_product_real_reg is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real_20 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real_10 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: operator complexMult_163/_zz_product_real0 is absorbed into DSP complexMult_163/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_163/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_163/aiD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/mid_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/brD2_delay_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/brD2_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/arD1_delay_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_2_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_1_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: register complexMult_163/_zz_product_imag_reg is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag_20 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag_10 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: operator complexMult_163/_zz_product_imag0 is absorbed into DSP complexMult_163/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_164/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_164/coeff_imag_delay_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/arD1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/data_real_delay_2_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_56_port0_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/coeff_real_delay_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/mid_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/_zz_mid_1_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: register complexMult_164/_zz_mid_reg is absorbed into DSP complexMult_164/mid_reg.
DSP Report: operator complexMult_164/_zz_mid_10 is absorbed into DSP complexMult_164/mid_reg.
DSP Report: operator complexMult_164/_zz_mid0 is absorbed into DSP complexMult_164/mid_reg.
DSP Report: Generating DSP complexMult_164/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_164/biD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/biD2_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/data_real_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/arD1_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/mid_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/aiD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_2_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_1_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: register complexMult_164/_zz_product_real_reg is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real_20 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real_10 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: operator complexMult_164/_zz_product_real0 is absorbed into DSP complexMult_164/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_164/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_164/aiD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/mid_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/brD2_delay_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/brD2_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/arD1_delay_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_2_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_1_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: register complexMult_164/_zz_product_imag_reg is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag_20 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag_10 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: operator complexMult_164/_zz_product_imag0 is absorbed into DSP complexMult_164/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_165/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_165/coeff_imag_delay_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/arD1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/data_real_delay_2_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_57_port0_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/coeff_real_delay_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/mid_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/_zz_mid_1_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: register complexMult_165/_zz_mid_reg is absorbed into DSP complexMult_165/mid_reg.
DSP Report: operator complexMult_165/_zz_mid_10 is absorbed into DSP complexMult_165/mid_reg.
DSP Report: operator complexMult_165/_zz_mid0 is absorbed into DSP complexMult_165/mid_reg.
DSP Report: Generating DSP complexMult_165/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_165/biD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/biD2_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/data_real_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/arD1_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/mid_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/aiD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_2_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_1_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: register complexMult_165/_zz_product_real_reg is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real_20 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real_10 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: operator complexMult_165/_zz_product_real0 is absorbed into DSP complexMult_165/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_165/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_165/aiD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/mid_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/brD2_delay_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/brD2_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/arD1_delay_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_2_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_1_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: register complexMult_165/_zz_product_imag_reg is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag_20 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag_10 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: operator complexMult_165/_zz_product_imag0 is absorbed into DSP complexMult_165/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_166/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_166/coeff_imag_delay_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/arD1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/data_real_delay_2_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_58_port0_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/coeff_real_delay_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/mid_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/_zz_mid_1_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: register complexMult_166/_zz_mid_reg is absorbed into DSP complexMult_166/mid_reg.
DSP Report: operator complexMult_166/_zz_mid_10 is absorbed into DSP complexMult_166/mid_reg.
DSP Report: operator complexMult_166/_zz_mid0 is absorbed into DSP complexMult_166/mid_reg.
DSP Report: Generating DSP complexMult_166/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_166/biD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/biD2_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/data_real_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/arD1_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/mid_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/aiD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_2_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_1_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: register complexMult_166/_zz_product_real_reg is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real_20 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real_10 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: operator complexMult_166/_zz_product_real0 is absorbed into DSP complexMult_166/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_166/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_166/aiD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/mid_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/brD2_delay_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/brD2_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/arD1_delay_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_2_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_1_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: register complexMult_166/_zz_product_imag_reg is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag_20 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag_10 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: operator complexMult_166/_zz_product_imag0 is absorbed into DSP complexMult_166/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_167/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_167/coeff_imag_delay_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/arD1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/data_real_delay_2_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_59_port0_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/coeff_real_delay_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/mid_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/_zz_mid_1_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: register complexMult_167/_zz_mid_reg is absorbed into DSP complexMult_167/mid_reg.
DSP Report: operator complexMult_167/_zz_mid_10 is absorbed into DSP complexMult_167/mid_reg.
DSP Report: operator complexMult_167/_zz_mid0 is absorbed into DSP complexMult_167/mid_reg.
DSP Report: Generating DSP complexMult_167/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_167/biD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/biD2_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/data_real_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/arD1_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/mid_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/aiD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_2_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_1_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: register complexMult_167/_zz_product_real_reg is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real_20 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real_10 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: operator complexMult_167/_zz_product_real0 is absorbed into DSP complexMult_167/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_167/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_167/aiD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/mid_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/brD2_delay_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/brD2_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/arD1_delay_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_2_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_1_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: register complexMult_167/_zz_product_imag_reg is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag_20 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag_10 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: operator complexMult_167/_zz_product_imag0 is absorbed into DSP complexMult_167/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_168/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_168/coeff_imag_delay_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/arD1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/data_real_delay_2_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_60_port0_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/coeff_real_delay_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/mid_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/_zz_mid_1_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: register complexMult_168/_zz_mid_reg is absorbed into DSP complexMult_168/mid_reg.
DSP Report: operator complexMult_168/_zz_mid_10 is absorbed into DSP complexMult_168/mid_reg.
DSP Report: operator complexMult_168/_zz_mid0 is absorbed into DSP complexMult_168/mid_reg.
DSP Report: Generating DSP complexMult_168/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_168/biD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/biD2_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/data_real_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/arD1_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/mid_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/aiD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_2_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_1_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: register complexMult_168/_zz_product_real_reg is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real_20 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real_10 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: operator complexMult_168/_zz_product_real0 is absorbed into DSP complexMult_168/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_168/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_168/aiD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/mid_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/brD2_delay_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/brD2_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/arD1_delay_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_2_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_1_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: register complexMult_168/_zz_product_imag_reg is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag_20 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag_10 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: operator complexMult_168/_zz_product_imag0 is absorbed into DSP complexMult_168/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_169/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_169/coeff_imag_delay_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/arD1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/data_real_delay_2_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_61_port0_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/coeff_real_delay_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/mid_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/_zz_mid_1_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: register complexMult_169/_zz_mid_reg is absorbed into DSP complexMult_169/mid_reg.
DSP Report: operator complexMult_169/_zz_mid_10 is absorbed into DSP complexMult_169/mid_reg.
DSP Report: operator complexMult_169/_zz_mid0 is absorbed into DSP complexMult_169/mid_reg.
DSP Report: Generating DSP complexMult_169/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_169/biD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/biD2_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/data_real_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/arD1_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/mid_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/aiD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_2_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_1_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: register complexMult_169/_zz_product_real_reg is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real_20 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real_10 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: operator complexMult_169/_zz_product_real0 is absorbed into DSP complexMult_169/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_169/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_169/aiD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/mid_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/brD2_delay_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/brD2_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/arD1_delay_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_2_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_1_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: register complexMult_169/_zz_product_imag_reg is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag_20 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag_10 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: operator complexMult_169/_zz_product_imag0 is absorbed into DSP complexMult_169/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_170/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_170/coeff_imag_delay_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/arD1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/data_real_delay_2_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_62_port0_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/coeff_real_delay_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/mid_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/_zz_mid_1_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: register complexMult_170/_zz_mid_reg is absorbed into DSP complexMult_170/mid_reg.
DSP Report: operator complexMult_170/_zz_mid_10 is absorbed into DSP complexMult_170/mid_reg.
DSP Report: operator complexMult_170/_zz_mid0 is absorbed into DSP complexMult_170/mid_reg.
DSP Report: Generating DSP complexMult_170/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_170/biD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/biD2_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/data_real_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/arD1_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/mid_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/aiD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_2_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_1_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: register complexMult_170/_zz_product_real_reg is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real_20 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real_10 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: operator complexMult_170/_zz_product_real0 is absorbed into DSP complexMult_170/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_170/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_170/aiD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/mid_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/brD2_delay_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/brD2_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/arD1_delay_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_2_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_1_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: register complexMult_170/_zz_product_imag_reg is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag_20 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag_10 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: operator complexMult_170/_zz_product_imag0 is absorbed into DSP complexMult_170/_zz_product_imag_2_reg.
DSP Report: Generating DSP complexMult_171/mid_reg, operation Mode is: ((D'+A'')*B'')'.
DSP Report: register complexMult_171/coeff_imag_delay_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/arD1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/data_real_delay_2_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register _zz_twiddleFactorROMs_63_port0_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/coeff_real_delay_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/mid_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/_zz_mid_1_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: register complexMult_171/_zz_mid_reg is absorbed into DSP complexMult_171/mid_reg.
DSP Report: operator complexMult_171/_zz_mid_10 is absorbed into DSP complexMult_171/mid_reg.
DSP Report: operator complexMult_171/_zz_mid0 is absorbed into DSP complexMult_171/mid_reg.
DSP Report: Generating DSP complexMult_171/_zz_product_real_2_reg, operation Mode is: (C'-((D'+A'')*B'')')'.
DSP Report: register complexMult_171/biD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/biD2_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/data_real_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/arD1_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/mid_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/aiD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_2_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_1_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: register complexMult_171/_zz_product_real_reg is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real_20 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real_10 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: operator complexMult_171/_zz_product_real0 is absorbed into DSP complexMult_171/_zz_product_real_2_reg.
DSP Report: Generating DSP complexMult_171/_zz_product_imag_2_reg, operation Mode is: (C'+((D'-ACIN2)*B'')')'.
DSP Report: register complexMult_171/aiD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/mid_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/brD2_delay_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/brD2_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/arD1_delay_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_2_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_1_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: register complexMult_171/_zz_product_imag_reg is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag_20 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag_10 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
DSP Report: operator complexMult_171/_zz_product_imag0 is absorbed into DSP complexMult_171/_zz_product_imag_2_reg.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_59_port0_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_49_port0_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_44_port0_reg[8] )
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_18_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_17_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_16_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_15_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_14_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_13_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_12_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_11_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_10_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_9_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_8_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_7_port0_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_7_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_6_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_5_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_4_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_3_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_2_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_1_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[0] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[1] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[5] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[13] )
INFO: [Synth 8-3333] propagating constant 1 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_0_port0_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_59_port0_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_47_port0_reg[20] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_144/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_144/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_143/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_143/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_142/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_142/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_141/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_141/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_32_port0_reg[17] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_32_port0_reg[23] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_32_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_139/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_139/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_138/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_138/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_29_port0_reg[21] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_29_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_29_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_136/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_136/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_135/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_135/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_134/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_134/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_133/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_133/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_132/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_132/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_131/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_131/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_130/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_130/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_129/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_129/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_128/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_128/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_127/coeff_imag_delay_1_reg[14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\complexMult_127/coeff_imag_delay_1_reg[15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_18_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_18_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_17_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_17_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_16_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_16_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_15_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_15_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_14_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_14_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_13_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_13_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_12_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_12_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_11_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_11_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_10_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_10_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_9_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_9_port0_reg[31] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_8_port0_reg[30] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\_zz_twiddleFactorROMs_8_port0_reg[31] )
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-3917] design S2P_s64_p512_dut has port dataOut_valid driven by constant 1
WARNING: [Synth 8-7129] Port dataIn_valid in module S2P_s64_p512_dut is either unconnected or has no load
WARNING: [Synth 8-3917] design hsIfftPost_dut has port dataOut_valid driven by constant 1
WARNING: [Synth 8-7129] Port validIn in module anon_3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_110 is either unconnected or has no load
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:30 ; elapsed = 00:01:51 . Memory (MB): peak = 6794.645 ; gain = 1519.078 ; free physical = 25780 ; free virtual = 62518
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
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Distributed RAM: Preliminary Mapping Report (see note below)
+-------------+------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+------------+-----------+----------------------+----------------+
|unamed__GBM0 | rams_3_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_4_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_5_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_6_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_1_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_2_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|implTx | rams_7_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|implTx | rams_0_reg | Implied | 16 x 288 | RAM32M16 x 21 |
+-------------+------------+-----------+----------------------+----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A2*(B:0x2d41))' | 18 | 15 | - | - | 33 | 1 | 0 | - | - | - | 1 | 0 |
|ComplexMult | (((D:0x3fb1)'+(A:0x645)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3ec5)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3d3e)'+(A:0x1294)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3871)'+(A:0x1e2b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0x3179)'+(A:0x2899)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3ec5)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_31 | ((D'+A2)*(B:0x2d41))' | 16 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_31 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 16 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|implTx | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3ec5)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3d3e)'+(A:0x1294)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3179)'+(A:0x2899)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3fb1)'+(A:0x645)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xf384)'+(A:0x3ec5)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xe1d5)'+(A:0x3871)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|unamed_31 | ((D'+A2)*(B:0x2d41))' | 16 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_31 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 16 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|implTx | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xe783)'+(A:0x3b20)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|unamed_49 | ((D'+A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_49 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|implTx | (((D:0xc4e0)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3871)'+(A:0x1e2b)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3fb1)'+(A:0x645)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xe783)'+(A:0x3b20)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xce87)'+(A:0x2899)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xc13b)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0xc2c2)'+(A:0xed6c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3536)'+(A:0x238e)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3b20)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xf384)'+(A:0x3ec5)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_49 | ((D'+A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|unamed_49 | ((D'-A2)*(B:0x2d41))' | 18 | 15 | - | 18 | 34 | 1 | 0 | - | 1 | 1 | 1 | 0 |
|implTx | (((D:0xc13b)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xc4e0)'+(A:0xe783)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D:0xdc72)'+(A:0xcaca)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3179)'+(A:0x2899)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x3ec5)'+(A:0xc7c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xe1d5)'+(A:0x3871)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xc4e0)'+(A:0x187d)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xc2c2)'+(A:0xed6c)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0xdc72)'+(A:0xcaca)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*BCIN2)')' | 18 | 16 | 32 | 18 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D:0x645)'+(A:0xc04f)')*B'')' | 16 | 18 | - | 16 | 35 | 1 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+(A:0x4000)'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | ((D'+A'')*B'')' | 16 | 18 | - | 16 | 35 | 2 | 2 | - | 1 | 1 | 1 | 1 |
|ComplexMult | (C'-((D'+A'')*B'')')' | 18 | 16 | 32 | 18 | 32 | 2 | 2 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-ACIN2)*B'')')' | 18 | 16 | 32 | 18 | 32 | 1 | 2 | 1 | 1 | 1 | 1 | 1 |
+------------+----------------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:43 ; elapsed = 00:02:05 . Memory (MB): peak = 6794.645 ; gain = 1519.078 ; free physical = 25050 ; free virtual = 61892
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Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:02:27 ; elapsed = 00:02:50 . Memory (MB): peak = 6955.910 ; gain = 1680.344 ; free physical = 22648 ; free virtual = 59511
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Distributed RAM: Final Mapping Report
+-------------+------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+------------+-----------+----------------------+----------------+
|unamed__GBM0 | rams_3_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_4_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_5_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_6_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_1_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_2_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|implTx | rams_7_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|implTx | rams_0_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_3_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_4_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_5_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_6_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_1_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|unamed__GBM0 | rams_2_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|implTx | rams_7_reg | Implied | 16 x 288 | RAM32M16 x 21 |
|implTx | rams_0_reg | Implied | 16 x 288 | RAM32M16 x 21 |
+-------------+------------+-----------+----------------------+----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `convFtn_intrlvFtn_dut`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `convFtn_intrlvFtn_dut' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GB0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GB0' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GB1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GB1' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GB2`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GB2' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GB3`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GB3' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GB4`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GB4' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GB5`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GB5' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GB6`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GB6' done
INFO: [Synth 8-5816] Retiming module `unamed_104__GB7`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_104__GB7' done
INFO: [Synth 8-5816] Retiming module `unamed_105`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_105' done
INFO: [Synth 8-5816] Retiming module `convFtn_intrlvFtn_QammodFtn_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `convFtn_intrlvFtn_QammodFtn_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB1' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB2`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB2' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB3`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB3' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB4`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB4' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB5`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB5' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB6`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB6' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB7`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB7' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB8`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB8' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB9`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB9' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB10`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB10' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB11`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_2__GB11' done
INFO: [Synth 8-5816] Retiming module `hsIfftPre_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `hsIfftPre_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `unamed__GBM1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM1' done
INFO: [Synth 8-5816] Retiming module `matintrlv_r64_c8_w36_sw64_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `matintrlv_r64_c8_w36_sw64_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `matintrlv_r8_c64_w36_sw64_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `matintrlv_r8_c64_w36_sw64_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `unamed__GBM1__1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM1__1' done
INFO: [Synth 8-5816] Retiming module `unamed_3`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3:/_zz_ret_3_real_reg[17]_bret
unamed_3:/_zz_ret_3_real_reg[17]_bret__0
unamed_3:/_zz_ret_3_real_reg[17]_bret__1
unamed_3:/_zz_ret_3_real_reg[17]_bret__10
unamed_3:/_zz_ret_3_real_reg[17]_bret__11
unamed_3:/_zz_ret_3_real_reg[17]_bret__12
unamed_3:/_zz_ret_3_real_reg[17]_bret__13
unamed_3:/_zz_ret_3_real_reg[17]_bret__14
unamed_3:/_zz_ret_3_real_reg[17]_bret__15
unamed_3:/_zz_ret_3_real_reg[17]_bret__16
unamed_3:/_zz_ret_3_real_reg[17]_bret__17
unamed_3:/_zz_ret_3_real_reg[17]_bret__18
unamed_3:/_zz_ret_3_real_reg[17]_bret__19
unamed_3:/_zz_ret_3_real_reg[17]_bret__2
unamed_3:/_zz_ret_3_real_reg[17]_bret__20
unamed_3:/_zz_ret_3_real_reg[17]_bret__21
unamed_3:/_zz_ret_3_real_reg[17]_bret__22
unamed_3:/_zz_ret_3_real_reg[17]_bret__23
unamed_3:/_zz_ret_3_real_reg[17]_bret__24
unamed_3:/_zz_ret_3_real_reg[17]_bret__25
unamed_3:/_zz_ret_3_real_reg[17]_bret__26
unamed_3:/_zz_ret_3_real_reg[17]_bret__27
unamed_3:/_zz_ret_3_real_reg[17]_bret__28
unamed_3:/_zz_ret_3_real_reg[17]_bret__29
unamed_3:/_zz_ret_3_real_reg[17]_bret__3
unamed_3:/_zz_ret_3_real_reg[17]_bret__30
unamed_3:/_zz_ret_3_real_reg[17]_bret__31
unamed_3:/_zz_ret_3_real_reg[17]_bret__32
unamed_3:/_zz_ret_3_real_reg[17]_bret__33
unamed_3:/_zz_ret_3_real_reg[17]_bret__34
unamed_3:/_zz_ret_3_real_reg[17]_bret__35
unamed_3:/_zz_ret_3_real_reg[17]_bret__36
unamed_3:/_zz_ret_3_real_reg[17]_bret__37
unamed_3:/_zz_ret_3_real_reg[17]_bret__38
unamed_3:/_zz_ret_3_real_reg[17]_bret__39
unamed_3:/_zz_ret_3_real_reg[17]_bret__4
unamed_3:/_zz_ret_3_real_reg[17]_bret__40
unamed_3:/_zz_ret_3_real_reg[17]_bret__41
unamed_3:/_zz_ret_3_real_reg[17]_bret__42
unamed_3:/_zz_ret_3_real_reg[17]_bret__43
unamed_3:/_zz_ret_3_real_reg[17]_bret__44
unamed_3:/_zz_ret_3_real_reg[17]_bret__45
unamed_3:/_zz_ret_3_real_reg[17]_bret__46
unamed_3:/_zz_ret_3_real_reg[17]_bret__47
unamed_3:/_zz_ret_3_real_reg[17]_bret__48
unamed_3:/_zz_ret_3_real_reg[17]_bret__49
unamed_3:/_zz_ret_3_real_reg[17]_bret__5
unamed_3:/_zz_ret_3_real_reg[17]_bret__50
unamed_3:/_zz_ret_3_real_reg[17]_bret__51
unamed_3:/_zz_ret_3_real_reg[17]_bret__6
unamed_3:/_zz_ret_3_real_reg[17]_bret__7
unamed_3:/_zz_ret_3_real_reg[17]_bret__8
unamed_3:/_zz_ret_3_real_reg[17]_bret__9
unamed_3:/_zz_ret_7_real_17_reg[17]_bret
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__0__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__0__0__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__1
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__10
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__10__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__11
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__11__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__12
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__12__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__13
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__13__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__14
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__14__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__15
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__15__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__16
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__17
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__18
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__19
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__1__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__2
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__20
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__21
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__22
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__23
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__24
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__25
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__26
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__27
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__28
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__29
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__2__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__3
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__30
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__31
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__32
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__33
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__34
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__3__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__4
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__4__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__5
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__5__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__6
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__6__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__7
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__7__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__8
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__8__0
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__9
unamed_3:/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3' done
INFO: [Synth 8-5816] Retiming module `unamed_3__1`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__1
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__10
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__11
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__12
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__13
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__14
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__15
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__16
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__17
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__18
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__19
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__2
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__20
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__21
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__22
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__23
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__24
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__25
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__26
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__27
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__28
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__29
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__3
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__30
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__31
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__32
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__33
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__34
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__35
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__36
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__37
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__38
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__39
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__4
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__40
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__41
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__42
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__43
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__44
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__45
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__46
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__47
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__48
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__49
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__5
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__50
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__51
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__6
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__7
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__8
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__9
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__0__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__0__0__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__1
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__10
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__10__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__11
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__11__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__12
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__12__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__13
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__13__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__14
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__14__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__15
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__15__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__16
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__17
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__18
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__19
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__1__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__2
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__20
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__21
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__22
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__23
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__24
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__25
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__26
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__27
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__28
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__29
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__2__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__3
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__30
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__31
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__32
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__33
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__34
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__3__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__4
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__4__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__5
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__5__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__6
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__6__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__7
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__7__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__8
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__8__0
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__9
core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3__1' done
INFO: [Synth 8-5816] Retiming module `unamed_3__2`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3__2:/_zz_ret_3_real_reg[17]_bret
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__0
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__1
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__10
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__11
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__12
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__13
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__14
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__15
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__16
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__17
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__18
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__19
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__2
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__20
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__21
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__22
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__23
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__24
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__25
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__26
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__27
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__28
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__29
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__3
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__30
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__31
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__32
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__33
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__34
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__35
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__36
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__37
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__38
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__39
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__4
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__40
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__41
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__42
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__43
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__44
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__45
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__46
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__47
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__48
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__49
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__5
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__50
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__51
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__6
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__7
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__8
unamed_3__2:/_zz_ret_3_real_reg[17]_bret__9
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__0__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__0__0__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__1
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__10
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__10__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__11
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__11__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__12
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__12__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__13
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__13__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__14
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__14__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__15
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__15__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__16
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__17
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__18
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__19
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__1__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__2
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__20
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__21
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__22
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__23
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__24
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__25
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__26
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__27
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__28
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__29
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__2__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__3
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__30
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__31
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__32
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__33
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__34
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__3__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__4
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__4__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__5
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__5__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__6
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__6__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__7
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__7__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__8
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__8__0
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__9
unamed_3__2:/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3__2' done
INFO: [Synth 8-5816] Retiming module `unamed_3__3`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__1
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__10
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__11
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__12
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__13
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__14
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__15
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__16
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__17
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__18
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__19
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__2
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__20
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__21
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__22
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__23
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__24
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__25
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__26
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__27
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__28
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__29
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__3
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__30
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__31
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__32
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__33
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__34
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__35
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__36
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__37
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__38
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__39
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__4
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__40
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__41
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__42
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__43
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__44
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__45
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__46
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__47
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__48
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__49
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__5
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__50
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__51
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__6
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__7
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__8
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__9
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__0__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__0__0__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__1
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__10
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__10__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__11
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__11__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__12
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__12__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__13
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__13__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__14
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__14__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__15
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__15__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__16
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__17
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__18
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__19
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__1__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__2
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__20
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__21
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__22
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__23
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__24
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__25
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__26
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__27
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__28
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__29
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__2__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__3
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__30
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__31
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__32
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__33
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__34
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__3__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__4
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__4__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__5
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__5__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__6
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__6__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__7
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__7__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__8
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__8__0
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__9
core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3__3' done
INFO: [Synth 8-5816] Retiming module `ifft_n64_factors_8_8_scales_2_2_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `ifft_n64_factors_8_8_scales_2_2_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `unamed_3__4`
Numbers of forward move = 0, and backward move = 2
Retimed registers names:
unamed_3__4:/_zz_ret_3_real_reg[17]_bret
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__0
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__1
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__10
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__11
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__12
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__13
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__14
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__15
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__16
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__17
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__18
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__19
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__2
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__20
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__21
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__22
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__23
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__24
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__25
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__26
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__27
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__28
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__29
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__3
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__30
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__31
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__32
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__33
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__34
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__35
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__36
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__37
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__38
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__39
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__4
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__40
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__41
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__42
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__43
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__44
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__45
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__46
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__47
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__48
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__49
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__5
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__50
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__51
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__6
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__7
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__8
unamed_3__4:/_zz_ret_3_real_reg[17]_bret__9
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__0__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__0__0__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__1
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__10
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__10__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__11
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__11__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__12
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__12__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__13
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__13__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__14
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__14__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__15
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__15__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__16
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__17
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__18
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__19
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__1__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__2
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__20
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__21
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__22
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__23
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__24
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__25
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__26
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__27
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__28
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__29
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__2__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__3
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__30
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__31
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__32
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__33
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__34
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__3__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__4
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__4__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__5
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__5__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__6
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__6__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__7
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__7__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__8
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__8__0
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__9
unamed_3__4:/_zz_ret_7_real_17_reg[17]_bret__9__0
INFO: [Synth 8-5816] Retiming module `unamed_3__4' done
INFO: [Synth 8-5816] Retiming module `ifft_n8_factors_8_scales_1_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `ifft_n8_factors_8_scales_1_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `ifft_n512_sw64_factors_8_8_8_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `ifft_n512_sw64_factors_8_8_8_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `implTx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `implTx' done
INFO: [Synth 8-5816] Retiming module `unamed_106_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_106_tempName' done
INFO: [Synth 8-5816] Retiming module `implTx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `implTx' done
INFO: [Synth 8-5816] Retiming module `unamed__GBM0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GBM0_tempName' done
INFO: [Synth 8-5816] Retiming module `implTx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `implTx' done
INFO: [Synth 8-5816] Retiming module `unamed_95__GC0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_95__GC0_tempName' done
INFO: [Synth 8-5816] Retiming module `implTx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `implTx' done
INFO: [Synth 8-5816] Retiming module `unamed_108__GC0_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed_108__GC0_tempName' done
INFO: [Synth 8-5816] Retiming module `implTx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `implTx' done
INFO: [Synth 8-5816] Retiming module `S2P_s64_p512_dut_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `S2P_s64_p512_dut_tempName' done
INFO: [Synth 8-5816] Retiming module `implTx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `implTx' done
INFO: [Synth 8-5816] Retiming module `hsIfftPost_dut_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `hsIfftPost_dut_tempName' done
INFO: [Synth 8-5816] Retiming module `implTx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `implTx' done
INFO: [Synth 8-5816] Retiming module `anon_4__GCB2_tempName`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon_4__GCB2_tempName' done
INFO: [Synth 8-5816] Retiming module `implTx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `implTx' done
INFO: [Common 17-14] Message 'Synth 8-5816' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:03:52 ; elapsed = 00:04:14 . Memory (MB): peak = 7040.379 ; gain = 1764.812 ; free physical = 19862 ; free virtual = 56726
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:04:28 ; elapsed = 00:04:51 . Memory (MB): peak = 7169.246 ; gain = 1893.680 ; free physical = 24192 ; free virtual = 61214
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:04:29 ; elapsed = 00:04:52 . Memory (MB): peak = 7169.246 ; gain = 1893.680 ; free physical = 24731 ; free virtual = 61753
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:05:35 ; elapsed = 00:05:59 . Memory (MB): peak = 7250.473 ; gain = 1974.906 ; free physical = 24706 ; free virtual = 61729
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:05:37 ; elapsed = 00:06:00 . Memory (MB): peak = 7250.473 ; gain = 1974.906 ; free physical = 24542 ; free virtual = 61565
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:05:42 ; elapsed = 00:06:05 . Memory (MB): peak = 7250.473 ; gain = 1974.906 ; free physical = 24133 ; free virtual = 61156
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:05:44 ; elapsed = 00:06:08 . Memory (MB): peak = 7250.473 ; gain = 1974.906 ; free physical = 23930 ; free virtual = 60952
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+------------+-----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+------------+-----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|implTx | core1/core/ifftCore/core/core0/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_113/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_114/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_115/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_116/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_117/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_118/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_119/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_184/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_185/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_186/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_187/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_188/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_189/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_190/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_191/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_120/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_120/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_121/ret_real_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_121/ret_imag_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_122/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_122/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_123/ret_real_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_123/ret_imag_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_124/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_124/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_125/ret_real_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_125/ret_imag_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_126/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_126/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_127/ret_real_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_127/ret_imag_reg[17] | 7 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_128/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_128/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_132/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_136/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_136/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_144/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_144/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_150/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_152/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_152/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_156/ret_real_reg[17] | 6 | 17 | NO | NO | YES | 17 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_156/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_160/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_160/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_162/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_166/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_168/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_168/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_176/ret_real_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_176/ret_imag_reg[17] | 8 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core0/core/unamed_178/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/core1s_0/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core1s_1/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core1s_2/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core1s_3/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core1s_4/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core1s_5/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core1s_6/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/core1s_7/core/unamed_112/_zz_ret_3_real_reg[17]_bret__44 | 4 | 18 | NO | YES | YES | 18 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_108/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_109/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_109/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_110/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_110/brD2_reg[13] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_111/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_111/brD2_reg[13] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_112/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_112/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_113/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_113/brD2_reg[10] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_114/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_114/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_115/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_115/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_116/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_117/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_118/brD2_reg[13] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_119/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_120/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_121/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_122/brD2_reg[13] | 3 | 10 | NO | NO | YES | 10 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_123/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_124/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_124/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_125/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_125/brD2_reg[13] | 3 | 10 | NO | NO | YES | 10 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_126/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_126/brD2_reg[13] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_127/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_127/brD2_reg[14] | 3 | 10 | NO | NO | YES | 10 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_128/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_128/brD2_reg[14] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_129/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_129/brD2_reg[14] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_130/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_130/brD2_reg[14] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_131/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_131/brD2_reg[14] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_132/brD2_reg[14] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_133/brD2_reg[14] | 3 | 10 | NO | NO | YES | 10 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_134/brD2_reg[14] | 3 | 11 | NO | NO | YES | 11 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_135/brD2_reg[14] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_136/brD2_reg[14] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_137/brD2_reg[14] | 3 | 10 | NO | NO | YES | 10 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_138/brD2_reg[14] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_139/brD2_reg[14] | 3 | 4 | NO | NO | YES | 4 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_140/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_140/brD2_reg[14] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_141/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_141/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_142/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_142/brD2_reg[12] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_143/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_143/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_144/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_144/brD2_reg[13] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_145/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_145/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_146/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_146/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_147/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_147/brD2_reg[13] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_148/brD2_reg[13] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_149/brD2_reg[13] | 3 | 5 | NO | NO | YES | 5 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_150/brD2_reg[13] | 3 | 5 | NO | NO | YES | 5 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_151/brD2_reg[12] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_152/brD2_reg[11] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_153/brD2_reg[12] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_154/brD2_reg[12] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_155/brD2_reg[12] | 3 | 5 | NO | NO | YES | 5 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_156/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_156/brD2_reg[12] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_157/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_157/brD2_reg[12] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_158/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_158/brD2_reg[12] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_159/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_159/brD2_reg[12] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_160/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_160/brD2_reg[12] | 3 | 7 | NO | NO | YES | 7 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_161/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_161/brD2_reg[12] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_162/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_162/brD2_reg[12] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_163/aiD2_reg[17] | 4 | 16 | NO | YES | YES | 16 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_163/brD2_reg[14] | 3 | 5 | NO | NO | YES | 5 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_164/brD2_reg[15] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_165/brD2_reg[15] | 3 | 11 | NO | NO | YES | 11 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_166/brD2_reg[15] | 3 | 11 | NO | NO | YES | 11 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_167/brD2_reg[15] | 3 | 10 | NO | NO | YES | 10 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_168/brD2_reg[15] | 3 | 4 | NO | NO | YES | 4 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_169/brD2_reg[15] | 3 | 6 | NO | NO | YES | 6 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_170/brD2_reg[15] | 3 | 9 | NO | NO | YES | 9 | 0 |
|implTx | core1/core/ifftCore/core/complexMult_171/brD2_reg[15] | 3 | 8 | NO | NO | YES | 8 | 0 |
|implTx | core0/dataIn_payload_last_delay_7_reg | 5 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/ifftCore/core/inter1/core/core/writeRefresh_reg | 7 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/ifftCore/core/inter1/core/core/readRefresh_reg | 8 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/ifftCore/core/inter2/core/core/writeRefresh_reg | 6 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/ifftCore/core/inter2/core/core/readRefresh_reg | 8 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/ifftCore/dataIn_payload_last_delay_60_reg | 33 | 1 | YES | NO | YES | 0 | 1 |
|implTx | core1/core/ifftCore/core/inter0/core/core/writeRefresh_reg | 7 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/ifftCore/core/inter0/core/core/readRefresh_reg | 8 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/ifftCore/core/core0/dataIn_payload_last_delay_16_reg | 16 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/s2p/dataIn_payload_last_delay_8_reg | 8 | 1 | YES | NO | YES | 1 | 0 |
|implTx | core1/core/post/core/lastIn_delay_5_reg | 4 | 1 | YES | NO | YES | 1 | 0 |
+------------+-----------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
Retiming Report:
+--------------------+-----+
|Retiming summary: | |
+--------------------+-----+
|Forward Retiming | 0 |
|Backward Retiming | 10 |
|New registers added | 530 |
|Registers deleted | 180 |
+--------------------+-----+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
DSP Final Report (the ' indicates corresponding REG is set)
+------------+-----------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
+------------+-----------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|ComplexMult | (((D'+A)'*B'')')' | 15 | 18 | - | 0 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 15 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 11 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 11 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 12 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 12 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 13 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 13 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 13 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 13 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 13 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 13 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 13 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 13 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 15 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 15 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 15 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 15 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 14 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 14 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (((D'+A'')'*B'')')' | 30 | 18 | - | 27 | 32 | 2 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B'')'))' | 30 | 18 | 48 | 27 | 32 | 2 | 2 | 2 | 2 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B'')')' | 0 | 18 | 48 | 27 | 32 | 1 | 2 | 2 | 2 | 1 | 1 | 1 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|ComplexMult | (((D+A)'*B'')')' | 11 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 11 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 12 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 12 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 12 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_31 | (((D'+A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|unamed_31 | (((D'-A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 14 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 12 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 12 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 11 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|unamed_31 | (((D'+A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|unamed_31 | (((D'-A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|unamed_49 | (((D'+A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|unamed_49 | (((D'-A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 11 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 11 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A')'*B)')' | 0 | 18 | 48 | 27 | 32 | 1 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 12 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 12 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|unamed_49 | (((D'+A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|unamed_49 | (((D'-A')'*B)')' | 30 | 14 | - | 27 | 32 | 1 | 0 | - | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 12 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 12 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 12 | 18 | - | 14 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 12 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 14 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 14 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 13 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 13 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 30 | 18 | - | 27 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B')'))' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B')')' | 30 | 0 | 48 | 27 | 32 | 2 | 1 | 1 | 1 | 1 | 1 | 1 |
|implTx | (((D+A)'*B'')')' | 30 | 18 | - | 11 | 32 | 0 | 2 | - | 2 | 1 | 1 | 1 |
|ComplexMult | (not(C'+((D'+A'')'*B)'))' | 30 | 18 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|ComplexMult | (C'+((D'-A'')'*B)')' | 30 | 11 | 48 | 27 | 32 | 2 | 0 | 0 | 0 | 1 | 1 | 1 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
|unamed_3 | (A'*B)' | 30 | 14 | - | - | 32 | 1 | 0 | - | - | - | 1 | 0 |
+------------+-----------------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------------+-------+
| |Cell |Count |
+------+----------------+-------+
|1 |CARRY8 | 8763|
|2 |DSP_ALU | 428|
|3 |DSP_A_B_DATA | 428|
|13 |DSP_C_DATA | 428|
|14 |DSP_MULTIPLIER | 428|
|16 |DSP_M_DATA | 428|
|17 |DSP_OUTPUT | 428|
|19 |DSP_PREADD | 428|
|20 |DSP_PREADD_DATA | 428|
|23 |LUT1 | 11919|
|24 |LUT2 | 42305|
|25 |LUT3 | 16706|
|26 |LUT4 | 1542|
|27 |LUT5 | 135|
|28 |LUT6 | 28537|
|29 |MUXF7 | 9152|
|30 |RAM32M16 | 504|
|31 |SRL16E | 2028|
|32 |SRLC32E | 1|
|33 |FDCE | 1542|
|34 |FDPE | 36|
|35 |FDRE | 164969|
|36 |FDSE | 216|
+------+----------------+-------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:05:45 ; elapsed = 00:06:09 . Memory (MB): peak = 7250.473 ; gain = 1974.906 ; free physical = 23868 ; free virtual = 60890
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 426 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:05:19 ; elapsed = 00:05:47 . Memory (MB): peak = 7254.383 ; gain = 1276.191 ; free physical = 35421 ; free virtual = 72444
Synthesis Optimization Complete : Time (s): cpu = 00:05:49 ; elapsed = 00:06:11 . Memory (MB): peak = 7254.383 ; gain = 1978.816 ; free physical = 35451 ; free virtual = 72443
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 7484.559 ; gain = 0.000 ; free physical = 33798 ; free virtual = 70791
INFO: [Netlist 29-17] Analyzing 18847 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 5 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 7877.617 ; gain = 0.000 ; free physical = 32346 ; free virtual = 69338
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 932 instances were transformed.
DSP48E2 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD, DSP_PREADD_DATA): 428 instances
RAM32M16 => RAM32M16 (RAMD32(x14), RAMS32(x2)): 504 instances
Synth Design complete, checksum: 338d908c
INFO: [Common 17-83] Releasing license: Synthesis
678 Infos, 222 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:06:57 ; elapsed = 00:07:19 . Memory (MB): peak = 7877.617 ; gain = 2709.840 ; free physical = 33095 ; free virtual = 70088
# write_checkpoint -force implTx_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/implTx/implTx_after_synth.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:01:44 ; elapsed = 00:00:42 . Memory (MB): peak = 8275.258 ; gain = 397.641 ; free physical = 32560 ; free virtual = 69655
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:56:57 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : implTx
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+----------------------------+--------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+--------+-------+------------+-----------+-------+
| CLB LUTs* | 104579 | 0 | 0 | 1182240 | 8.85 |
| LUT as Logic | 98518 | 0 | 0 | 1182240 | 8.33 |
| LUT as Memory | 6061 | 0 | 0 | 591840 | 1.02 |
| LUT as Distributed RAM | 4032 | 0 | | | |
| LUT as Shift Register | 2029 | 0 | | | |
| CLB Registers | 166763 | 0 | 0 | 2364480 | 7.05 |
| Register as Flip Flop | 166763 | 0 | 0 | 2364480 | 7.05 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 8763 | 0 | 0 | 147780 | 5.93 |
| F7 Muxes | 9152 | 0 | 0 | 591120 | 1.55 |
| F8 Muxes | 0 | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+----------------------------+--------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+--------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+--------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 36 | Yes | - | Set |
| 1542 | Yes | - | Reset |
| 216 | Yes | Set | - |
| 164969 | Yes | Reset | - |
+--------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------+------+-------+------------+-----------+-------+
| DSPs | 428 | 0 | 0 | 6840 | 6.26 |
| DSP48E2 only | 428 | | | | |
+----------------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+--------+---------------------+
| Ref Name | Used | Functional Category |
+----------+--------+---------------------+
| FDRE | 164969 | Register |
| LUT2 | 42305 | CLB |
| LUT6 | 28537 | CLB |
| LUT3 | 16706 | CLB |
| LUT1 | 11919 | CLB |
| MUXF7 | 9152 | CLB |
| CARRY8 | 8763 | CLB |
| RAMD32 | 7056 | CLB |
| SRL16E | 2028 | CLB |
| LUT4 | 1542 | CLB |
| FDCE | 1542 | Register |
| RAMS32 | 1008 | CLB |
| DSP48E2 | 428 | Arithmetic |
| FDSE | 216 | Register |
| LUT5 | 135 | CLB |
| FDPE | 36 | Register |
| SRLC32E | 1 | CLB |
+----------+--------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 20:57:32 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : implTx
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -0.476ns (required time - arrival time)
Source: core0/core/core0/core/core1/core/localCounter_value_reg[2]/C
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: core0/core/core0/core/core1/core/ret_reg[0]/D
(rising edge-triggered cell FDRE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 1.708ns (logic 0.531ns (31.089%) route 1.177ns (68.911%))
Logic Levels: 6 (LUT3=2 LUT6=4)
Clock Path Skew: -0.008ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.028ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=179423, unset) 0.028 0.028 core0/core/core0/core/core1/core/clk
FDCE r core0/core/core0/core/core1/core/localCounter_value_reg[2]/C
------------------------------------------------------------------- -------------------
FDCE (Prop_FDCE_C_Q) 0.077 0.105 r core0/core/core0/core/core1/core/localCounter_value_reg[2]/Q
net (fo=6, unplaced) 0.123 0.228 core0/core/core0/core/core1/core/localCounter_value[2]
LUT3 (Prop_LUT3_I0_O) 0.090 0.318 r core0/core/core0/core/core1/core/localCounter_value[6]_i_2/O
net (fo=3, unplaced) 0.203 0.521 core0/core/core0/core/core1/core/localCounter_value[6]_i_2_n_0
LUT6 (Prop_LUT6_I2_O) 0.038 0.559 r core0/core/core0/core/core1/core/localCounter_value[6]_i_1/O
net (fo=255, unplaced) 0.304 0.863 core0/core/core0/core/core0/core/p_0_in[6]
LUT6 (Prop_LUT6_I4_O) 0.038 0.901 r core0/core/core0/core/core0/core/ret[246]_i_28/O
net (fo=4, unplaced) 0.133 1.034 core0/core/core0/core/core0/core/_zz_ret_5[134]
LUT6 (Prop_LUT6_I0_O) 0.150 1.184 r core0/core/core0/core/core0/core/ret[222]_i_8/O
net (fo=4, unplaced) 0.169 1.353 core0/core/core0/core/core0/core/_zz_ret_3[158]
LUT6 (Prop_LUT6_I0_O) 0.100 1.453 r core0/core/core0/core/core0/core/ret[128]_i_2/O
net (fo=2, unplaced) 0.197 1.650 core0/core/core0/core/core0/core/_zz_ret_1[0]
LUT3 (Prop_LUT3_I2_O) 0.038 1.688 r core0/core/core0/core/core0/core/ret[0]_i_1/O
net (fo=1, unplaced) 0.048 1.736 core0/core/core0/core/core1/core/ret_reg[253]_0[0]
FDRE r core0/core/core0/core/core1/core/ret_reg[0]/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=179423, unset) 0.020 1.270 core0/core/core0/core/core1/core/clk
FDRE r core0/core/core0/core/core1/core/ret_reg[0]/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDRE (Setup_FDRE_C_D) 0.025 1.260 core0/core/core0/core/core1/core/ret_reg[0]
-------------------------------------------------------------------
required time 1.260
arrival time -1.736
-------------------------------------------------------------------
slack -0.476
report_timing: Time (s): cpu = 00:01:20 ; elapsed = 00:00:35 . Memory (MB): peak = 8785.457 ; gain = 510.199 ; free physical = 31439 ; free virtual = 68533
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 20:57:33 2022...
-
[INFO ]
-
: binary adder cost = 14591
-
[INFO ]
-
: ternary adder cost = 26316
-
[INFO ]
-
: reg cost = 198778
-
[INFO ]
-
:
LUT: 104579
FF: 166763
DSP: 428
BRAM: 0
CARRY8: 8763
-
[INFO ]
-
:
fmax = 579.3742757821552 MHz
-
10 m 30 s
passedshould synth for rx
-
[Runtime] SpinalHDL v1.7.3 git head : ed8004c489ee8a38c2cab309d0447b543fe9d5b8
[Runtime] JVM max memory : 27305.0MiB
[Runtime] Current date : 2022.10.25 20:57:37
[Progress] at 3501.945 : Elaborate components
[Progress] at 3503.269 : Checks and transforms
[Progress] at 3511.624 : Generate Verilog
[Warning] toplevel/core1/core/cores_0/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_1/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_2/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_3/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_4/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_5/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_6/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_7/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_8/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_9/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_10/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_11/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_12/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_13/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_14/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_15/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_16/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_17/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_18/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_19/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_20/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_21/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_22/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_23/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_24/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_25/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_26/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_27/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_28/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_29/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_30/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_31/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_32/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_33/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_34/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_35/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_36/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_37/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_38/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_39/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_40/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_41/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_42/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_43/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_44/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_45/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_46/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_47/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_48/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_49/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_50/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_51/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_52/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_53/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_54/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_55/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_56/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_57/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_58/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_59/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_60/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_61/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_62/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_63/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_64/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_65/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_66/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_67/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_68/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_69/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_70/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_71/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_72/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_73/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_74/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_75/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_76/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_77/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_78/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_79/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_80/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_81/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_82/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_83/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_84/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_85/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_86/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_87/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_88/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_89/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_90/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_91/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_92/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_93/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_94/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_95/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_96/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_97/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_98/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_99/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_100/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_101/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_102/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_103/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_104/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_105/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_106/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_107/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_108/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_109/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_110/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_111/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_112/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_113/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_114/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_115/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_116/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_117/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_118/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_119/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_120/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_121/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_122/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_123/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_124/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_125/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] toplevel/core1/core/cores_126/forward/updatingROM : Mem[4*256 bits].readAsync can only be write first into Verilog
[Warning] 65804 signals were pruned. You can call printPruned on the backend report to get more informations.
[Done] at 3515.544
vivado -stack 2000 -nojournal -log doit.log -mode batch -source doit.tcl
****** Vivado v2022.1 (64-bit)
**** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
**** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
source doit.tcl
# read_verilog unamed.v
# read_verilog unamed_1.v
# read_verilog anon.v
# read_verilog anon_1.v
# read_verilog unamed_2.v
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# read_verilog unamed_380.v
# read_verilog QamdemodFtn_dut.v
# read_verilog deintrlvFtn_dut.v
# read_verilog unamed_383.v
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# read_verilog unamed_463.v
# read_verilog unamed_464.v
# read_verilog unamed_465.v
# read_verilog unamed_466.v
# read_verilog unamed_467.v
# read_verilog unamed_468.v
# read_verilog unamed_469.v
# read_verilog unamed_470.v
# read_verilog unamed_471.v
# read_verilog unamed_472.v
# read_verilog unamed_473.v
# read_verilog unamed_474.v
# read_verilog unamed_475.v
# read_verilog unamed_476.v
# read_verilog unamed_477.v
# read_verilog unamed_478.v
# read_verilog unamed_479.v
# read_verilog unamed_480.v
# read_verilog unamed_481.v
# read_verilog unamed_482.v
# read_verilog unamed_483.v
# read_verilog unamed_484.v
# read_verilog unamed_485.v
# read_verilog unamed_486.v
# read_verilog unamed_487.v
# read_verilog unamed_488.v
# read_verilog unamed_489.v
# read_verilog unamed_490.v
# read_verilog unamed_491.v
# read_verilog unamed_492.v
# read_verilog unamed_493.v
# read_verilog unamed_494.v
# read_verilog unamed_495.v
# read_verilog unamed_496.v
# read_verilog unamed_497.v
# read_verilog unamed_498.v
# read_verilog unamed_499.v
# read_verilog unamed_500.v
# read_verilog unamed_501.v
# read_verilog unamed_502.v
# read_verilog unamed_503.v
# read_verilog unamed_504.v
# read_verilog unamed_505.v
# read_verilog unamed_506.v
# read_verilog unamed_507.v
# read_verilog unamed_508.v
# read_verilog unamed_509.v
# read_verilog unamed_510.v
# read_verilog anon_2.v
# read_verilog QamdemodFtn_deintrlvFtn_dut.v
# read_verilog viterbiFtn_dut.v
# read_verilog synthRx.v
# read_xdc doit.xdc
# synth_design -part xcvu9p-flga2104-2-i -top synthRx -mode out_of_context -retiming
Command: synth_design -part xcvu9p-flga2104-2-i -top synthRx -mode out_of_context -retiming
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2-i
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 12736
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5767.348 ; gain = 490.793 ; free physical = 34488 ; free virtual = 71162
---------------------------------------------------------------------------------
WARNING: [Synth 8-6014] Unused sequential element lastForBack_reg was removed. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_4.v:201]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_383 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_383.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_383 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_383.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_383 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_383.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_384 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_384.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_384 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_384.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_384 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_384.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_385 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_385.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_385 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_385.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_385 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_385.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_386 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_386.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_386 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_386.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_386 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_386.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_387 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_387.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_387 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_387.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_387 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_387.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_388 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_388.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_388 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_388.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_388 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_388.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_389 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_389.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_389 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_389.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_389 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_389.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_390 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_390.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_390 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_390.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_390 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_390.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_391 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_391.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_391 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_391.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_391 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_391.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_392 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_392.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_392 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_392.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_392 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_392.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_393 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_393.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_393 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_393.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_393 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_393.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_394 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_394.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_394 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_394.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_394 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_394.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_395 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_395.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_395 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_395.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_395 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_395.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_396 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_396.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_396 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_396.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_396 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_396.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_397 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_397.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_397 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_397.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_397 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_397.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_398 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_398.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_398 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_398.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_398 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_398.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_399 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_399.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_399 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_399.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_399 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_399.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_400 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_400.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_400 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_400.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_400 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_400.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_401 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_401.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_401 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_401.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_401 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_401.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_402 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_402.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_402 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_402.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_402 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_402.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_403 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_403.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_403 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_403.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_403 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_403.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_404 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_404.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_404 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_404.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_404 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_404.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_405 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_405.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_405 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_405.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_405 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_405.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_406 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_406.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_406 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_406.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_406 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_406.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_407 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_407.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_407 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_407.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_407 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_407.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_408 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_408.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_408 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_408.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_408 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_408.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_409 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_409.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_409 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_409.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_409 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_409.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_410 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_410.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_410 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_410.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_410 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_410.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_411 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_411.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_411 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_411.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_411 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_411.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_412 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_412.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_412 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_412.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_412 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_412.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_413 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_413.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_413 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_413.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_413 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_413.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_414 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_414.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_414 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_414.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_414 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_414.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_415 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_415.v:81]
WARNING: [Synth 8-3848] Net backward_validIn in module/entity unamed_415 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_415.v:80]
WARNING: [Synth 8-3848] Net forward_validIn in module/entity unamed_415 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_415.v:15]
WARNING: [Synth 8-3848] Net reverse_validIn in module/entity unamed_416 does not have driver. [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_416.v:81]
INFO: [Common 17-14] Message 'Synth 8-3848' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Synth 8-7129] Port validIn in module unamed_4 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_3 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_380 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_509 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_377 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_508 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_374 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_507 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_371 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_506 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_368 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_505 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_365 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_504 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_362 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_503 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_359 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_502 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_356 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_501 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_353 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_500 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_350 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_499 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_347 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_498 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_344 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_497 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_341 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_496 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_338 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_495 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_335 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_494 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_332 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_493 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_329 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_492 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_326 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_491 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_323 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_490 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_320 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_489 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_317 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_488 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_314 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_487 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_311 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_486 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_308 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_485 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_305 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_484 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_302 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_483 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_299 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_482 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_296 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_481 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_293 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_480 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_290 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_479 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_287 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_478 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_284 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_477 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_281 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_476 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_278 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_475 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_275 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_474 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_272 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_473 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_269 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_472 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_266 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_471 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_263 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_470 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_260 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_469 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_257 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_468 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_254 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_467 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_251 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_466 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_248 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_465 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_245 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_464 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_242 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_463 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_239 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_462 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_236 is either unconnected or has no load
WARNING: [Synth 8-7129] Port validIn in module unamed_461 is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:41 ; elapsed = 00:01:07 . Memory (MB): peak = 6933.535 ; gain = 1656.980 ; free physical = 24845 ; free virtual = 61542
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:44 ; elapsed = 00:01:10 . Memory (MB): peak = 6933.535 ; gain = 1656.980 ; free physical = 24811 ; free virtual = 61508
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:44 ; elapsed = 00:01:10 . Memory (MB): peak = 6933.535 ; gain = 1656.980 ; free physical = 24811 ; free virtual = 61508
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 6933.535 ; gain = 0.000 ; free physical = 24462 ; free virtual = 61159
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/doit.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 7183.660 ; gain = 0.000 ; free physical = 24460 ; free virtual = 61158
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 7183.660 ; gain = 0.000 ; free physical = 24455 ; free virtual = 61153
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:01:20 ; elapsed = 00:01:42 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 24992 ; free virtual = 61690
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xcvu9p-flga2104-2-i
INFO: [Synth 8-6742] Reading net delay rules and data
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:01:20 ; elapsed = 00:01:42 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 24992 ; free virtual = 61690
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:01:20 ; elapsed = 00:01:42 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 24992 ; free virtual = 61690
---------------------------------------------------------------------------------
INFO: [Synth 8-6904] The RAM "unamed_4:/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:02:17 ; elapsed = 00:02:40 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 24710 ; free virtual = 61432
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
3 Input 18 Bit Adders := 508
2 Input 7 Bit Adders := 509
2 Input 6 Bit Adders := 254
2 Input 4 Bit Adders := 16256
2 Input 2 Bit Adders := 1
+---Registers :
256 Bit Registers := 127
18 Bit Registers := 508
7 Bit Registers := 255
6 Bit Registers := 381
4 Bit Registers := 8382
1 Bit Registers := 18684
+---RAMs :
32K Bit (128 X 256 bit) RAMs := 127
128 Bit (128 X 1 bit) RAMs := 127
+---Muxes :
2 Input 254 Bit Muxes := 7
2 Input 18 Bit Muxes := 508
2 Input 8 Bit Muxes := 1
2 Input 7 Bit Muxes := 509
2 Input 6 Bit Muxes := 508
64 Input 5 Bit Muxes := 254
2 Input 4 Bit Muxes := 16256
32 Input 4 Bit Muxes := 254
2 Input 2 Bit Muxes := 128
4 Input 1 Bit Muxes := 254
2 Input 1 Bit Muxes := 254
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 6840 (col length:120)
BRAMs: 4320 (col length: RAMB18 360 RAMB36 180)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_1_reg' into 'cores_51/lastIn_delay_1_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:488]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_2_reg' into 'cores_51/lastIn_delay_2_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:489]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_3_reg' into 'cores_51/lastIn_delay_3_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:490]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_4_reg' into 'cores_51/lastIn_delay_4_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:491]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_5_reg' into 'cores_51/lastIn_delay_5_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:492]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_6_reg' into 'cores_51/lastIn_delay_6_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:493]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_7_reg' into 'cores_51/lastIn_delay_7_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:494]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_8_reg' into 'cores_51/lastIn_delay_8_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:495]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_9_reg' into 'cores_51/lastIn_delay_9_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:496]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_10_reg' into 'cores_51/lastIn_delay_10_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:497]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_11_reg' into 'cores_51/lastIn_delay_11_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:498]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_12_reg' into 'cores_51/lastIn_delay_12_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:499]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_13_reg' into 'cores_51/lastIn_delay_13_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:500]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_14_reg' into 'cores_51/lastIn_delay_14_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:501]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_15_reg' into 'cores_51/lastIn_delay_15_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:502]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_16_reg' into 'cores_51/lastIn_delay_16_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:503]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_17_reg' into 'cores_51/lastIn_delay_17_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:504]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_18_reg' into 'cores_51/lastIn_delay_18_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:505]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_19_reg' into 'cores_51/lastIn_delay_19_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:506]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_20_reg' into 'cores_51/lastIn_delay_20_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:507]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_21_reg' into 'cores_51/lastIn_delay_21_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:508]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_22_reg' into 'cores_51/lastIn_delay_22_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:509]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_23_reg' into 'cores_51/lastIn_delay_23_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:510]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_24_reg' into 'cores_51/lastIn_delay_24_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:511]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_25_reg' into 'cores_51/lastIn_delay_25_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:512]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_26_reg' into 'cores_51/lastIn_delay_26_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:513]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_27_reg' into 'cores_51/lastIn_delay_27_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:514]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_28_reg' into 'cores_51/lastIn_delay_28_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:515]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_29_reg' into 'cores_51/lastIn_delay_29_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:516]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_30_reg' into 'cores_51/lastIn_delay_30_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:517]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_31_reg' into 'cores_51/lastIn_delay_31_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:518]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_32_reg' into 'cores_51/lastIn_delay_32_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:519]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_33_reg' into 'cores_51/lastIn_delay_33_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:520]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_34_reg' into 'cores_51/lastIn_delay_34_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:521]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_35_reg' into 'cores_51/lastIn_delay_35_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:522]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_36_reg' into 'cores_51/lastIn_delay_36_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:523]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_37_reg' into 'cores_51/lastIn_delay_37_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:524]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_38_reg' into 'cores_51/lastIn_delay_38_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:525]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_39_reg' into 'cores_51/lastIn_delay_39_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:526]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_40_reg' into 'cores_51/lastIn_delay_40_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:527]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_41_reg' into 'cores_51/lastIn_delay_41_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:528]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_42_reg' into 'cores_51/lastIn_delay_42_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:529]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_43_reg' into 'cores_51/lastIn_delay_43_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:530]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_44_reg' into 'cores_51/lastIn_delay_44_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:531]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_45_reg' into 'cores_51/lastIn_delay_45_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:532]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_46_reg' into 'cores_51/lastIn_delay_46_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:533]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_47_reg' into 'cores_51/lastIn_delay_47_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:534]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_48_reg' into 'cores_51/lastIn_delay_48_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:535]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_49_reg' into 'cores_51/lastIn_delay_49_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:536]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_50_reg' into 'cores_51/lastIn_delay_50_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:537]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_51_reg' into 'cores_51/lastIn_delay_51_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:538]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_52_reg' into 'cores_51/lastIn_delay_52_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:539]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_53_reg' into 'cores_51/lastIn_delay_53_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:540]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_54_reg' into 'cores_51/lastIn_delay_54_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:541]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_55_reg' into 'cores_51/lastIn_delay_55_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:542]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_56_reg' into 'cores_51/lastIn_delay_56_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:543]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_57_reg' into 'cores_51/lastIn_delay_57_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:544]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_58_reg' into 'cores_51/lastIn_delay_58_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:545]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_59_reg' into 'cores_51/lastIn_delay_59_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:546]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_60_reg' into 'cores_51/lastIn_delay_60_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:547]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_61_reg' into 'cores_51/lastIn_delay_61_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:548]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_62_reg' into 'cores_51/lastIn_delay_62_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:549]
INFO: [Synth 8-4471] merging register 'cores_61/lastIn_delay_63_reg' into 'cores_51/lastIn_delay_63_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:550]
INFO: [Synth 8-4471] merging register 'cores_61/lastForRead_reg' into 'cores_51/lastForRead_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:551]
INFO: [Synth 8-4471] merging register 'cores_61/lastForBack_reg' into 'cores_51/lastForBack_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_444.v:389]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_1_reg' into 'cores_51/lastIn_delay_1_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:488]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_2_reg' into 'cores_51/lastIn_delay_2_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:489]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_3_reg' into 'cores_51/lastIn_delay_3_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:490]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_4_reg' into 'cores_51/lastIn_delay_4_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:491]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_5_reg' into 'cores_51/lastIn_delay_5_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:492]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_6_reg' into 'cores_51/lastIn_delay_6_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:493]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_7_reg' into 'cores_51/lastIn_delay_7_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:494]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_8_reg' into 'cores_51/lastIn_delay_8_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:495]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_9_reg' into 'cores_51/lastIn_delay_9_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:496]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_10_reg' into 'cores_51/lastIn_delay_10_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:497]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_11_reg' into 'cores_51/lastIn_delay_11_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:498]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_12_reg' into 'cores_51/lastIn_delay_12_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:499]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_13_reg' into 'cores_51/lastIn_delay_13_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:500]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_14_reg' into 'cores_51/lastIn_delay_14_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:501]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_15_reg' into 'cores_51/lastIn_delay_15_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:502]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_16_reg' into 'cores_51/lastIn_delay_16_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:503]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_17_reg' into 'cores_51/lastIn_delay_17_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:504]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_18_reg' into 'cores_51/lastIn_delay_18_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:505]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_19_reg' into 'cores_51/lastIn_delay_19_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:506]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_20_reg' into 'cores_51/lastIn_delay_20_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:507]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_21_reg' into 'cores_51/lastIn_delay_21_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:508]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_22_reg' into 'cores_51/lastIn_delay_22_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:509]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_23_reg' into 'cores_51/lastIn_delay_23_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:510]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_24_reg' into 'cores_51/lastIn_delay_24_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:511]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_25_reg' into 'cores_51/lastIn_delay_25_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:512]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_26_reg' into 'cores_51/lastIn_delay_26_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:513]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_27_reg' into 'cores_51/lastIn_delay_27_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:514]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_28_reg' into 'cores_51/lastIn_delay_28_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:515]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_29_reg' into 'cores_51/lastIn_delay_29_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:516]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_30_reg' into 'cores_51/lastIn_delay_30_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:517]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_31_reg' into 'cores_51/lastIn_delay_31_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:518]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_32_reg' into 'cores_51/lastIn_delay_32_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:519]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_33_reg' into 'cores_51/lastIn_delay_33_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:520]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_34_reg' into 'cores_51/lastIn_delay_34_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:521]
INFO: [Synth 8-4471] merging register 'cores_60/lastIn_delay_35_reg' into 'cores_51/lastIn_delay_35_reg' [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/unamed_443.v:522]
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_51/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_61/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_60/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_59/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_58/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_57/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_56/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_52/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_53/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_54/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_55/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_51/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_51/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_61/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_61/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_60/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_60/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_59/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_59/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_58/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_58/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_57/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_57/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_56/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_56/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_52/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_52/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_53/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_53/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_54/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_54/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB0/cores_55/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB0/cores_55/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "anon_2__GB1/cores_47/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB1/cores_50/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB1/cores_62/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB1/cores_49/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB1/cores_47/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB1/cores_47/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB1/cores_50/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB1/cores_50/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB1/cores_62/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB1/cores_62/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB1/cores_49/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB1/cores_49/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "anon_2__GB2/cores_44/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB2/cores_45/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB2/cores_46/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB2/cores_63/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB2/cores_44/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB2/cores_44/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB2/cores_45/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB2/cores_45/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB2/cores_46/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB2/cores_46/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB2/cores_63/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB2/cores_63/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_40/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_41/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_42/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_43/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_125/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB3/cores_40/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_40/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB3/cores_41/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_41/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB3/cores_42/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_42/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB3/cores_43/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_43/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB3/cores_125/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB3/cores_125/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_39/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_38/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_37/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_36/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_35/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_34/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_126/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB4/cores_39/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_39/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB4/cores_38/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_38/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB4/cores_37/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_37/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB4/cores_36/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_36/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB4/cores_35/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_35/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB4/cores_34/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_34/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB4/cores_126/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB4/cores_126/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_48/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_33/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_32/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_31/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_30/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_29/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_28/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_27/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_25/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_48/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_48/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_33/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_33/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_32/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_32/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_31/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_31/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_30/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_30/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_29/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_29/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_28/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_28/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_27/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_27/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB5/cores_25/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB5/cores_25/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_26/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_24/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_23/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_22/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_21/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_20/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_19/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_18/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_17/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_16/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_15/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB6/cores_26/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_26/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB6/cores_24/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_24/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB6/cores_23/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_23/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB6/cores_22/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_22/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB6/cores_21/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_21/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB6/cores_20/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_20/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB6/cores_19/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_19/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
RAM ("anon_2__GB6/cores_18/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-6904] The RAM "anon_2__GB6/cores_18/reverse/stack_reg" of size (depth=128 x width=1) is automatically implemented using LUTRAM. BRAM implementation would be inefficient
INFO: [Common 17-14] Message 'Synth 8-6904' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
RAM ("anon_2__GB6/cores_17/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB6/cores_16/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB6/cores_15/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("anon_2__GB7/cores_14/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB7/cores_13/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB7/cores_12/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB7/cores_11/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB7/cores_10/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB7/cores_9/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB7/cores_8/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB7/cores_7/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB7/cores_6/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("anon_2__GB8/cores_2/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB8/cores_3/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB8/cores_5/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("anon_2__GB9/cores_0/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB9/cores_1/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB9/cores_4/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
RAM ("anon_2__GB10/cores_123/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_121/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_120/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_119/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_118/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_117/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_116/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_115/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_113/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_112/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB10/cores_110/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("anon_2__GB11/cores_108/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB11/cores_109/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB11/cores_114/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("anon_2__GB12/cores_105/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB12/cores_106/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB12/cores_107/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB12/cores_111/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("anon_2__GB13/cores_100/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB13/cores_101/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB13/cores_102/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB13/cores_103/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB13/cores_122/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
RAM ("anon_2__GB14/cores_94/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB14/cores_95/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB14/cores_96/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB14/cores_97/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB14/cores_98/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB14/cores_99/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Synth 8-7031] Trying to map ROM "p_0_out" into Block RAM due to explicit "ram_style" or "rom_style" specification
INFO: [Common 17-14] Message 'Synth 8-7031' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5586] ROM size for "p_0_out" is below threshold of ROM address width. However it will be mapped to Block Ram due to explicit rom_style/ram_style attribute
INFO: [Common 17-14] Message 'Synth 8-5586' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
RAM ("anon_2__GB15/cores_86/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB15/cores_87/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB15/cores_88/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB15/cores_89/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB15/cores_90/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB15/cores_91/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB15/cores_92/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB15/cores_93/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_77/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_78/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_79/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_80/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_81/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_82/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_83/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_84/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_85/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB16/cores_104/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Common 17-14] Message 'Synth 8-4471' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
RAM ("anon_2__GB17/cores_66/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_67/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_68/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_64/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_70/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_71/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_72/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_73/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_74/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_75/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB17/cores_76/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB18/cores_124/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB18/cores_65/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
RAM ("anon_2__GB18/cores_69/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:04:45 ; elapsed = 00:05:58 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 24135 ; free virtual = 61066
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------+-------------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------+-------------------+---------------+----------------+
|unamed_2 | updatingROM | 4x6 | LUT |
|unamed_3 | candidateStates_1 | 64x6 | LUT |
|unamed_3 | candidateStates_0 | 64x6 | LUT |
|unamed_5 | updatingROM | 4x6 | LUT |
|unamed_8 | updatingROM | 4x6 | LUT |
|unamed_11 | updatingROM | 4x6 | LUT |
|unamed_14 | updatingROM | 4x6 | LUT |
|unamed_17 | updatingROM | 4x6 | LUT |
|unamed_20 | updatingROM | 4x6 | LUT |
|unamed_23 | updatingROM | 4x6 | LUT |
|unamed_26 | updatingROM | 4x6 | LUT |
|unamed_29 | updatingROM | 4x6 | LUT |
|unamed_32 | updatingROM | 4x6 | LUT |
|unamed_35 | updatingROM | 4x6 | LUT |
|unamed_38 | updatingROM | 4x6 | LUT |
|unamed_41 | updatingROM | 4x6 | LUT |
|unamed_44 | updatingROM | 4x6 | LUT |
|unamed_47 | updatingROM | 4x6 | LUT |
|unamed_50 | updatingROM | 4x6 | LUT |
|unamed_53 | updatingROM | 4x6 | LUT |
|unamed_56 | updatingROM | 4x6 | LUT |
|unamed_59 | updatingROM | 4x6 | LUT |
|unamed_62 | updatingROM | 4x6 | LUT |
|unamed_65 | updatingROM | 4x6 | LUT |
|unamed_68 | updatingROM | 4x6 | LUT |
|unamed_71 | updatingROM | 4x6 | LUT |
|unamed_74 | updatingROM | 4x6 | LUT |
|unamed_77 | updatingROM | 4x6 | LUT |
|unamed_80 | updatingROM | 4x6 | LUT |
|unamed_83 | updatingROM | 4x6 | LUT |
|unamed_86 | updatingROM | 4x6 | LUT |
|unamed_89 | updatingROM | 4x6 | LUT |
|unamed_92 | updatingROM | 4x6 | LUT |
|unamed_95 | updatingROM | 4x6 | LUT |
|unamed_98 | updatingROM | 4x6 | LUT |
|unamed_101 | updatingROM | 4x6 | LUT |
|unamed_104 | updatingROM | 4x6 | LUT |
|unamed_107 | updatingROM | 4x6 | LUT |
|unamed_110 | updatingROM | 4x6 | LUT |
|unamed_113 | updatingROM | 4x6 | LUT |
|unamed_116 | updatingROM | 4x6 | LUT |
|unamed_119 | updatingROM | 4x6 | LUT |
|unamed_122 | updatingROM | 4x6 | LUT |
|unamed_125 | updatingROM | 4x6 | LUT |
|unamed_128 | updatingROM | 4x6 | LUT |
|unamed_131 | updatingROM | 4x6 | LUT |
|unamed_134 | updatingROM | 4x6 | LUT |
|unamed_137 | updatingROM | 4x6 | LUT |
|unamed_140 | updatingROM | 4x6 | LUT |
|unamed_143 | updatingROM | 4x6 | LUT |
|unamed_146 | updatingROM | 4x6 | LUT |
|unamed_149 | updatingROM | 4x6 | LUT |
|unamed_152 | updatingROM | 4x6 | LUT |
|unamed_155 | updatingROM | 4x6 | LUT |
|unamed_158 | updatingROM | 4x6 | LUT |
|unamed_161 | updatingROM | 4x6 | LUT |
|unamed_164 | updatingROM | 4x6 | LUT |
|unamed_167 | updatingROM | 4x6 | LUT |
|unamed_170 | updatingROM | 4x6 | LUT |
|unamed_173 | updatingROM | 4x6 | LUT |
|unamed_176 | updatingROM | 4x6 | LUT |
|unamed_179 | updatingROM | 4x6 | LUT |
|unamed_182 | updatingROM | 4x6 | LUT |
|unamed_185 | updatingROM | 4x6 | LUT |
|unamed_188 | updatingROM | 4x6 | LUT |
|unamed_191 | updatingROM | 4x6 | LUT |
|unamed_194 | updatingROM | 4x6 | LUT |
|unamed_197 | updatingROM | 4x6 | LUT |
|unamed_200 | updatingROM | 4x6 | LUT |
|unamed_203 | updatingROM | 4x6 | LUT |
|unamed_206 | updatingROM | 4x6 | LUT |
|unamed_209 | updatingROM | 4x6 | LUT |
|unamed_212 | updatingROM | 4x6 | LUT |
|unamed_215 | updatingROM | 4x6 | LUT |
|unamed_218 | updatingROM | 4x6 | LUT |
|unamed_221 | updatingROM | 4x6 | LUT |
|unamed_224 | updatingROM | 4x6 | LUT |
|unamed_227 | updatingROM | 4x6 | LUT |
|unamed_230 | updatingROM | 4x6 | LUT |
|unamed_233 | updatingROM | 4x6 | LUT |
|unamed_236 | updatingROM | 4x6 | LUT |
|unamed_239 | updatingROM | 4x6 | LUT |
|unamed_242 | updatingROM | 4x6 | LUT |
|unamed_245 | updatingROM | 4x6 | LUT |
|unamed_248 | updatingROM | 4x6 | LUT |
|unamed_251 | updatingROM | 4x6 | LUT |
|unamed_254 | updatingROM | 4x6 | LUT |
|unamed_257 | updatingROM | 4x6 | LUT |
|unamed_260 | updatingROM | 4x6 | LUT |
|unamed_263 | updatingROM | 4x6 | LUT |
|unamed_266 | updatingROM | 4x6 | LUT |
|unamed_269 | updatingROM | 4x6 | LUT |
|unamed_272 | updatingROM | 4x6 | LUT |
|unamed_275 | updatingROM | 4x6 | LUT |
|unamed_278 | updatingROM | 4x6 | LUT |
|unamed_281 | updatingROM | 4x6 | LUT |
|unamed_284 | updatingROM | 4x6 | LUT |
|unamed_287 | updatingROM | 4x6 | LUT |
|unamed_290 | updatingROM | 4x6 | LUT |
|unamed_293 | updatingROM | 4x6 | LUT |
|unamed_296 | updatingROM | 4x6 | LUT |
|unamed_299 | updatingROM | 4x6 | LUT |
|unamed_302 | updatingROM | 4x6 | LUT |
|unamed_305 | updatingROM | 4x6 | LUT |
|unamed_308 | updatingROM | 4x6 | LUT |
|unamed_311 | updatingROM | 4x6 | LUT |
|unamed_314 | updatingROM | 4x6 | LUT |
|unamed_317 | updatingROM | 4x6 | LUT |
|unamed_320 | updatingROM | 4x6 | LUT |
|unamed_323 | updatingROM | 4x6 | LUT |
|unamed_326 | updatingROM | 4x6 | LUT |
|unamed_329 | updatingROM | 4x6 | LUT |
|unamed_332 | updatingROM | 4x6 | LUT |
|unamed_335 | updatingROM | 4x6 | LUT |
|unamed_338 | updatingROM | 4x6 | LUT |
|unamed_341 | updatingROM | 4x6 | LUT |
|unamed_344 | updatingROM | 4x6 | LUT |
|unamed_347 | updatingROM | 4x6 | LUT |
|unamed_350 | updatingROM | 4x6 | LUT |
|unamed_353 | updatingROM | 4x6 | LUT |
|unamed_356 | updatingROM | 4x6 | LUT |
|unamed_359 | updatingROM | 4x6 | LUT |
|unamed_362 | updatingROM | 4x6 | LUT |
|unamed_365 | updatingROM | 4x6 | LUT |
|unamed_368 | updatingROM | 4x6 | LUT |
|unamed_371 | updatingROM | 4x6 | LUT |
|unamed_374 | updatingROM | 4x6 | LUT |
|unamed_377 | updatingROM | 4x6 | LUT |
|unamed_380 | updatingROM | 4x6 | LUT |
+------------+-------------------+---------------+----------------+
Block RAM: Preliminary Mapping Report (see note below)
+-------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights |
+-------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|anon_2__GB0 | cores_51/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_61/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_60/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_59/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_58/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_57/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_56/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_52/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_53/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_54/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB0 | cores_55/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB1 | cores_47/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB1 | cores_50/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB1 | cores_62/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB1 | cores_49/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB2 | cores_44/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB2 | cores_45/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB2 | cores_46/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB2 | cores_63/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_40/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_41/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_42/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_43/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_125/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_39/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_38/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_37/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_36/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_35/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_34/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_126/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_48/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_33/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_32/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_31/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_30/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_29/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_28/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_27/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_25/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_26/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_24/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_23/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_22/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_21/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_20/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_19/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_18/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_17/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_16/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_15/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_14/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_13/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_12/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_11/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_10/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_9/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_8/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_7/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_6/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB8 | cores_2/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB8 | cores_3/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB8 | cores_5/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB9 | cores_0/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB9 | cores_1/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB9 | cores_4/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_123/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_121/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_120/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_119/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_118/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_117/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_116/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_115/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_113/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_112/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_110/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB11 | cores_108/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB11 | cores_109/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB11 | cores_114/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB12 | cores_105/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB12 | cores_106/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB12 | cores_107/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB12 | cores_111/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_100/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_101/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_102/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_103/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_122/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_94/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_95/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_96/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_97/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_98/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_99/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_86/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_87/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_88/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_89/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_90/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_91/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_92/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_93/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_77/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_78/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_79/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_80/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_81/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_82/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_83/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_84/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_85/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_104/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_66/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_67/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_68/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_64/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_70/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_71/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_72/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_73/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_74/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_75/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_76/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB18 | cores_124/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB18 | cores_65/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB18 | cores_69/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
+-------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
Distributed RAM: Preliminary Mapping Report (see note below)
+-------------+-----------------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+-----------------------------+-----------+----------------------+----------------+
|anon_2__GB0 | cores_51/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_61/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_60/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_59/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_58/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_57/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_56/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_52/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_53/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_54/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_55/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB1 | cores_47/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB1 | cores_50/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB1 | cores_62/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB1 | cores_49/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB2 | cores_44/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB2 | cores_45/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB2 | cores_46/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB2 | cores_63/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_40/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_41/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_42/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_43/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_125/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_39/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_38/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_37/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_36/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_35/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_34/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_126/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_48/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_33/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_32/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_31/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_30/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_29/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_28/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_27/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_25/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_26/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_24/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_23/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_22/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_21/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_20/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_19/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_18/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_17/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_16/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_15/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_14/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_13/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_12/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_11/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_10/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_9/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_8/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_7/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_6/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB8 | cores_2/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB8 | cores_3/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB8 | cores_5/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB9 | cores_0/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB9 | cores_1/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB9 | cores_4/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_123/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_121/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_120/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_119/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_118/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_117/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_116/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_115/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_113/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_112/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_110/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB11 | cores_108/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB11 | cores_109/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB11 | cores_114/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB12 | cores_105/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB12 | cores_106/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB12 | cores_107/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB12 | cores_111/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_100/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_101/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_102/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_103/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_122/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_94/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_95/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_96/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_97/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_98/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_99/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_86/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_87/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_88/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_89/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_90/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_91/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_92/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_93/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_77/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_78/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_79/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_80/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_81/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_82/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_83/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_84/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_85/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_104/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_66/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_67/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_68/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_64/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_70/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_71/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_72/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_73/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_74/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_75/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_76/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB18 | cores_124/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB18 | cores_65/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB18 | cores_69/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
+-------------+-----------------------------+-----------+----------------------+----------------+
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:04:58 ; elapsed = 00:06:13 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 23546 ; free virtual = 60669
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-5584] The signal "synthRx/cores_51/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5584] The signal "synthRx/cores_61/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5584] The signal "synthRx/cores_60/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5584] The signal "synthRx/cores_59/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5584] The signal "synthRx/cores_58/recordStack_reg" is implemented as distributed LUT RAM for the following reason(s): The timing constraints suggest that the chosen mapping will yield better timing results.
INFO: [Synth 8-5556] The block RAM "synthRx/cores_57/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthRx/cores_57/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthRx/cores_56/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthRx/cores_56/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthRx/cores_52/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthRx/cores_52/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthRx/cores_53/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthRx/cores_53/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthRx/cores_54/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthRx/cores_54/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
INFO: [Synth 8-5556] The block RAM "synthRx/cores_55/recordStack_reg" may be mapped as a cascade chain, because it is not timing critical.
RAM ("synthRx/cores_55/recordStack_reg") is too shallow (depth = 128) to use URAM. Choosing BRAM instead of URAM
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:05:22 ; elapsed = 00:06:37 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 23396 ; free virtual = 60520
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Block RAM: Final Mapping Report
+-------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | Cascade Heights |
+-------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
|synthRx | cores_57/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthRx | cores_56/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthRx | cores_52/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthRx | cores_53/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthRx | cores_54/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|synthRx | cores_55/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB1 | cores_47/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB1 | cores_50/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB1 | cores_62/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB1 | cores_49/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB2 | cores_44/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB2 | cores_45/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB2 | cores_46/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB2 | cores_63/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_40/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_41/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_42/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_43/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB3 | cores_125/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_39/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_38/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_37/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_36/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_35/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_34/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB4 | cores_126/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_48/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_33/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_32/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_31/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_30/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_29/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_28/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_27/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB5 | cores_25/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_26/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_24/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_23/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_22/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_21/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_20/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_19/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_18/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_17/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_16/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB6 | cores_15/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_14/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_13/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_12/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_11/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_10/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_9/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_8/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_7/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB7 | cores_6/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB8 | cores_2/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB8 | cores_3/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB8 | cores_5/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB9 | cores_0/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB9 | cores_1/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB9 | cores_4/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_123/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_121/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_120/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_119/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_118/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_117/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_116/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_115/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_113/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_112/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB10 | cores_110/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB11 | cores_108/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB11 | cores_109/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB11 | cores_114/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB12 | cores_105/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB12 | cores_106/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB12 | cores_107/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB12 | cores_111/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_100/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_101/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_102/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_103/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB13 | cores_122/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_94/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_95/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_96/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_97/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_98/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB14 | cores_99/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_86/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_87/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_88/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_89/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_90/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_91/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_92/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB15 | cores_93/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_77/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_78/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_79/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_80/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_81/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_82/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_83/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_84/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_85/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB16 | cores_104/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_66/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_67/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_68/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_64/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_70/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_71/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_72/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_73/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_74/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_75/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB17 | cores_76/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB18 | cores_124/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB18 | cores_65/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
|anon_2__GB18 | cores_69/recordStack_reg | 128 x 256(READ_FIRST) | W | | 128 x 256(WRITE_FIRST) | | R | Port A and B | 0 | 4 | |
+-------------+---------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+-----------------+
Distributed RAM: Final Mapping Report
+-------------+-----------------------------+-----------+----------------------+----------------+
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
+-------------+-----------------------------+-----------+----------------------+----------------+
|anon_2__GB0 | cores_51/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_61/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_60/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_59/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_58/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_57/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_56/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_52/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_53/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_54/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB0 | cores_55/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB1 | cores_47/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB1 | cores_50/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB1 | cores_62/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB1 | cores_49/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB2 | cores_44/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB2 | cores_45/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB2 | cores_46/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB2 | cores_63/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_40/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_41/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_42/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_43/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB3 | cores_125/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_39/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_38/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_37/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_36/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_35/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_34/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB4 | cores_126/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_48/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_33/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_32/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_31/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_30/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_29/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_28/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_27/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB5 | cores_25/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_26/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_24/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_23/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_22/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_21/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_20/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_19/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_18/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_17/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_16/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB6 | cores_15/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_14/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_13/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_12/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_11/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_10/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_9/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_8/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_7/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB7 | cores_6/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB8 | cores_2/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB8 | cores_3/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB8 | cores_5/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB9 | cores_0/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB9 | cores_1/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB9 | cores_4/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_123/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_121/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_120/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_119/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_118/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_117/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_116/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_115/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_113/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_112/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB10 | cores_110/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB11 | cores_108/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB11 | cores_109/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB11 | cores_114/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB12 | cores_105/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB12 | cores_106/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB12 | cores_107/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB12 | cores_111/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_100/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_101/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_102/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_103/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB13 | cores_122/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_94/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_95/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_96/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_97/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_98/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB14 | cores_99/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_86/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_87/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_88/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_89/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_90/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_91/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_92/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB15 | cores_93/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_77/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_78/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_79/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_80/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_81/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_82/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_83/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_84/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_85/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB16 | cores_104/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_66/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_67/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_68/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_64/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_70/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_71/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_72/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_73/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_74/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_75/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB17 | cores_76/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB18 | cores_124/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB18 | cores_65/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
|anon_2__GB18 | cores_69/reverse/stack_reg | Implied | 128 x 1 | RAM128X1D x 1 |
+-------------+-----------------------------+-----------+----------------------+----------------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-5816] Retiming module `unamed__GB0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GB0' done
INFO: [Synth 8-5816] Retiming module `unamed__GB1`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GB1' done
INFO: [Synth 8-5816] Retiming module `unamed__GB2`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `unamed__GB2' done
INFO: [Synth 8-5816] Retiming module `anon__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `anon__GC0' done
INFO: [Synth 8-5816] Retiming module `QamdemodFtn_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `QamdemodFtn_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `deintrlvFtn_dut`
Numbers of forward move = 2, and backward move = 0
Retimed registers names:
core0/core/core1/core/localCounter_value_reg[2]_fret
core0/core/core1/core/localCounter_value_reg[6]_fret
INFO: [Synth 8-5816] Retiming module `deintrlvFtn_dut' done
INFO: [Synth 8-5816] Retiming module `QamdemodFtn_deintrlvFtn_dut__GC0`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `QamdemodFtn_deintrlvFtn_dut__GC0' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
WARNING: [Synth 8-3332] Sequential element (core/localCounter_value_reg[6]_fret) is unused and will be removed from module deintrlvFtn_dut.
INFO: [Synth 8-5816] Retiming module `anon_2__GB0_tempName`
Numbers of forward move = 0, and backward move = 48
Retimed registers names:
core1/core/cores_52/backward/currentState_reg[0]_bret__0
core1/core/cores_52/backward/currentState_reg[0]_bret__1
core1/core/cores_52/backward/currentState_reg[0]_bret__2
core1/core/cores_52/backward/currentState_reg[0]_bret__3
core1/core/cores_52/backward/currentState_reg[0]_bret__4
core1/core/cores_52/backward/currentState_reg[0]_bret_bret
core1/core/cores_52/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_52/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_52/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_52/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_52/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_52/backward/currentState_reg[1]_bret
core1/core/cores_52/backward/currentState_reg[1]_bret__1
core1/core/cores_52/backward/currentState_reg[1]_bret__2
core1/core/cores_52/backward/currentState_reg[1]_bret__3
core1/core/cores_52/backward/currentState_reg[2]_bret
core1/core/cores_52/backward/currentState_reg[2]_bret__1
core1/core/cores_52/backward/currentState_reg[2]_bret__2
core1/core/cores_52/backward/currentState_reg[2]_bret__3
core1/core/cores_52/backward/currentState_reg[3]_bret
core1/core/cores_52/backward/currentState_reg[3]_bret__1
core1/core/cores_52/backward/currentState_reg[3]_bret__2
core1/core/cores_52/backward/currentState_reg[3]_bret__3
core1/core/cores_52/backward/currentState_reg[4]_bret
core1/core/cores_52/backward/currentState_reg[4]_bret__1
core1/core/cores_52/backward/currentState_reg[4]_bret__2
core1/core/cores_52/backward/currentState_reg[4]_bret__3
core1/core/cores_52/backward/currentState_reg[5]_bret
core1/core/cores_52/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_52/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_52/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_52/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_52/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_52/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_52/backward/currentState_reg[5]_bret__1
core1/core/cores_52/backward/currentState_reg[5]_bret__2
core1/core/cores_52/backward/currentState_reg[5]_bret__3
core1/core/cores_53/backward/currentState_reg[0]_bret__0
core1/core/cores_53/backward/currentState_reg[0]_bret__1
core1/core/cores_53/backward/currentState_reg[0]_bret__2
core1/core/cores_53/backward/currentState_reg[0]_bret__3
core1/core/cores_53/backward/currentState_reg[0]_bret__4
core1/core/cores_53/backward/currentState_reg[0]_bret_bret
core1/core/cores_53/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_53/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_53/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_53/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_53/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_53/backward/currentState_reg[1]_bret
core1/core/cores_53/backward/currentState_reg[1]_bret__1
core1/core/cores_53/backward/currentState_reg[1]_bret__2
core1/core/cores_53/backward/currentState_reg[1]_bret__3
core1/core/cores_53/backward/currentState_reg[2]_bret
core1/core/cores_53/backward/currentState_reg[2]_bret__1
core1/core/cores_53/backward/currentState_reg[2]_bret__2
core1/core/cores_53/backward/currentState_reg[2]_bret__3
core1/core/cores_53/backward/currentState_reg[3]_bret
core1/core/cores_53/backward/currentState_reg[3]_bret__1
core1/core/cores_53/backward/currentState_reg[3]_bret__2
core1/core/cores_53/backward/currentState_reg[3]_bret__3
core1/core/cores_53/backward/currentState_reg[4]_bret
core1/core/cores_53/backward/currentState_reg[4]_bret__1
core1/core/cores_53/backward/currentState_reg[4]_bret__2
core1/core/cores_53/backward/currentState_reg[4]_bret__3
core1/core/cores_53/backward/currentState_reg[5]_bret
core1/core/cores_53/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_53/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_53/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_53/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_53/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_53/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_53/backward/currentState_reg[5]_bret__1
core1/core/cores_53/backward/currentState_reg[5]_bret__2
core1/core/cores_53/backward/currentState_reg[5]_bret__3
core1/core/cores_54/backward/currentState_reg[0]_bret__0
core1/core/cores_54/backward/currentState_reg[0]_bret__1
core1/core/cores_54/backward/currentState_reg[0]_bret__2
core1/core/cores_54/backward/currentState_reg[0]_bret__3
core1/core/cores_54/backward/currentState_reg[0]_bret__4
core1/core/cores_54/backward/currentState_reg[0]_bret_bret
core1/core/cores_54/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_54/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_54/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_54/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_54/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_54/backward/currentState_reg[1]_bret
core1/core/cores_54/backward/currentState_reg[1]_bret__1
core1/core/cores_54/backward/currentState_reg[1]_bret__2
core1/core/cores_54/backward/currentState_reg[1]_bret__3
core1/core/cores_54/backward/currentState_reg[2]_bret
core1/core/cores_54/backward/currentState_reg[2]_bret__1
core1/core/cores_54/backward/currentState_reg[2]_bret__2
core1/core/cores_54/backward/currentState_reg[2]_bret__3
core1/core/cores_54/backward/currentState_reg[3]_bret
core1/core/cores_54/backward/currentState_reg[3]_bret__1
core1/core/cores_54/backward/currentState_reg[3]_bret__2
core1/core/cores_54/backward/currentState_reg[3]_bret__3
core1/core/cores_54/backward/currentState_reg[4]_bret
core1/core/cores_54/backward/currentState_reg[4]_bret__1
core1/core/cores_54/backward/currentState_reg[4]_bret__2
core1/core/cores_54/backward/currentState_reg[4]_bret__3
core1/core/cores_54/backward/currentState_reg[5]_bret
core1/core/cores_54/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_54/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_54/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_54/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_54/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_54/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_54/backward/currentState_reg[5]_bret__1
core1/core/cores_54/backward/currentState_reg[5]_bret__2
core1/core/cores_54/backward/currentState_reg[5]_bret__3
core1/core/cores_55/backward/currentState_reg[0]_bret__0
core1/core/cores_55/backward/currentState_reg[0]_bret__1
core1/core/cores_55/backward/currentState_reg[0]_bret__2
core1/core/cores_55/backward/currentState_reg[0]_bret__3
core1/core/cores_55/backward/currentState_reg[0]_bret__4
core1/core/cores_55/backward/currentState_reg[0]_bret_bret
core1/core/cores_55/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_55/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_55/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_55/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_55/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_55/backward/currentState_reg[1]_bret
core1/core/cores_55/backward/currentState_reg[1]_bret__1
core1/core/cores_55/backward/currentState_reg[1]_bret__2
core1/core/cores_55/backward/currentState_reg[1]_bret__3
core1/core/cores_55/backward/currentState_reg[2]_bret
core1/core/cores_55/backward/currentState_reg[2]_bret__1
core1/core/cores_55/backward/currentState_reg[2]_bret__2
core1/core/cores_55/backward/currentState_reg[2]_bret__3
core1/core/cores_55/backward/currentState_reg[3]_bret
core1/core/cores_55/backward/currentState_reg[3]_bret__1
core1/core/cores_55/backward/currentState_reg[3]_bret__2
core1/core/cores_55/backward/currentState_reg[3]_bret__3
core1/core/cores_55/backward/currentState_reg[4]_bret
core1/core/cores_55/backward/currentState_reg[4]_bret__1
core1/core/cores_55/backward/currentState_reg[4]_bret__2
core1/core/cores_55/backward/currentState_reg[4]_bret__3
core1/core/cores_55/backward/currentState_reg[5]_bret
core1/core/cores_55/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_55/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_55/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_55/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_55/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_55/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_55/backward/currentState_reg[5]_bret__1
core1/core/cores_55/backward/currentState_reg[5]_bret__2
core1/core/cores_55/backward/currentState_reg[5]_bret__3
core1/core/cores_56/backward/currentState_reg[0]_bret__0
core1/core/cores_56/backward/currentState_reg[0]_bret__1
core1/core/cores_56/backward/currentState_reg[0]_bret__2
core1/core/cores_56/backward/currentState_reg[0]_bret__3
core1/core/cores_56/backward/currentState_reg[0]_bret__4
core1/core/cores_56/backward/currentState_reg[0]_bret_bret
core1/core/cores_56/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_56/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_56/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_56/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_56/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_56/backward/currentState_reg[1]_bret
core1/core/cores_56/backward/currentState_reg[1]_bret__1
core1/core/cores_56/backward/currentState_reg[1]_bret__2
core1/core/cores_56/backward/currentState_reg[1]_bret__3
core1/core/cores_56/backward/currentState_reg[2]_bret
core1/core/cores_56/backward/currentState_reg[2]_bret__1
core1/core/cores_56/backward/currentState_reg[2]_bret__2
core1/core/cores_56/backward/currentState_reg[2]_bret__3
core1/core/cores_56/backward/currentState_reg[3]_bret
core1/core/cores_56/backward/currentState_reg[3]_bret__1
core1/core/cores_56/backward/currentState_reg[3]_bret__2
core1/core/cores_56/backward/currentState_reg[3]_bret__3
core1/core/cores_56/backward/currentState_reg[4]_bret
core1/core/cores_56/backward/currentState_reg[4]_bret__1
core1/core/cores_56/backward/currentState_reg[4]_bret__2
core1/core/cores_56/backward/currentState_reg[4]_bret__3
core1/core/cores_56/backward/currentState_reg[5]_bret
core1/core/cores_56/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_56/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_56/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_56/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_56/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_56/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_56/backward/currentState_reg[5]_bret__1
core1/core/cores_56/backward/currentState_reg[5]_bret__2
core1/core/cores_56/backward/currentState_reg[5]_bret__3
core1/core/cores_57/backward/currentState_reg[0]_bret__0
core1/core/cores_57/backward/currentState_reg[0]_bret__1
core1/core/cores_57/backward/currentState_reg[0]_bret__2
core1/core/cores_57/backward/currentState_reg[0]_bret__3
core1/core/cores_57/backward/currentState_reg[0]_bret__4
core1/core/cores_57/backward/currentState_reg[0]_bret_bret
core1/core/cores_57/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_57/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_57/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_57/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_57/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_57/backward/currentState_reg[1]_bret
core1/core/cores_57/backward/currentState_reg[1]_bret__1
core1/core/cores_57/backward/currentState_reg[1]_bret__2
core1/core/cores_57/backward/currentState_reg[1]_bret__3
core1/core/cores_57/backward/currentState_reg[2]_bret
core1/core/cores_57/backward/currentState_reg[2]_bret__1
core1/core/cores_57/backward/currentState_reg[2]_bret__2
core1/core/cores_57/backward/currentState_reg[2]_bret__3
core1/core/cores_57/backward/currentState_reg[3]_bret
core1/core/cores_57/backward/currentState_reg[3]_bret__1
core1/core/cores_57/backward/currentState_reg[3]_bret__2
core1/core/cores_57/backward/currentState_reg[3]_bret__3
core1/core/cores_57/backward/currentState_reg[4]_bret
core1/core/cores_57/backward/currentState_reg[4]_bret__1
core1/core/cores_57/backward/currentState_reg[4]_bret__2
core1/core/cores_57/backward/currentState_reg[4]_bret__3
core1/core/cores_57/backward/currentState_reg[5]_bret
core1/core/cores_57/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_57/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_57/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_57/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_57/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_57/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_57/backward/currentState_reg[5]_bret__1
core1/core/cores_57/backward/currentState_reg[5]_bret__2
core1/core/cores_57/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB0_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/reverse/lastIn_delay_1_reg' (FDC) to 'corei_6/core1/core/cores_57/backward/currentState_reg[0]_bret__4'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_55/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_55/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_55/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_55/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_55/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_55/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_55/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_54/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_54/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_54/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_54/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_54/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_54/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_54/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_54/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_54/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_54/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_54/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_54/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_54/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_54/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_53/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_53/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_53/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_53/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_53/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_53/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_53/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_53/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_53/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_53/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_53/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_53/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_53/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_53/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_52/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_52/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_52/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_52/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_52/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_52/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_52/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_52/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_52/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_52/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_52/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_52/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_52/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_52/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_56/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_56/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_56/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_56/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_56/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_56/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_56/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_56/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_56/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_56/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_56/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_56/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_56/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_56/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_57/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_57/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_57/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_57/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_57/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_57/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_57/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_57/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_57/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_57/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_57/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_57/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_57/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_57/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_58/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_58/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_58/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_58/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_58/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_58/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_58/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_58/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_58/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_58/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_58/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_58/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_58/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_58/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_58/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_59/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_59/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_59/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_59/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_59/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_59/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_59/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_59/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_59/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_59/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_59/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_59/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_59/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_59/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_59/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_60/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_60/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_60/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_60/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_60/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_60/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_60/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_60/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_60/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_60/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_60/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_60/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_60/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_60/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_60/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_61/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_61/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_61/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_61/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_61/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_61/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_61/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_61/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_61/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_61/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_61/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_61/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_61/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_61/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_61/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_51/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_51/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_51/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_51/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_51/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_51/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_51/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_51/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_55/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_54/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_54/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_53/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_53/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_52/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_52/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_56/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_56/writeLock_reg' (FDPE) to 'corei_6/core1/core/cores_57/writeLock_reg'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/reverse/readCounter_reg_rep[6]' (FD) to 'corei_6/core1/core/cores_55/reverse/readCounter_reg[6]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/reverse/readCounter_reg_rep[4]' (FD) to 'corei_6/core1/core/cores_55/reverse/readCounter_reg[4]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/reverse/readCounter_reg_rep[2]' (FD) to 'corei_6/core1/core/cores_55/reverse/readCounter_reg[2]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/reverse/readCounter_reg_rep[0]' (FD) to 'corei_6/core1/core/cores_55/reverse/readCounter_reg[0]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/reverse/readCounter_reg_rep[1]' (FD) to 'corei_6/core1/core/cores_55/reverse/readCounter_reg[1]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/reverse/readCounter_reg_rep[3]' (FD) to 'corei_6/core1/core/cores_55/reverse/readCounter_reg[3]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/reverse/readCounter_reg_rep[5]' (FD) to 'corei_6/core1/core/cores_55/reverse/readCounter_reg[5]'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/backward/currentState_reg[3]_bret' (FDC) to 'corei_6/core1/core/cores_57/backward/currentState_reg[0]_bret__4'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/backward/currentState_reg[3]_bret__1' (FDC) to 'corei_6/core1/core/cores_55/backward/currentState_reg[0]_bret__2'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/backward/currentState_reg[3]_bret__2' (FDC) to 'corei_6/core1/core/cores_55/backward/currentState_reg[0]_bret__3'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/backward/currentState_reg[2]_bret' (FDC) to 'corei_6/core1/core/cores_57/backward/currentState_reg[0]_bret__4'
INFO: [Synth 8-3886] merging instance 'corei_6/core1/core/cores_55/backward/currentState_reg[2]_bret__1' (FDC) to 'corei_6/core1/core/cores_55/backward/currentState_reg[0]_bret__2'
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_57/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_57/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_57/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_57/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_56/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_56/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_56/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_56/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_52/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_52/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_52/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_52/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_53/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_53/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_53/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_53/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_54/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_54/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_54/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_54/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_55/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_55/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_55/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_6/core1/core/cores_55/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-5816] Retiming module `anon_2__GB1_tempName`
Numbers of forward move = 0, and backward move = 40
Retimed registers names:
core1/core/cores_47/backward/currentState_reg[0]_bret__0
core1/core/cores_47/backward/currentState_reg[0]_bret__1
core1/core/cores_47/backward/currentState_reg[0]_bret__4
core1/core/cores_47/backward/currentState_reg[0]_bret_bret
core1/core/cores_47/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_47/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_47/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_47/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_47/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_47/backward/currentState_reg[1]_bret
core1/core/cores_47/backward/currentState_reg[1]_bret__3
core1/core/cores_47/backward/currentState_reg[2]_bret
core1/core/cores_47/backward/currentState_reg[2]_bret__3
core1/core/cores_47/backward/currentState_reg[3]_bret
core1/core/cores_47/backward/currentState_reg[3]_bret__3
core1/core/cores_47/backward/currentState_reg[4]_bret
core1/core/cores_47/backward/currentState_reg[4]_bret__3
core1/core/cores_47/backward/currentState_reg[5]_bret
core1/core/cores_47/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_47/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_47/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_47/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_47/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_47/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_47/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_47/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_47/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_47/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_47/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_47/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_47/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_47/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_47/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_47/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_47/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_47/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_47/backward/currentState_reg[5]_bret__3
core1/core/cores_49/backward/currentState_reg[0]_bret__0
core1/core/cores_49/backward/currentState_reg[0]_bret__1
core1/core/cores_49/backward/currentState_reg[0]_bret__4
core1/core/cores_49/backward/currentState_reg[0]_bret_bret
core1/core/cores_49/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_49/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_49/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_49/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_49/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_49/backward/currentState_reg[1]_bret
core1/core/cores_49/backward/currentState_reg[1]_bret__3
core1/core/cores_49/backward/currentState_reg[2]_bret
core1/core/cores_49/backward/currentState_reg[2]_bret__3
core1/core/cores_49/backward/currentState_reg[3]_bret
core1/core/cores_49/backward/currentState_reg[3]_bret__3
core1/core/cores_49/backward/currentState_reg[4]_bret
core1/core/cores_49/backward/currentState_reg[4]_bret__3
core1/core/cores_49/backward/currentState_reg[5]_bret
core1/core/cores_49/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_49/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_49/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_49/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_49/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_49/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_49/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_49/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_49/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_49/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_49/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_49/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_49/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_49/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_49/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_49/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_49/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_49/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_49/backward/currentState_reg[5]_bret__3
core1/core/cores_50/backward/currentState_reg[0]_bret__0
core1/core/cores_50/backward/currentState_reg[0]_bret__1
core1/core/cores_50/backward/currentState_reg[0]_bret__4
core1/core/cores_50/backward/currentState_reg[0]_bret_bret
core1/core/cores_50/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_50/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_50/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_50/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_50/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_50/backward/currentState_reg[1]_bret
core1/core/cores_50/backward/currentState_reg[1]_bret__3
core1/core/cores_50/backward/currentState_reg[2]_bret
core1/core/cores_50/backward/currentState_reg[2]_bret__3
core1/core/cores_50/backward/currentState_reg[3]_bret
core1/core/cores_50/backward/currentState_reg[3]_bret__3
core1/core/cores_50/backward/currentState_reg[4]_bret
core1/core/cores_50/backward/currentState_reg[4]_bret__3
core1/core/cores_50/backward/currentState_reg[5]_bret
core1/core/cores_50/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_50/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_50/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_50/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_50/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_50/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_50/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_50/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_50/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_50/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_50/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_50/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_50/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_50/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_50/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_50/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_50/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_50/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_50/backward/currentState_reg[5]_bret__3
core1/core/cores_62/backward/currentState_reg[0]_bret__0
core1/core/cores_62/backward/currentState_reg[0]_bret__1
core1/core/cores_62/backward/currentState_reg[0]_bret__4
core1/core/cores_62/backward/currentState_reg[0]_bret_bret
core1/core/cores_62/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_62/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_62/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_62/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_62/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_62/backward/currentState_reg[1]_bret
core1/core/cores_62/backward/currentState_reg[1]_bret__3
core1/core/cores_62/backward/currentState_reg[2]_bret
core1/core/cores_62/backward/currentState_reg[2]_bret__3
core1/core/cores_62/backward/currentState_reg[3]_bret
core1/core/cores_62/backward/currentState_reg[3]_bret__3
core1/core/cores_62/backward/currentState_reg[4]_bret
core1/core/cores_62/backward/currentState_reg[4]_bret__3
core1/core/cores_62/backward/currentState_reg[5]_bret
core1/core/cores_62/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_62/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_62/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_62/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_62/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_62/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_62/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_62/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_62/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_62/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_62/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_62/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_62/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_62/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_62/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_62/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_62/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_62/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_62/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB1_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB2_tempName`
Numbers of forward move = 0, and backward move = 40
Retimed registers names:
core1/core/cores_44/backward/currentState_reg[0]_bret__0
core1/core/cores_44/backward/currentState_reg[0]_bret__1
core1/core/cores_44/backward/currentState_reg[0]_bret__4
core1/core/cores_44/backward/currentState_reg[0]_bret_bret
core1/core/cores_44/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_44/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_44/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_44/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_44/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_44/backward/currentState_reg[1]_bret
core1/core/cores_44/backward/currentState_reg[1]_bret__3
core1/core/cores_44/backward/currentState_reg[2]_bret
core1/core/cores_44/backward/currentState_reg[2]_bret__3
core1/core/cores_44/backward/currentState_reg[3]_bret
core1/core/cores_44/backward/currentState_reg[3]_bret__3
core1/core/cores_44/backward/currentState_reg[4]_bret
core1/core/cores_44/backward/currentState_reg[4]_bret__3
core1/core/cores_44/backward/currentState_reg[5]_bret
core1/core/cores_44/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_44/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_44/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_44/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_44/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_44/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_44/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_44/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_44/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_44/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_44/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_44/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_44/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_44/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_44/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_44/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_44/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_44/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_44/backward/currentState_reg[5]_bret__3
core1/core/cores_45/backward/currentState_reg[0]_bret__0
core1/core/cores_45/backward/currentState_reg[0]_bret__1
core1/core/cores_45/backward/currentState_reg[0]_bret__4
core1/core/cores_45/backward/currentState_reg[0]_bret_bret
core1/core/cores_45/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_45/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_45/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_45/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_45/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_45/backward/currentState_reg[1]_bret
core1/core/cores_45/backward/currentState_reg[1]_bret__3
core1/core/cores_45/backward/currentState_reg[2]_bret
core1/core/cores_45/backward/currentState_reg[2]_bret__3
core1/core/cores_45/backward/currentState_reg[3]_bret
core1/core/cores_45/backward/currentState_reg[3]_bret__3
core1/core/cores_45/backward/currentState_reg[4]_bret
core1/core/cores_45/backward/currentState_reg[4]_bret__3
core1/core/cores_45/backward/currentState_reg[5]_bret
core1/core/cores_45/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_45/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_45/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_45/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_45/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_45/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_45/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_45/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_45/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_45/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_45/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_45/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_45/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_45/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_45/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_45/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_45/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_45/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_45/backward/currentState_reg[5]_bret__3
core1/core/cores_46/backward/currentState_reg[0]_bret__0
core1/core/cores_46/backward/currentState_reg[0]_bret__1
core1/core/cores_46/backward/currentState_reg[0]_bret__4
core1/core/cores_46/backward/currentState_reg[0]_bret_bret
core1/core/cores_46/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_46/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_46/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_46/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_46/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_46/backward/currentState_reg[1]_bret
core1/core/cores_46/backward/currentState_reg[1]_bret__3
core1/core/cores_46/backward/currentState_reg[2]_bret
core1/core/cores_46/backward/currentState_reg[2]_bret__3
core1/core/cores_46/backward/currentState_reg[3]_bret
core1/core/cores_46/backward/currentState_reg[3]_bret__3
core1/core/cores_46/backward/currentState_reg[4]_bret
core1/core/cores_46/backward/currentState_reg[4]_bret__3
core1/core/cores_46/backward/currentState_reg[5]_bret
core1/core/cores_46/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_46/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_46/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_46/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_46/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_46/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_46/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_46/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_46/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_46/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_46/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_46/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_46/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_46/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_46/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_46/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_46/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_46/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_46/backward/currentState_reg[5]_bret__3
core1/core/cores_63/backward/currentState_reg[0]_bret__0
core1/core/cores_63/backward/currentState_reg[0]_bret__1
core1/core/cores_63/backward/currentState_reg[0]_bret__4
core1/core/cores_63/backward/currentState_reg[0]_bret_bret
core1/core/cores_63/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_63/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_63/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_63/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_63/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_63/backward/currentState_reg[1]_bret
core1/core/cores_63/backward/currentState_reg[1]_bret__3
core1/core/cores_63/backward/currentState_reg[2]_bret
core1/core/cores_63/backward/currentState_reg[2]_bret__3
core1/core/cores_63/backward/currentState_reg[3]_bret
core1/core/cores_63/backward/currentState_reg[3]_bret__3
core1/core/cores_63/backward/currentState_reg[4]_bret
core1/core/cores_63/backward/currentState_reg[4]_bret__3
core1/core/cores_63/backward/currentState_reg[5]_bret
core1/core/cores_63/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_63/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_63/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_63/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_63/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_63/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_63/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_63/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_63/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_63/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_63/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_63/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_63/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_63/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_63/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_63/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_63/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_63/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_63/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB2_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB3_tempName`
Numbers of forward move = 0, and backward move = 50
Retimed registers names:
core1/core/cores_125/backward/currentState_reg[0]_bret__0
core1/core/cores_125/backward/currentState_reg[0]_bret__1
core1/core/cores_125/backward/currentState_reg[0]_bret__4
core1/core/cores_125/backward/currentState_reg[0]_bret_bret
core1/core/cores_125/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_125/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_125/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_125/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_125/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_125/backward/currentState_reg[1]_bret
core1/core/cores_125/backward/currentState_reg[1]_bret__3
core1/core/cores_125/backward/currentState_reg[2]_bret
core1/core/cores_125/backward/currentState_reg[2]_bret__3
core1/core/cores_125/backward/currentState_reg[3]_bret
core1/core/cores_125/backward/currentState_reg[3]_bret__3
core1/core/cores_125/backward/currentState_reg[4]_bret
core1/core/cores_125/backward/currentState_reg[4]_bret__3
core1/core/cores_125/backward/currentState_reg[5]_bret
core1/core/cores_125/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_125/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_125/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_125/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_125/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_125/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_125/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_125/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_125/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_125/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_125/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_125/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_125/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_125/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_125/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_125/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_125/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_125/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_125/backward/currentState_reg[5]_bret__3
core1/core/cores_40/backward/currentState_reg[0]_bret__0
core1/core/cores_40/backward/currentState_reg[0]_bret__1
core1/core/cores_40/backward/currentState_reg[0]_bret__4
core1/core/cores_40/backward/currentState_reg[0]_bret_bret
core1/core/cores_40/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_40/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_40/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_40/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_40/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_40/backward/currentState_reg[1]_bret
core1/core/cores_40/backward/currentState_reg[1]_bret__3
core1/core/cores_40/backward/currentState_reg[2]_bret
core1/core/cores_40/backward/currentState_reg[2]_bret__3
core1/core/cores_40/backward/currentState_reg[3]_bret
core1/core/cores_40/backward/currentState_reg[3]_bret__3
core1/core/cores_40/backward/currentState_reg[4]_bret
core1/core/cores_40/backward/currentState_reg[4]_bret__3
core1/core/cores_40/backward/currentState_reg[5]_bret
core1/core/cores_40/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_40/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_40/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_40/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_40/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_40/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_40/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_40/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_40/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_40/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_40/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_40/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_40/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_40/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_40/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_40/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_40/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_40/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_40/backward/currentState_reg[5]_bret__3
core1/core/cores_41/backward/currentState_reg[0]_bret__0
core1/core/cores_41/backward/currentState_reg[0]_bret__1
core1/core/cores_41/backward/currentState_reg[0]_bret__4
core1/core/cores_41/backward/currentState_reg[0]_bret_bret
core1/core/cores_41/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_41/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_41/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_41/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_41/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_41/backward/currentState_reg[1]_bret
core1/core/cores_41/backward/currentState_reg[1]_bret__3
core1/core/cores_41/backward/currentState_reg[2]_bret
core1/core/cores_41/backward/currentState_reg[2]_bret__3
core1/core/cores_41/backward/currentState_reg[3]_bret
core1/core/cores_41/backward/currentState_reg[3]_bret__3
core1/core/cores_41/backward/currentState_reg[4]_bret
core1/core/cores_41/backward/currentState_reg[4]_bret__3
core1/core/cores_41/backward/currentState_reg[5]_bret
core1/core/cores_41/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_41/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_41/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_41/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_41/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_41/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_41/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_41/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_41/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_41/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_41/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_41/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_41/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_41/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_41/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_41/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_41/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_41/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_41/backward/currentState_reg[5]_bret__3
core1/core/cores_42/backward/currentState_reg[0]_bret__0
core1/core/cores_42/backward/currentState_reg[0]_bret__1
core1/core/cores_42/backward/currentState_reg[0]_bret__4
core1/core/cores_42/backward/currentState_reg[0]_bret_bret
core1/core/cores_42/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_42/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_42/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_42/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_42/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_42/backward/currentState_reg[1]_bret
core1/core/cores_42/backward/currentState_reg[1]_bret__3
core1/core/cores_42/backward/currentState_reg[2]_bret
core1/core/cores_42/backward/currentState_reg[2]_bret__3
core1/core/cores_42/backward/currentState_reg[3]_bret
core1/core/cores_42/backward/currentState_reg[3]_bret__3
core1/core/cores_42/backward/currentState_reg[4]_bret
core1/core/cores_42/backward/currentState_reg[4]_bret__3
core1/core/cores_42/backward/currentState_reg[5]_bret
core1/core/cores_42/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_42/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_42/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_42/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_42/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_42/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_42/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_42/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_42/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_42/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_42/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_42/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_42/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_42/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_42/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_42/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_42/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_42/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_42/backward/currentState_reg[5]_bret__3
core1/core/cores_43/backward/currentState_reg[0]_bret__0
core1/core/cores_43/backward/currentState_reg[0]_bret__1
core1/core/cores_43/backward/currentState_reg[0]_bret__4
core1/core/cores_43/backward/currentState_reg[0]_bret_bret
core1/core/cores_43/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_43/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_43/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_43/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_43/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_43/backward/currentState_reg[1]_bret
core1/core/cores_43/backward/currentState_reg[1]_bret__3
core1/core/cores_43/backward/currentState_reg[2]_bret
core1/core/cores_43/backward/currentState_reg[2]_bret__3
core1/core/cores_43/backward/currentState_reg[3]_bret
core1/core/cores_43/backward/currentState_reg[3]_bret__3
core1/core/cores_43/backward/currentState_reg[4]_bret
core1/core/cores_43/backward/currentState_reg[4]_bret__3
core1/core/cores_43/backward/currentState_reg[5]_bret
core1/core/cores_43/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_43/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_43/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_43/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_43/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_43/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_43/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_43/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_43/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_43/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_43/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_43/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_43/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_43/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_43/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_43/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_43/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_43/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_43/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB3_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_40/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_40/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_40/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_40/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_41/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_41/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_41/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_41/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_42/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_42/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_42/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_42/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_43/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_43/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_43/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_43/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_125/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_125/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_125/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_9/core1/core/cores_125/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `anon_2__GB4_tempName`
Numbers of forward move = 0, and backward move = 70
Retimed registers names:
core1/core/cores_126/backward/currentState_reg[0]_bret__0
core1/core/cores_126/backward/currentState_reg[0]_bret__1
core1/core/cores_126/backward/currentState_reg[0]_bret__4
core1/core/cores_126/backward/currentState_reg[0]_bret_bret
core1/core/cores_126/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_126/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_126/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_126/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_126/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_126/backward/currentState_reg[1]_bret
core1/core/cores_126/backward/currentState_reg[1]_bret__3
core1/core/cores_126/backward/currentState_reg[2]_bret
core1/core/cores_126/backward/currentState_reg[2]_bret__3
core1/core/cores_126/backward/currentState_reg[3]_bret
core1/core/cores_126/backward/currentState_reg[3]_bret__3
core1/core/cores_126/backward/currentState_reg[4]_bret
core1/core/cores_126/backward/currentState_reg[4]_bret__3
core1/core/cores_126/backward/currentState_reg[5]_bret
core1/core/cores_126/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_126/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_126/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_126/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_126/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_126/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_126/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_126/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_126/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_126/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_126/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_126/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_126/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_126/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_126/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_126/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_126/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_126/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_126/backward/currentState_reg[5]_bret__3
core1/core/cores_34/backward/currentState_reg[0]_bret__0
core1/core/cores_34/backward/currentState_reg[0]_bret__1
core1/core/cores_34/backward/currentState_reg[0]_bret__4
core1/core/cores_34/backward/currentState_reg[0]_bret_bret
core1/core/cores_34/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_34/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_34/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_34/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_34/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_34/backward/currentState_reg[1]_bret
core1/core/cores_34/backward/currentState_reg[1]_bret__3
core1/core/cores_34/backward/currentState_reg[2]_bret
core1/core/cores_34/backward/currentState_reg[2]_bret__3
core1/core/cores_34/backward/currentState_reg[3]_bret
core1/core/cores_34/backward/currentState_reg[3]_bret__3
core1/core/cores_34/backward/currentState_reg[4]_bret
core1/core/cores_34/backward/currentState_reg[4]_bret__3
core1/core/cores_34/backward/currentState_reg[5]_bret
core1/core/cores_34/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_34/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_34/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_34/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_34/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_34/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_34/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_34/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_34/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_34/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_34/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_34/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_34/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_34/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_34/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_34/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_34/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_34/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_34/backward/currentState_reg[5]_bret__3
core1/core/cores_35/backward/currentState_reg[0]_bret__0
core1/core/cores_35/backward/currentState_reg[0]_bret__1
core1/core/cores_35/backward/currentState_reg[0]_bret__4
core1/core/cores_35/backward/currentState_reg[0]_bret_bret
core1/core/cores_35/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_35/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_35/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_35/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_35/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_35/backward/currentState_reg[1]_bret
core1/core/cores_35/backward/currentState_reg[1]_bret__3
core1/core/cores_35/backward/currentState_reg[2]_bret
core1/core/cores_35/backward/currentState_reg[2]_bret__3
core1/core/cores_35/backward/currentState_reg[3]_bret
core1/core/cores_35/backward/currentState_reg[3]_bret__3
core1/core/cores_35/backward/currentState_reg[4]_bret
core1/core/cores_35/backward/currentState_reg[4]_bret__3
core1/core/cores_35/backward/currentState_reg[5]_bret
core1/core/cores_35/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_35/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_35/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_35/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_35/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_35/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_35/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_35/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_35/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_35/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_35/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_35/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_35/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_35/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_35/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_35/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_35/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_35/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_35/backward/currentState_reg[5]_bret__3
core1/core/cores_36/backward/currentState_reg[0]_bret__0
core1/core/cores_36/backward/currentState_reg[0]_bret__1
core1/core/cores_36/backward/currentState_reg[0]_bret__4
core1/core/cores_36/backward/currentState_reg[0]_bret_bret
core1/core/cores_36/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_36/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_36/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_36/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_36/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_36/backward/currentState_reg[1]_bret
core1/core/cores_36/backward/currentState_reg[1]_bret__3
core1/core/cores_36/backward/currentState_reg[2]_bret
core1/core/cores_36/backward/currentState_reg[2]_bret__3
core1/core/cores_36/backward/currentState_reg[3]_bret
core1/core/cores_36/backward/currentState_reg[3]_bret__3
core1/core/cores_36/backward/currentState_reg[4]_bret
core1/core/cores_36/backward/currentState_reg[4]_bret__3
core1/core/cores_36/backward/currentState_reg[5]_bret
core1/core/cores_36/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_36/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_36/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_36/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_36/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_36/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_36/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_36/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_36/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_36/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_36/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_36/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_36/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_36/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_36/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_36/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_36/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_36/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_36/backward/currentState_reg[5]_bret__3
core1/core/cores_37/backward/currentState_reg[0]_bret__0
core1/core/cores_37/backward/currentState_reg[0]_bret__1
core1/core/cores_37/backward/currentState_reg[0]_bret__4
core1/core/cores_37/backward/currentState_reg[0]_bret_bret
core1/core/cores_37/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_37/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_37/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_37/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_37/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_37/backward/currentState_reg[1]_bret
core1/core/cores_37/backward/currentState_reg[1]_bret__3
core1/core/cores_37/backward/currentState_reg[2]_bret
core1/core/cores_37/backward/currentState_reg[2]_bret__3
core1/core/cores_37/backward/currentState_reg[3]_bret
core1/core/cores_37/backward/currentState_reg[3]_bret__3
core1/core/cores_37/backward/currentState_reg[4]_bret
core1/core/cores_37/backward/currentState_reg[4]_bret__3
core1/core/cores_37/backward/currentState_reg[5]_bret
core1/core/cores_37/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_37/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_37/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_37/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_37/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_37/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_37/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_37/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_37/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_37/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_37/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_37/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_37/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_37/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_37/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_37/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_37/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_37/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_37/backward/currentState_reg[5]_bret__3
core1/core/cores_38/backward/currentState_reg[0]_bret__0
core1/core/cores_38/backward/currentState_reg[0]_bret__1
core1/core/cores_38/backward/currentState_reg[0]_bret__4
core1/core/cores_38/backward/currentState_reg[0]_bret_bret
core1/core/cores_38/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_38/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_38/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_38/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_38/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_38/backward/currentState_reg[1]_bret
core1/core/cores_38/backward/currentState_reg[1]_bret__3
core1/core/cores_38/backward/currentState_reg[2]_bret
core1/core/cores_38/backward/currentState_reg[2]_bret__3
core1/core/cores_38/backward/currentState_reg[3]_bret
core1/core/cores_38/backward/currentState_reg[3]_bret__3
core1/core/cores_38/backward/currentState_reg[4]_bret
core1/core/cores_38/backward/currentState_reg[4]_bret__3
core1/core/cores_38/backward/currentState_reg[5]_bret
core1/core/cores_38/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_38/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_38/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_38/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_38/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_38/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_38/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_38/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_38/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_38/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_38/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_38/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_38/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_38/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_38/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_38/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_38/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_38/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_38/backward/currentState_reg[5]_bret__3
core1/core/cores_39/backward/currentState_reg[0]_bret__0
core1/core/cores_39/backward/currentState_reg[0]_bret__1
core1/core/cores_39/backward/currentState_reg[0]_bret__4
core1/core/cores_39/backward/currentState_reg[0]_bret_bret
core1/core/cores_39/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_39/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_39/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_39/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_39/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_39/backward/currentState_reg[1]_bret
core1/core/cores_39/backward/currentState_reg[1]_bret__3
core1/core/cores_39/backward/currentState_reg[2]_bret
core1/core/cores_39/backward/currentState_reg[2]_bret__3
core1/core/cores_39/backward/currentState_reg[3]_bret
core1/core/cores_39/backward/currentState_reg[3]_bret__3
core1/core/cores_39/backward/currentState_reg[4]_bret
core1/core/cores_39/backward/currentState_reg[4]_bret__3
core1/core/cores_39/backward/currentState_reg[5]_bret
core1/core/cores_39/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_39/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_39/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_39/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_39/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_39/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_39/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_39/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_39/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_39/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_39/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_39/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_39/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_39/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_39/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_39/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_39/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_39/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_39/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB4_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_39/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_39/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_39/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_39/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_38/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_38/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_38/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_38/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_37/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_37/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_37/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_37/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_36/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_36/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_36/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_36/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_35/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_35/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_35/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_35/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_34/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_34/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_34/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_10/core1/core/cores_34/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `anon_2__GB5_tempName`
Numbers of forward move = 0, and backward move = 90
Retimed registers names:
core1/core/cores_25/backward/currentState_reg[0]_bret__0
core1/core/cores_25/backward/currentState_reg[0]_bret__1
core1/core/cores_25/backward/currentState_reg[0]_bret__4
core1/core/cores_25/backward/currentState_reg[0]_bret_bret
core1/core/cores_25/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_25/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_25/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_25/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_25/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_25/backward/currentState_reg[1]_bret
core1/core/cores_25/backward/currentState_reg[1]_bret__3
core1/core/cores_25/backward/currentState_reg[2]_bret
core1/core/cores_25/backward/currentState_reg[2]_bret__3
core1/core/cores_25/backward/currentState_reg[3]_bret
core1/core/cores_25/backward/currentState_reg[3]_bret__3
core1/core/cores_25/backward/currentState_reg[4]_bret
core1/core/cores_25/backward/currentState_reg[4]_bret__3
core1/core/cores_25/backward/currentState_reg[5]_bret
core1/core/cores_25/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_25/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_25/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_25/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_25/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_25/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_25/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_25/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_25/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_25/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_25/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_25/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_25/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_25/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_25/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_25/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_25/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_25/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_25/backward/currentState_reg[5]_bret__3
core1/core/cores_27/backward/currentState_reg[0]_bret__0
core1/core/cores_27/backward/currentState_reg[0]_bret__1
core1/core/cores_27/backward/currentState_reg[0]_bret__4
core1/core/cores_27/backward/currentState_reg[0]_bret_bret
core1/core/cores_27/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_27/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_27/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_27/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_27/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_27/backward/currentState_reg[1]_bret
core1/core/cores_27/backward/currentState_reg[1]_bret__3
core1/core/cores_27/backward/currentState_reg[2]_bret
core1/core/cores_27/backward/currentState_reg[2]_bret__3
core1/core/cores_27/backward/currentState_reg[3]_bret
core1/core/cores_27/backward/currentState_reg[3]_bret__3
core1/core/cores_27/backward/currentState_reg[4]_bret
core1/core/cores_27/backward/currentState_reg[4]_bret__3
core1/core/cores_27/backward/currentState_reg[5]_bret
core1/core/cores_27/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_27/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_27/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_27/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_27/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_27/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_27/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_27/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_27/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_27/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_27/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_27/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_27/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_27/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_27/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_27/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_27/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_27/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_27/backward/currentState_reg[5]_bret__3
core1/core/cores_28/backward/currentState_reg[0]_bret__0
core1/core/cores_28/backward/currentState_reg[0]_bret__1
core1/core/cores_28/backward/currentState_reg[0]_bret__4
core1/core/cores_28/backward/currentState_reg[0]_bret_bret
core1/core/cores_28/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_28/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_28/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_28/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_28/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_28/backward/currentState_reg[1]_bret
core1/core/cores_28/backward/currentState_reg[1]_bret__3
core1/core/cores_28/backward/currentState_reg[2]_bret
core1/core/cores_28/backward/currentState_reg[2]_bret__3
core1/core/cores_28/backward/currentState_reg[3]_bret
core1/core/cores_28/backward/currentState_reg[3]_bret__3
core1/core/cores_28/backward/currentState_reg[4]_bret
core1/core/cores_28/backward/currentState_reg[4]_bret__3
core1/core/cores_28/backward/currentState_reg[5]_bret
core1/core/cores_28/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_28/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_28/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_28/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_28/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_28/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_28/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_28/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_28/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_28/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_28/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_28/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_28/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_28/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_28/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_28/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_28/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_28/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_28/backward/currentState_reg[5]_bret__3
core1/core/cores_29/backward/currentState_reg[0]_bret__0
core1/core/cores_29/backward/currentState_reg[0]_bret__1
core1/core/cores_29/backward/currentState_reg[0]_bret__4
core1/core/cores_29/backward/currentState_reg[0]_bret_bret
core1/core/cores_29/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_29/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_29/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_29/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_29/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_29/backward/currentState_reg[1]_bret
core1/core/cores_29/backward/currentState_reg[1]_bret__3
core1/core/cores_29/backward/currentState_reg[2]_bret
core1/core/cores_29/backward/currentState_reg[2]_bret__3
core1/core/cores_29/backward/currentState_reg[3]_bret
core1/core/cores_29/backward/currentState_reg[3]_bret__3
core1/core/cores_29/backward/currentState_reg[4]_bret
core1/core/cores_29/backward/currentState_reg[4]_bret__3
core1/core/cores_29/backward/currentState_reg[5]_bret
core1/core/cores_29/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_29/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_29/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_29/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_29/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_29/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_29/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_29/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_29/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_29/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_29/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_29/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_29/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_29/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_29/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_29/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_29/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_29/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_29/backward/currentState_reg[5]_bret__3
core1/core/cores_30/backward/currentState_reg[0]_bret__0
core1/core/cores_30/backward/currentState_reg[0]_bret__1
core1/core/cores_30/backward/currentState_reg[0]_bret__4
core1/core/cores_30/backward/currentState_reg[0]_bret_bret
core1/core/cores_30/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_30/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_30/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_30/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_30/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_30/backward/currentState_reg[1]_bret
core1/core/cores_30/backward/currentState_reg[1]_bret__3
core1/core/cores_30/backward/currentState_reg[2]_bret
core1/core/cores_30/backward/currentState_reg[2]_bret__3
core1/core/cores_30/backward/currentState_reg[3]_bret
core1/core/cores_30/backward/currentState_reg[3]_bret__3
core1/core/cores_30/backward/currentState_reg[4]_bret
core1/core/cores_30/backward/currentState_reg[4]_bret__3
core1/core/cores_30/backward/currentState_reg[5]_bret
core1/core/cores_30/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_30/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_30/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_30/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_30/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_30/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_30/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_30/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_30/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_30/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_30/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_30/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_30/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_30/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_30/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_30/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_30/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_30/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_30/backward/currentState_reg[5]_bret__3
core1/core/cores_31/backward/currentState_reg[0]_bret__0
core1/core/cores_31/backward/currentState_reg[0]_bret__1
core1/core/cores_31/backward/currentState_reg[0]_bret__4
core1/core/cores_31/backward/currentState_reg[0]_bret_bret
core1/core/cores_31/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_31/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_31/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_31/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_31/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_31/backward/currentState_reg[1]_bret
core1/core/cores_31/backward/currentState_reg[1]_bret__3
core1/core/cores_31/backward/currentState_reg[2]_bret
core1/core/cores_31/backward/currentState_reg[2]_bret__3
core1/core/cores_31/backward/currentState_reg[3]_bret
core1/core/cores_31/backward/currentState_reg[3]_bret__3
core1/core/cores_31/backward/currentState_reg[4]_bret
core1/core/cores_31/backward/currentState_reg[4]_bret__3
core1/core/cores_31/backward/currentState_reg[5]_bret
core1/core/cores_31/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_31/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_31/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_31/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_31/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_31/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_31/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_31/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_31/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_31/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_31/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_31/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_31/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_31/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_31/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_31/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_31/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_31/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_31/backward/currentState_reg[5]_bret__3
core1/core/cores_32/backward/currentState_reg[0]_bret__0
core1/core/cores_32/backward/currentState_reg[0]_bret__1
core1/core/cores_32/backward/currentState_reg[0]_bret__4
core1/core/cores_32/backward/currentState_reg[0]_bret_bret
core1/core/cores_32/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_32/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_32/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_32/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_32/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_32/backward/currentState_reg[1]_bret
core1/core/cores_32/backward/currentState_reg[1]_bret__3
core1/core/cores_32/backward/currentState_reg[2]_bret
core1/core/cores_32/backward/currentState_reg[2]_bret__3
core1/core/cores_32/backward/currentState_reg[3]_bret
core1/core/cores_32/backward/currentState_reg[3]_bret__3
core1/core/cores_32/backward/currentState_reg[4]_bret
core1/core/cores_32/backward/currentState_reg[4]_bret__3
core1/core/cores_32/backward/currentState_reg[5]_bret
core1/core/cores_32/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_32/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_32/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_32/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_32/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_32/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_32/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_32/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_32/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_32/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_32/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_32/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_32/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_32/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_32/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_32/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_32/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_32/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_32/backward/currentState_reg[5]_bret__3
core1/core/cores_33/backward/currentState_reg[0]_bret__0
core1/core/cores_33/backward/currentState_reg[0]_bret__1
core1/core/cores_33/backward/currentState_reg[0]_bret__4
core1/core/cores_33/backward/currentState_reg[0]_bret_bret
core1/core/cores_33/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_33/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_33/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_33/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_33/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_33/backward/currentState_reg[1]_bret
core1/core/cores_33/backward/currentState_reg[1]_bret__3
core1/core/cores_33/backward/currentState_reg[2]_bret
core1/core/cores_33/backward/currentState_reg[2]_bret__3
core1/core/cores_33/backward/currentState_reg[3]_bret
core1/core/cores_33/backward/currentState_reg[3]_bret__3
core1/core/cores_33/backward/currentState_reg[4]_bret
core1/core/cores_33/backward/currentState_reg[4]_bret__3
core1/core/cores_33/backward/currentState_reg[5]_bret
core1/core/cores_33/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_33/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_33/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_33/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_33/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_33/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_33/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_33/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_33/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_33/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_33/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_33/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_33/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_33/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_33/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_33/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_33/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_33/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_33/backward/currentState_reg[5]_bret__3
core1/core/cores_48/backward/currentState_reg[0]_bret__0
core1/core/cores_48/backward/currentState_reg[0]_bret__1
core1/core/cores_48/backward/currentState_reg[0]_bret__4
core1/core/cores_48/backward/currentState_reg[0]_bret_bret
core1/core/cores_48/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_48/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_48/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_48/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_48/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_48/backward/currentState_reg[1]_bret
core1/core/cores_48/backward/currentState_reg[1]_bret__3
core1/core/cores_48/backward/currentState_reg[2]_bret
core1/core/cores_48/backward/currentState_reg[2]_bret__3
core1/core/cores_48/backward/currentState_reg[3]_bret
core1/core/cores_48/backward/currentState_reg[3]_bret__3
core1/core/cores_48/backward/currentState_reg[4]_bret
core1/core/cores_48/backward/currentState_reg[4]_bret__3
core1/core/cores_48/backward/currentState_reg[5]_bret
core1/core/cores_48/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_48/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_48/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_48/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_48/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_48/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_48/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_48/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_48/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_48/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_48/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_48/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_48/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_48/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_48/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_48/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_48/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_48/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_48/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB5_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_48/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_48/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_48/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_48/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_33/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_33/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_33/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_33/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_32/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_32/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_32/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_32/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_31/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_31/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_31/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_31/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_30/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_30/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_30/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_30/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_29/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_29/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_29/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_29/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_28/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_28/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_28/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_28/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_27/recordStack_reg_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_27/recordStack_reg_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_27/recordStack_reg_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance corei_11/core1/core/cores_27/recordStack_reg_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `anon_2__GB6_tempName`
Numbers of forward move = 0, and backward move = 110
Retimed registers names:
core1/core/cores_15/backward/currentState_reg[0]_bret__0
core1/core/cores_15/backward/currentState_reg[0]_bret__1
core1/core/cores_15/backward/currentState_reg[0]_bret__4
core1/core/cores_15/backward/currentState_reg[0]_bret_bret
core1/core/cores_15/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_15/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_15/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_15/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_15/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_15/backward/currentState_reg[1]_bret
core1/core/cores_15/backward/currentState_reg[1]_bret__3
core1/core/cores_15/backward/currentState_reg[2]_bret
core1/core/cores_15/backward/currentState_reg[2]_bret__3
core1/core/cores_15/backward/currentState_reg[3]_bret
core1/core/cores_15/backward/currentState_reg[3]_bret__3
core1/core/cores_15/backward/currentState_reg[4]_bret
core1/core/cores_15/backward/currentState_reg[4]_bret__3
core1/core/cores_15/backward/currentState_reg[5]_bret
core1/core/cores_15/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_15/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_15/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_15/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_15/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_15/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_15/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_15/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_15/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_15/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_15/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_15/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_15/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_15/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_15/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_15/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_15/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_15/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_15/backward/currentState_reg[5]_bret__3
core1/core/cores_16/backward/currentState_reg[0]_bret__0
core1/core/cores_16/backward/currentState_reg[0]_bret__1
core1/core/cores_16/backward/currentState_reg[0]_bret__4
core1/core/cores_16/backward/currentState_reg[0]_bret_bret
core1/core/cores_16/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_16/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_16/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_16/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_16/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_16/backward/currentState_reg[1]_bret
core1/core/cores_16/backward/currentState_reg[1]_bret__3
core1/core/cores_16/backward/currentState_reg[2]_bret
core1/core/cores_16/backward/currentState_reg[2]_bret__3
core1/core/cores_16/backward/currentState_reg[3]_bret
core1/core/cores_16/backward/currentState_reg[3]_bret__3
core1/core/cores_16/backward/currentState_reg[4]_bret
core1/core/cores_16/backward/currentState_reg[4]_bret__3
core1/core/cores_16/backward/currentState_reg[5]_bret
core1/core/cores_16/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_16/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_16/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_16/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_16/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_16/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_16/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_16/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_16/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_16/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_16/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_16/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_16/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_16/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_16/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_16/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_16/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_16/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_16/backward/currentState_reg[5]_bret__3
core1/core/cores_17/backward/currentState_reg[0]_bret__0
core1/core/cores_17/backward/currentState_reg[0]_bret__1
core1/core/cores_17/backward/currentState_reg[0]_bret__4
core1/core/cores_17/backward/currentState_reg[0]_bret_bret
core1/core/cores_17/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_17/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_17/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_17/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_17/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_17/backward/currentState_reg[1]_bret
core1/core/cores_17/backward/currentState_reg[1]_bret__3
core1/core/cores_17/backward/currentState_reg[2]_bret
core1/core/cores_17/backward/currentState_reg[2]_bret__3
core1/core/cores_17/backward/currentState_reg[3]_bret
core1/core/cores_17/backward/currentState_reg[3]_bret__3
core1/core/cores_17/backward/currentState_reg[4]_bret
core1/core/cores_17/backward/currentState_reg[4]_bret__3
core1/core/cores_17/backward/currentState_reg[5]_bret
core1/core/cores_17/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_17/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_17/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_17/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_17/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_17/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_17/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_17/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_17/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_17/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_17/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_17/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_17/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_17/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_17/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_17/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_17/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_17/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_17/backward/currentState_reg[5]_bret__3
core1/core/cores_18/backward/currentState_reg[0]_bret__0
core1/core/cores_18/backward/currentState_reg[0]_bret__1
core1/core/cores_18/backward/currentState_reg[0]_bret__4
core1/core/cores_18/backward/currentState_reg[0]_bret_bret
core1/core/cores_18/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_18/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_18/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_18/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_18/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_18/backward/currentState_reg[1]_bret
core1/core/cores_18/backward/currentState_reg[1]_bret__3
core1/core/cores_18/backward/currentState_reg[2]_bret
core1/core/cores_18/backward/currentState_reg[2]_bret__3
core1/core/cores_18/backward/currentState_reg[3]_bret
core1/core/cores_18/backward/currentState_reg[3]_bret__3
core1/core/cores_18/backward/currentState_reg[4]_bret
core1/core/cores_18/backward/currentState_reg[4]_bret__3
core1/core/cores_18/backward/currentState_reg[5]_bret
core1/core/cores_18/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_18/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_18/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_18/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_18/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_18/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_18/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_18/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_18/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_18/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_18/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_18/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_18/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_18/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_18/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_18/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_18/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_18/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_18/backward/currentState_reg[5]_bret__3
core1/core/cores_19/backward/currentState_reg[0]_bret__0
core1/core/cores_19/backward/currentState_reg[0]_bret__1
core1/core/cores_19/backward/currentState_reg[0]_bret__4
core1/core/cores_19/backward/currentState_reg[0]_bret_bret
core1/core/cores_19/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_19/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_19/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_19/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_19/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_19/backward/currentState_reg[1]_bret
core1/core/cores_19/backward/currentState_reg[1]_bret__3
core1/core/cores_19/backward/currentState_reg[2]_bret
core1/core/cores_19/backward/currentState_reg[2]_bret__3
core1/core/cores_19/backward/currentState_reg[3]_bret
core1/core/cores_19/backward/currentState_reg[3]_bret__3
core1/core/cores_19/backward/currentState_reg[4]_bret
core1/core/cores_19/backward/currentState_reg[4]_bret__3
core1/core/cores_19/backward/currentState_reg[5]_bret
core1/core/cores_19/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_19/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_19/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_19/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_19/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_19/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_19/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_19/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_19/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_19/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_19/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_19/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_19/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_19/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_19/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_19/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_19/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_19/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_19/backward/currentState_reg[5]_bret__3
core1/core/cores_20/backward/currentState_reg[0]_bret__0
core1/core/cores_20/backward/currentState_reg[0]_bret__1
core1/core/cores_20/backward/currentState_reg[0]_bret__4
core1/core/cores_20/backward/currentState_reg[0]_bret_bret
core1/core/cores_20/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_20/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_20/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_20/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_20/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_20/backward/currentState_reg[1]_bret
core1/core/cores_20/backward/currentState_reg[1]_bret__3
core1/core/cores_20/backward/currentState_reg[2]_bret
core1/core/cores_20/backward/currentState_reg[2]_bret__3
core1/core/cores_20/backward/currentState_reg[3]_bret
core1/core/cores_20/backward/currentState_reg[3]_bret__3
core1/core/cores_20/backward/currentState_reg[4]_bret
core1/core/cores_20/backward/currentState_reg[4]_bret__3
core1/core/cores_20/backward/currentState_reg[5]_bret
core1/core/cores_20/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_20/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_20/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_20/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_20/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_20/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_20/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_20/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_20/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_20/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_20/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_20/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_20/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_20/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_20/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_20/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_20/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_20/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_20/backward/currentState_reg[5]_bret__3
core1/core/cores_21/backward/currentState_reg[0]_bret__0
core1/core/cores_21/backward/currentState_reg[0]_bret__1
core1/core/cores_21/backward/currentState_reg[0]_bret__4
core1/core/cores_21/backward/currentState_reg[0]_bret_bret
core1/core/cores_21/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_21/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_21/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_21/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_21/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_21/backward/currentState_reg[1]_bret
core1/core/cores_21/backward/currentState_reg[1]_bret__3
core1/core/cores_21/backward/currentState_reg[2]_bret
core1/core/cores_21/backward/currentState_reg[2]_bret__3
core1/core/cores_21/backward/currentState_reg[3]_bret
core1/core/cores_21/backward/currentState_reg[3]_bret__3
core1/core/cores_21/backward/currentState_reg[4]_bret
core1/core/cores_21/backward/currentState_reg[4]_bret__3
core1/core/cores_21/backward/currentState_reg[5]_bret
core1/core/cores_21/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_21/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_21/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_21/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_21/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_21/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_21/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_21/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_21/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_21/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_21/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_21/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_21/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_21/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_21/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_21/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_21/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_21/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_21/backward/currentState_reg[5]_bret__3
core1/core/cores_22/backward/currentState_reg[0]_bret__0
core1/core/cores_22/backward/currentState_reg[0]_bret__1
core1/core/cores_22/backward/currentState_reg[0]_bret__4
core1/core/cores_22/backward/currentState_reg[0]_bret_bret
core1/core/cores_22/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_22/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_22/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_22/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_22/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_22/backward/currentState_reg[1]_bret
core1/core/cores_22/backward/currentState_reg[1]_bret__3
core1/core/cores_22/backward/currentState_reg[2]_bret
core1/core/cores_22/backward/currentState_reg[2]_bret__3
core1/core/cores_22/backward/currentState_reg[3]_bret
core1/core/cores_22/backward/currentState_reg[3]_bret__3
core1/core/cores_22/backward/currentState_reg[4]_bret
core1/core/cores_22/backward/currentState_reg[4]_bret__3
core1/core/cores_22/backward/currentState_reg[5]_bret
core1/core/cores_22/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_22/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_22/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_22/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_22/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_22/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_22/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_22/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_22/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_22/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_22/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_22/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_22/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_22/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_22/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_22/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_22/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_22/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_22/backward/currentState_reg[5]_bret__3
core1/core/cores_23/backward/currentState_reg[0]_bret__0
core1/core/cores_23/backward/currentState_reg[0]_bret__1
core1/core/cores_23/backward/currentState_reg[0]_bret__4
core1/core/cores_23/backward/currentState_reg[0]_bret_bret
core1/core/cores_23/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_23/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_23/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_23/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_23/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_23/backward/currentState_reg[1]_bret
core1/core/cores_23/backward/currentState_reg[1]_bret__3
core1/core/cores_23/backward/currentState_reg[2]_bret
core1/core/cores_23/backward/currentState_reg[2]_bret__3
core1/core/cores_23/backward/currentState_reg[3]_bret
core1/core/cores_23/backward/currentState_reg[3]_bret__3
core1/core/cores_23/backward/currentState_reg[4]_bret
core1/core/cores_23/backward/currentState_reg[4]_bret__3
core1/core/cores_23/backward/currentState_reg[5]_bret
core1/core/cores_23/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_23/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_23/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_23/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_23/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_23/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_23/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_23/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_23/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_23/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_23/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_23/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_23/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_23/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_23/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_23/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_23/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_23/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_23/backward/currentState_reg[5]_bret__3
core1/core/cores_24/backward/currentState_reg[0]_bret__0
core1/core/cores_24/backward/currentState_reg[0]_bret__1
core1/core/cores_24/backward/currentState_reg[0]_bret__4
core1/core/cores_24/backward/currentState_reg[0]_bret_bret
core1/core/cores_24/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_24/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_24/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_24/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_24/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_24/backward/currentState_reg[1]_bret
core1/core/cores_24/backward/currentState_reg[1]_bret__3
core1/core/cores_24/backward/currentState_reg[2]_bret
core1/core/cores_24/backward/currentState_reg[2]_bret__3
core1/core/cores_24/backward/currentState_reg[3]_bret
core1/core/cores_24/backward/currentState_reg[3]_bret__3
core1/core/cores_24/backward/currentState_reg[4]_bret
core1/core/cores_24/backward/currentState_reg[4]_bret__3
core1/core/cores_24/backward/currentState_reg[5]_bret
core1/core/cores_24/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_24/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_24/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_24/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_24/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_24/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_24/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_24/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_24/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_24/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_24/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_24/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_24/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_24/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_24/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_24/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_24/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_24/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_24/backward/currentState_reg[5]_bret__3
core1/core/cores_26/backward/currentState_reg[0]_bret__0
core1/core/cores_26/backward/currentState_reg[0]_bret__1
core1/core/cores_26/backward/currentState_reg[0]_bret__4
core1/core/cores_26/backward/currentState_reg[0]_bret_bret
core1/core/cores_26/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_26/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_26/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_26/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_26/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_26/backward/currentState_reg[1]_bret
core1/core/cores_26/backward/currentState_reg[1]_bret__3
core1/core/cores_26/backward/currentState_reg[2]_bret
core1/core/cores_26/backward/currentState_reg[2]_bret__3
core1/core/cores_26/backward/currentState_reg[3]_bret
core1/core/cores_26/backward/currentState_reg[3]_bret__3
core1/core/cores_26/backward/currentState_reg[4]_bret
core1/core/cores_26/backward/currentState_reg[4]_bret__3
core1/core/cores_26/backward/currentState_reg[5]_bret
core1/core/cores_26/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_26/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_26/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_26/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_26/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_26/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_26/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_26/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_26/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_26/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_26/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_26/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_26/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_26/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_26/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_26/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_26/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_26/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_26/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB6_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `anon_2__GB7_tempName`
Numbers of forward move = 0, and backward move = 90
Retimed registers names:
core1/core/cores_10/backward/currentState_reg[0]_bret__0
core1/core/cores_10/backward/currentState_reg[0]_bret__1
core1/core/cores_10/backward/currentState_reg[0]_bret__4
core1/core/cores_10/backward/currentState_reg[0]_bret_bret
core1/core/cores_10/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_10/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_10/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_10/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_10/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_10/backward/currentState_reg[1]_bret
core1/core/cores_10/backward/currentState_reg[1]_bret__3
core1/core/cores_10/backward/currentState_reg[2]_bret
core1/core/cores_10/backward/currentState_reg[2]_bret__3
core1/core/cores_10/backward/currentState_reg[3]_bret
core1/core/cores_10/backward/currentState_reg[3]_bret__3
core1/core/cores_10/backward/currentState_reg[4]_bret
core1/core/cores_10/backward/currentState_reg[4]_bret__3
core1/core/cores_10/backward/currentState_reg[5]_bret
core1/core/cores_10/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_10/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_10/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_10/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_10/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_10/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_10/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_10/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_10/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_10/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_10/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_10/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_10/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_10/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_10/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_10/backward/currentState_reg[5]_bret__2_bret__2
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core1/core/cores_9/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB7_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB8_tempName`
Numbers of forward move = 0, and backward move = 30
Retimed registers names:
core1/core/cores_2/backward/currentState_reg[0]_bret__0
core1/core/cores_2/backward/currentState_reg[0]_bret__1
core1/core/cores_2/backward/currentState_reg[0]_bret__4
core1/core/cores_2/backward/currentState_reg[0]_bret_bret
core1/core/cores_2/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_2/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_2/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_2/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_2/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_2/backward/currentState_reg[1]_bret
core1/core/cores_2/backward/currentState_reg[1]_bret__3
core1/core/cores_2/backward/currentState_reg[2]_bret
core1/core/cores_2/backward/currentState_reg[2]_bret__3
core1/core/cores_2/backward/currentState_reg[3]_bret
core1/core/cores_2/backward/currentState_reg[3]_bret__3
core1/core/cores_2/backward/currentState_reg[4]_bret
core1/core/cores_2/backward/currentState_reg[4]_bret__3
core1/core/cores_2/backward/currentState_reg[5]_bret
core1/core/cores_2/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_2/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_2/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_2/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_2/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_2/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_2/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_2/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_2/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_2/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_2/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_2/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_2/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_2/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_2/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_2/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_2/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_2/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_2/backward/currentState_reg[5]_bret__3
core1/core/cores_3/backward/currentState_reg[0]_bret__0
core1/core/cores_3/backward/currentState_reg[0]_bret__1
core1/core/cores_3/backward/currentState_reg[0]_bret__4
core1/core/cores_3/backward/currentState_reg[0]_bret_bret
core1/core/cores_3/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_3/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_3/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_3/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_3/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_3/backward/currentState_reg[1]_bret
core1/core/cores_3/backward/currentState_reg[1]_bret__3
core1/core/cores_3/backward/currentState_reg[2]_bret
core1/core/cores_3/backward/currentState_reg[2]_bret__3
core1/core/cores_3/backward/currentState_reg[3]_bret
core1/core/cores_3/backward/currentState_reg[3]_bret__3
core1/core/cores_3/backward/currentState_reg[4]_bret
core1/core/cores_3/backward/currentState_reg[4]_bret__3
core1/core/cores_3/backward/currentState_reg[5]_bret
core1/core/cores_3/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_3/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_3/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_3/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_3/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_3/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_3/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_3/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_3/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_3/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_3/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_3/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_3/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_3/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_3/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_3/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_3/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_3/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_3/backward/currentState_reg[5]_bret__3
core1/core/cores_5/backward/currentState_reg[0]_bret__0
core1/core/cores_5/backward/currentState_reg[0]_bret__1
core1/core/cores_5/backward/currentState_reg[0]_bret__4
core1/core/cores_5/backward/currentState_reg[0]_bret_bret
core1/core/cores_5/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_5/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_5/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_5/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_5/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_5/backward/currentState_reg[1]_bret
core1/core/cores_5/backward/currentState_reg[1]_bret__3
core1/core/cores_5/backward/currentState_reg[2]_bret
core1/core/cores_5/backward/currentState_reg[2]_bret__3
core1/core/cores_5/backward/currentState_reg[3]_bret
core1/core/cores_5/backward/currentState_reg[3]_bret__3
core1/core/cores_5/backward/currentState_reg[4]_bret
core1/core/cores_5/backward/currentState_reg[4]_bret__3
core1/core/cores_5/backward/currentState_reg[5]_bret
core1/core/cores_5/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_5/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_5/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_5/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_5/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_5/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_5/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_5/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_5/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_5/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_5/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_5/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_5/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_5/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_5/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_5/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_5/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_5/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_5/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB8_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB9_tempName`
Numbers of forward move = 0, and backward move = 30
Retimed registers names:
core1/core/cores_0/backward/currentState_reg[0]_bret__0
core1/core/cores_0/backward/currentState_reg[0]_bret__1
core1/core/cores_0/backward/currentState_reg[0]_bret__4
core1/core/cores_0/backward/currentState_reg[0]_bret_bret
core1/core/cores_0/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_0/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_0/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_0/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_0/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_0/backward/currentState_reg[1]_bret
core1/core/cores_0/backward/currentState_reg[1]_bret__3
core1/core/cores_0/backward/currentState_reg[2]_bret
core1/core/cores_0/backward/currentState_reg[2]_bret__3
core1/core/cores_0/backward/currentState_reg[3]_bret
core1/core/cores_0/backward/currentState_reg[3]_bret__3
core1/core/cores_0/backward/currentState_reg[4]_bret
core1/core/cores_0/backward/currentState_reg[4]_bret__3
core1/core/cores_0/backward/currentState_reg[5]_bret
core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_0/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_0/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_0/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_0/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_0/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_0/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_0/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_0/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_0/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_0/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_0/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_0/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_0/backward/currentState_reg[5]_bret__3
core1/core/cores_1/backward/currentState_reg[0]_bret__0
core1/core/cores_1/backward/currentState_reg[0]_bret__1
core1/core/cores_1/backward/currentState_reg[0]_bret__4
core1/core/cores_1/backward/currentState_reg[0]_bret_bret
core1/core/cores_1/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_1/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_1/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_1/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_1/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_1/backward/currentState_reg[1]_bret
core1/core/cores_1/backward/currentState_reg[1]_bret__3
core1/core/cores_1/backward/currentState_reg[2]_bret
core1/core/cores_1/backward/currentState_reg[2]_bret__3
core1/core/cores_1/backward/currentState_reg[3]_bret
core1/core/cores_1/backward/currentState_reg[3]_bret__3
core1/core/cores_1/backward/currentState_reg[4]_bret
core1/core/cores_1/backward/currentState_reg[4]_bret__3
core1/core/cores_1/backward/currentState_reg[5]_bret
core1/core/cores_1/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_1/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_1/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_1/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_1/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_1/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_1/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_1/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_1/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_1/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_1/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_1/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_1/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_1/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_1/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_1/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_1/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_1/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_1/backward/currentState_reg[5]_bret__3
core1/core/cores_4/backward/currentState_reg[0]_bret__0
core1/core/cores_4/backward/currentState_reg[0]_bret__1
core1/core/cores_4/backward/currentState_reg[0]_bret__4
core1/core/cores_4/backward/currentState_reg[0]_bret_bret
core1/core/cores_4/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_4/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_4/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_4/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_4/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_4/backward/currentState_reg[1]_bret
core1/core/cores_4/backward/currentState_reg[1]_bret__3
core1/core/cores_4/backward/currentState_reg[2]_bret
core1/core/cores_4/backward/currentState_reg[2]_bret__3
core1/core/cores_4/backward/currentState_reg[3]_bret
core1/core/cores_4/backward/currentState_reg[3]_bret__3
core1/core/cores_4/backward/currentState_reg[4]_bret
core1/core/cores_4/backward/currentState_reg[4]_bret__3
core1/core/cores_4/backward/currentState_reg[5]_bret
core1/core/cores_4/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_4/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_4/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_4/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_4/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_4/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_4/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_4/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_4/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_4/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_4/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_4/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_4/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_4/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_4/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_4/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_4/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_4/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_4/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB9_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB10_tempName`
Numbers of forward move = 0, and backward move = 110
Retimed registers names:
core1/core/cores_110/backward/currentState_reg[0]_bret__0
core1/core/cores_110/backward/currentState_reg[0]_bret__1
core1/core/cores_110/backward/currentState_reg[0]_bret__4
core1/core/cores_110/backward/currentState_reg[0]_bret_bret
core1/core/cores_110/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_110/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_110/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_110/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_110/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_110/backward/currentState_reg[1]_bret
core1/core/cores_110/backward/currentState_reg[1]_bret__3
core1/core/cores_110/backward/currentState_reg[2]_bret
core1/core/cores_110/backward/currentState_reg[2]_bret__3
core1/core/cores_110/backward/currentState_reg[3]_bret
core1/core/cores_110/backward/currentState_reg[3]_bret__3
core1/core/cores_110/backward/currentState_reg[4]_bret
core1/core/cores_110/backward/currentState_reg[4]_bret__3
core1/core/cores_110/backward/currentState_reg[5]_bret
core1/core/cores_110/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_110/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_110/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_110/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_110/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_110/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_110/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_110/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_110/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_110/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_110/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_110/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_110/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_110/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_110/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_110/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_110/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_110/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_110/backward/currentState_reg[5]_bret__3
core1/core/cores_112/backward/currentState_reg[0]_bret__0
core1/core/cores_112/backward/currentState_reg[0]_bret__1
core1/core/cores_112/backward/currentState_reg[0]_bret__4
core1/core/cores_112/backward/currentState_reg[0]_bret_bret
core1/core/cores_112/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_112/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_112/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_112/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_112/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_112/backward/currentState_reg[1]_bret
core1/core/cores_112/backward/currentState_reg[1]_bret__3
core1/core/cores_112/backward/currentState_reg[2]_bret
core1/core/cores_112/backward/currentState_reg[2]_bret__3
core1/core/cores_112/backward/currentState_reg[3]_bret
core1/core/cores_112/backward/currentState_reg[3]_bret__3
core1/core/cores_112/backward/currentState_reg[4]_bret
core1/core/cores_112/backward/currentState_reg[4]_bret__3
core1/core/cores_112/backward/currentState_reg[5]_bret
core1/core/cores_112/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_112/backward/currentState_reg[5]_bret__0_bret__0
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core1/core/cores_121/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_121/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_121/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_121/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_121/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_121/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_121/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_121/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_121/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_121/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_121/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_121/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_121/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_121/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_121/backward/currentState_reg[5]_bret__3
core1/core/cores_123/backward/currentState_reg[0]_bret__0
core1/core/cores_123/backward/currentState_reg[0]_bret__1
core1/core/cores_123/backward/currentState_reg[0]_bret__4
core1/core/cores_123/backward/currentState_reg[0]_bret_bret
core1/core/cores_123/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_123/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_123/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_123/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_123/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_123/backward/currentState_reg[1]_bret
core1/core/cores_123/backward/currentState_reg[1]_bret__3
core1/core/cores_123/backward/currentState_reg[2]_bret
core1/core/cores_123/backward/currentState_reg[2]_bret__3
core1/core/cores_123/backward/currentState_reg[3]_bret
core1/core/cores_123/backward/currentState_reg[3]_bret__3
core1/core/cores_123/backward/currentState_reg[4]_bret
core1/core/cores_123/backward/currentState_reg[4]_bret__3
core1/core/cores_123/backward/currentState_reg[5]_bret
core1/core/cores_123/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_123/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_123/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_123/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_123/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_123/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_123/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_123/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_123/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_123/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_123/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_123/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_123/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_123/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_123/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_123/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_123/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_123/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_123/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB10_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `anon_2__GB11_tempName`
Numbers of forward move = 0, and backward move = 30
Retimed registers names:
core1/core/cores_108/backward/currentState_reg[0]_bret__0
core1/core/cores_108/backward/currentState_reg[0]_bret__1
core1/core/cores_108/backward/currentState_reg[0]_bret__4
core1/core/cores_108/backward/currentState_reg[0]_bret_bret
core1/core/cores_108/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_108/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_108/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_108/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_108/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_108/backward/currentState_reg[1]_bret
core1/core/cores_108/backward/currentState_reg[1]_bret__3
core1/core/cores_108/backward/currentState_reg[2]_bret
core1/core/cores_108/backward/currentState_reg[2]_bret__3
core1/core/cores_108/backward/currentState_reg[3]_bret
core1/core/cores_108/backward/currentState_reg[3]_bret__3
core1/core/cores_108/backward/currentState_reg[4]_bret
core1/core/cores_108/backward/currentState_reg[4]_bret__3
core1/core/cores_108/backward/currentState_reg[5]_bret
core1/core/cores_108/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_108/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_108/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_108/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_108/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_108/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_108/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_108/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_108/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_108/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_108/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_108/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_108/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_108/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_108/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_108/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_108/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_108/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_108/backward/currentState_reg[5]_bret__3
core1/core/cores_109/backward/currentState_reg[0]_bret__0
core1/core/cores_109/backward/currentState_reg[0]_bret__1
core1/core/cores_109/backward/currentState_reg[0]_bret__4
core1/core/cores_109/backward/currentState_reg[0]_bret_bret
core1/core/cores_109/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_109/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_109/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_109/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_109/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_109/backward/currentState_reg[1]_bret
core1/core/cores_109/backward/currentState_reg[1]_bret__3
core1/core/cores_109/backward/currentState_reg[2]_bret
core1/core/cores_109/backward/currentState_reg[2]_bret__3
core1/core/cores_109/backward/currentState_reg[3]_bret
core1/core/cores_109/backward/currentState_reg[3]_bret__3
core1/core/cores_109/backward/currentState_reg[4]_bret
core1/core/cores_109/backward/currentState_reg[4]_bret__3
core1/core/cores_109/backward/currentState_reg[5]_bret
core1/core/cores_109/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_109/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_109/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_109/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_109/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_109/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_109/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_109/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_109/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_109/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_109/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_109/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_109/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_109/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_109/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_109/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_109/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_109/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_109/backward/currentState_reg[5]_bret__3
core1/core/cores_114/backward/currentState_reg[0]_bret__0
core1/core/cores_114/backward/currentState_reg[0]_bret__1
core1/core/cores_114/backward/currentState_reg[0]_bret__4
core1/core/cores_114/backward/currentState_reg[0]_bret_bret
core1/core/cores_114/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_114/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_114/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_114/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_114/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_114/backward/currentState_reg[1]_bret
core1/core/cores_114/backward/currentState_reg[1]_bret__3
core1/core/cores_114/backward/currentState_reg[2]_bret
core1/core/cores_114/backward/currentState_reg[2]_bret__3
core1/core/cores_114/backward/currentState_reg[3]_bret
core1/core/cores_114/backward/currentState_reg[3]_bret__3
core1/core/cores_114/backward/currentState_reg[4]_bret
core1/core/cores_114/backward/currentState_reg[4]_bret__3
core1/core/cores_114/backward/currentState_reg[5]_bret
core1/core/cores_114/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_114/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_114/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_114/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_114/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_114/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_114/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_114/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_114/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_114/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_114/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_114/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_114/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_114/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_114/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_114/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_114/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_114/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_114/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB11_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB12_tempName`
Numbers of forward move = 0, and backward move = 40
Retimed registers names:
core1/core/cores_105/backward/currentState_reg[0]_bret__0
core1/core/cores_105/backward/currentState_reg[0]_bret__1
core1/core/cores_105/backward/currentState_reg[0]_bret__4
core1/core/cores_105/backward/currentState_reg[0]_bret_bret
core1/core/cores_105/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_105/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_105/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_105/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_105/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_105/backward/currentState_reg[1]_bret
core1/core/cores_105/backward/currentState_reg[1]_bret__3
core1/core/cores_105/backward/currentState_reg[2]_bret
core1/core/cores_105/backward/currentState_reg[2]_bret__3
core1/core/cores_105/backward/currentState_reg[3]_bret
core1/core/cores_105/backward/currentState_reg[3]_bret__3
core1/core/cores_105/backward/currentState_reg[4]_bret
core1/core/cores_105/backward/currentState_reg[4]_bret__3
core1/core/cores_105/backward/currentState_reg[5]_bret
core1/core/cores_105/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_105/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_105/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_105/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_105/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_105/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_105/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_105/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_105/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_105/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_105/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_105/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_105/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_105/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_105/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_105/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_105/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_105/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_105/backward/currentState_reg[5]_bret__3
core1/core/cores_106/backward/currentState_reg[0]_bret__0
core1/core/cores_106/backward/currentState_reg[0]_bret__1
core1/core/cores_106/backward/currentState_reg[0]_bret__4
core1/core/cores_106/backward/currentState_reg[0]_bret_bret
core1/core/cores_106/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_106/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_106/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_106/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_106/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_106/backward/currentState_reg[1]_bret
core1/core/cores_106/backward/currentState_reg[1]_bret__3
core1/core/cores_106/backward/currentState_reg[2]_bret
core1/core/cores_106/backward/currentState_reg[2]_bret__3
core1/core/cores_106/backward/currentState_reg[3]_bret
core1/core/cores_106/backward/currentState_reg[3]_bret__3
core1/core/cores_106/backward/currentState_reg[4]_bret
core1/core/cores_106/backward/currentState_reg[4]_bret__3
core1/core/cores_106/backward/currentState_reg[5]_bret
core1/core/cores_106/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_106/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_106/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_106/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_106/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_106/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_106/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_106/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_106/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_106/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_106/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_106/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_106/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_106/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_106/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_106/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_106/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_106/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_106/backward/currentState_reg[5]_bret__3
core1/core/cores_107/backward/currentState_reg[0]_bret__0
core1/core/cores_107/backward/currentState_reg[0]_bret__1
core1/core/cores_107/backward/currentState_reg[0]_bret__4
core1/core/cores_107/backward/currentState_reg[0]_bret_bret
core1/core/cores_107/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_107/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_107/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_107/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_107/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_107/backward/currentState_reg[1]_bret
core1/core/cores_107/backward/currentState_reg[1]_bret__3
core1/core/cores_107/backward/currentState_reg[2]_bret
core1/core/cores_107/backward/currentState_reg[2]_bret__3
core1/core/cores_107/backward/currentState_reg[3]_bret
core1/core/cores_107/backward/currentState_reg[3]_bret__3
core1/core/cores_107/backward/currentState_reg[4]_bret
core1/core/cores_107/backward/currentState_reg[4]_bret__3
core1/core/cores_107/backward/currentState_reg[5]_bret
core1/core/cores_107/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_107/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_107/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_107/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_107/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_107/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_107/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_107/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_107/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_107/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_107/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_107/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_107/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_107/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_107/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_107/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_107/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_107/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_107/backward/currentState_reg[5]_bret__3
core1/core/cores_111/backward/currentState_reg[0]_bret__0
core1/core/cores_111/backward/currentState_reg[0]_bret__1
core1/core/cores_111/backward/currentState_reg[0]_bret__4
core1/core/cores_111/backward/currentState_reg[0]_bret_bret
core1/core/cores_111/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_111/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_111/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_111/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_111/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_111/backward/currentState_reg[1]_bret
core1/core/cores_111/backward/currentState_reg[1]_bret__3
core1/core/cores_111/backward/currentState_reg[2]_bret
core1/core/cores_111/backward/currentState_reg[2]_bret__3
core1/core/cores_111/backward/currentState_reg[3]_bret
core1/core/cores_111/backward/currentState_reg[3]_bret__3
core1/core/cores_111/backward/currentState_reg[4]_bret
core1/core/cores_111/backward/currentState_reg[4]_bret__3
core1/core/cores_111/backward/currentState_reg[5]_bret
core1/core/cores_111/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_111/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_111/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_111/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_111/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_111/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_111/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_111/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_111/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_111/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_111/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_111/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_111/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_111/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_111/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_111/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_111/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_111/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_111/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB12_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `anon_2__GB13_tempName`
Numbers of forward move = 0, and backward move = 50
Retimed registers names:
core1/core/cores_100/backward/currentState_reg[0]_bret__0
core1/core/cores_100/backward/currentState_reg[0]_bret__1
core1/core/cores_100/backward/currentState_reg[0]_bret__4
core1/core/cores_100/backward/currentState_reg[0]_bret_bret
core1/core/cores_100/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_100/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_100/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_100/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_100/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_100/backward/currentState_reg[1]_bret
core1/core/cores_100/backward/currentState_reg[1]_bret__3
core1/core/cores_100/backward/currentState_reg[2]_bret
core1/core/cores_100/backward/currentState_reg[2]_bret__3
core1/core/cores_100/backward/currentState_reg[3]_bret
core1/core/cores_100/backward/currentState_reg[3]_bret__3
core1/core/cores_100/backward/currentState_reg[4]_bret
core1/core/cores_100/backward/currentState_reg[4]_bret__3
core1/core/cores_100/backward/currentState_reg[5]_bret
core1/core/cores_100/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_100/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_100/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_100/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_100/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_100/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_100/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_100/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_100/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_100/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_100/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_100/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_100/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_100/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_100/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_100/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_100/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_100/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_100/backward/currentState_reg[5]_bret__3
core1/core/cores_101/backward/currentState_reg[0]_bret__0
core1/core/cores_101/backward/currentState_reg[0]_bret__1
core1/core/cores_101/backward/currentState_reg[0]_bret__4
core1/core/cores_101/backward/currentState_reg[0]_bret_bret
core1/core/cores_101/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_101/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_101/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_101/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_101/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_101/backward/currentState_reg[1]_bret
core1/core/cores_101/backward/currentState_reg[1]_bret__3
core1/core/cores_101/backward/currentState_reg[2]_bret
core1/core/cores_101/backward/currentState_reg[2]_bret__3
core1/core/cores_101/backward/currentState_reg[3]_bret
core1/core/cores_101/backward/currentState_reg[3]_bret__3
core1/core/cores_101/backward/currentState_reg[4]_bret
core1/core/cores_101/backward/currentState_reg[4]_bret__3
core1/core/cores_101/backward/currentState_reg[5]_bret
core1/core/cores_101/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_101/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_101/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_101/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_101/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_101/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_101/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_101/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_101/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_101/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_101/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_101/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_101/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_101/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_101/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_101/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_101/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_101/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_101/backward/currentState_reg[5]_bret__3
core1/core/cores_102/backward/currentState_reg[0]_bret__0
core1/core/cores_102/backward/currentState_reg[0]_bret__1
core1/core/cores_102/backward/currentState_reg[0]_bret__4
core1/core/cores_102/backward/currentState_reg[0]_bret_bret
core1/core/cores_102/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_102/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_102/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_102/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_102/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_102/backward/currentState_reg[1]_bret
core1/core/cores_102/backward/currentState_reg[1]_bret__3
core1/core/cores_102/backward/currentState_reg[2]_bret
core1/core/cores_102/backward/currentState_reg[2]_bret__3
core1/core/cores_102/backward/currentState_reg[3]_bret
core1/core/cores_102/backward/currentState_reg[3]_bret__3
core1/core/cores_102/backward/currentState_reg[4]_bret
core1/core/cores_102/backward/currentState_reg[4]_bret__3
core1/core/cores_102/backward/currentState_reg[5]_bret
core1/core/cores_102/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_102/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_102/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_102/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_102/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_102/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_102/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_102/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_102/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_102/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_102/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_102/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_102/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_102/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_102/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_102/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_102/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_102/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_102/backward/currentState_reg[5]_bret__3
core1/core/cores_103/backward/currentState_reg[0]_bret__0
core1/core/cores_103/backward/currentState_reg[0]_bret__1
core1/core/cores_103/backward/currentState_reg[0]_bret__4
core1/core/cores_103/backward/currentState_reg[0]_bret_bret
core1/core/cores_103/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_103/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_103/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_103/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_103/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_103/backward/currentState_reg[1]_bret
core1/core/cores_103/backward/currentState_reg[1]_bret__3
core1/core/cores_103/backward/currentState_reg[2]_bret
core1/core/cores_103/backward/currentState_reg[2]_bret__3
core1/core/cores_103/backward/currentState_reg[3]_bret
core1/core/cores_103/backward/currentState_reg[3]_bret__3
core1/core/cores_103/backward/currentState_reg[4]_bret
core1/core/cores_103/backward/currentState_reg[4]_bret__3
core1/core/cores_103/backward/currentState_reg[5]_bret
core1/core/cores_103/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_103/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_103/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_103/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_103/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_103/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_103/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_103/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_103/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_103/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_103/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_103/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_103/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_103/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_103/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_103/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_103/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_103/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_103/backward/currentState_reg[5]_bret__3
core1/core/cores_122/backward/currentState_reg[0]_bret__0
core1/core/cores_122/backward/currentState_reg[0]_bret__1
core1/core/cores_122/backward/currentState_reg[0]_bret__4
core1/core/cores_122/backward/currentState_reg[0]_bret_bret
core1/core/cores_122/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_122/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_122/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_122/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_122/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_122/backward/currentState_reg[1]_bret
core1/core/cores_122/backward/currentState_reg[1]_bret__3
core1/core/cores_122/backward/currentState_reg[2]_bret
core1/core/cores_122/backward/currentState_reg[2]_bret__3
core1/core/cores_122/backward/currentState_reg[3]_bret
core1/core/cores_122/backward/currentState_reg[3]_bret__3
core1/core/cores_122/backward/currentState_reg[4]_bret
core1/core/cores_122/backward/currentState_reg[4]_bret__3
core1/core/cores_122/backward/currentState_reg[5]_bret
core1/core/cores_122/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_122/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_122/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_122/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_122/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_122/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_122/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_122/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_122/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_122/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_122/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_122/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_122/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_122/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_122/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_122/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_122/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_122/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_122/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB13_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `anon_2__GB14_tempName`
Numbers of forward move = 0, and backward move = 60
Retimed registers names:
core1/core/cores_94/backward/currentState_reg[0]_bret__0
core1/core/cores_94/backward/currentState_reg[0]_bret__1
core1/core/cores_94/backward/currentState_reg[0]_bret__4
core1/core/cores_94/backward/currentState_reg[0]_bret_bret
core1/core/cores_94/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_94/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_94/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_94/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_94/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_94/backward/currentState_reg[1]_bret
core1/core/cores_94/backward/currentState_reg[1]_bret__3
core1/core/cores_94/backward/currentState_reg[2]_bret
core1/core/cores_94/backward/currentState_reg[2]_bret__3
core1/core/cores_94/backward/currentState_reg[3]_bret
core1/core/cores_94/backward/currentState_reg[3]_bret__3
core1/core/cores_94/backward/currentState_reg[4]_bret
core1/core/cores_94/backward/currentState_reg[4]_bret__3
core1/core/cores_94/backward/currentState_reg[5]_bret
core1/core/cores_94/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_94/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_94/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_94/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_94/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_94/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_94/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_94/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_94/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_94/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_94/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_94/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_94/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_94/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_94/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_94/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_94/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_94/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_94/backward/currentState_reg[5]_bret__3
core1/core/cores_95/backward/currentState_reg[0]_bret__0
core1/core/cores_95/backward/currentState_reg[0]_bret__1
core1/core/cores_95/backward/currentState_reg[0]_bret__4
core1/core/cores_95/backward/currentState_reg[0]_bret_bret
core1/core/cores_95/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_95/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_95/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_95/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_95/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_95/backward/currentState_reg[1]_bret
core1/core/cores_95/backward/currentState_reg[1]_bret__3
core1/core/cores_95/backward/currentState_reg[2]_bret
core1/core/cores_95/backward/currentState_reg[2]_bret__3
core1/core/cores_95/backward/currentState_reg[3]_bret
core1/core/cores_95/backward/currentState_reg[3]_bret__3
core1/core/cores_95/backward/currentState_reg[4]_bret
core1/core/cores_95/backward/currentState_reg[4]_bret__3
core1/core/cores_95/backward/currentState_reg[5]_bret
core1/core/cores_95/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_95/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_95/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_95/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_95/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_95/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_95/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_95/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_95/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_95/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_95/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_95/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_95/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_95/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_95/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_95/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_95/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_95/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_95/backward/currentState_reg[5]_bret__3
core1/core/cores_96/backward/currentState_reg[0]_bret__0
core1/core/cores_96/backward/currentState_reg[0]_bret__1
core1/core/cores_96/backward/currentState_reg[0]_bret__4
core1/core/cores_96/backward/currentState_reg[0]_bret_bret
core1/core/cores_96/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_96/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_96/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_96/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_96/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_96/backward/currentState_reg[1]_bret
core1/core/cores_96/backward/currentState_reg[1]_bret__3
core1/core/cores_96/backward/currentState_reg[2]_bret
core1/core/cores_96/backward/currentState_reg[2]_bret__3
core1/core/cores_96/backward/currentState_reg[3]_bret
core1/core/cores_96/backward/currentState_reg[3]_bret__3
core1/core/cores_96/backward/currentState_reg[4]_bret
core1/core/cores_96/backward/currentState_reg[4]_bret__3
core1/core/cores_96/backward/currentState_reg[5]_bret
core1/core/cores_96/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_96/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_96/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_96/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_96/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_96/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_96/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_96/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_96/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_96/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_96/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_96/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_96/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_96/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_96/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_96/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_96/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_96/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_96/backward/currentState_reg[5]_bret__3
core1/core/cores_97/backward/currentState_reg[0]_bret__0
core1/core/cores_97/backward/currentState_reg[0]_bret__1
core1/core/cores_97/backward/currentState_reg[0]_bret__4
core1/core/cores_97/backward/currentState_reg[0]_bret_bret
core1/core/cores_97/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_97/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_97/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_97/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_97/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_97/backward/currentState_reg[1]_bret
core1/core/cores_97/backward/currentState_reg[1]_bret__3
core1/core/cores_97/backward/currentState_reg[2]_bret
core1/core/cores_97/backward/currentState_reg[2]_bret__3
core1/core/cores_97/backward/currentState_reg[3]_bret
core1/core/cores_97/backward/currentState_reg[3]_bret__3
core1/core/cores_97/backward/currentState_reg[4]_bret
core1/core/cores_97/backward/currentState_reg[4]_bret__3
core1/core/cores_97/backward/currentState_reg[5]_bret
core1/core/cores_97/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_97/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_97/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_97/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_97/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_97/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_97/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_97/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_97/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_97/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_97/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_97/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_97/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_97/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_97/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_97/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_97/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_97/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_97/backward/currentState_reg[5]_bret__3
core1/core/cores_98/backward/currentState_reg[0]_bret__0
core1/core/cores_98/backward/currentState_reg[0]_bret__1
core1/core/cores_98/backward/currentState_reg[0]_bret__4
core1/core/cores_98/backward/currentState_reg[0]_bret_bret
core1/core/cores_98/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_98/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_98/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_98/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_98/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_98/backward/currentState_reg[1]_bret
core1/core/cores_98/backward/currentState_reg[1]_bret__3
core1/core/cores_98/backward/currentState_reg[2]_bret
core1/core/cores_98/backward/currentState_reg[2]_bret__3
core1/core/cores_98/backward/currentState_reg[3]_bret
core1/core/cores_98/backward/currentState_reg[3]_bret__3
core1/core/cores_98/backward/currentState_reg[4]_bret
core1/core/cores_98/backward/currentState_reg[4]_bret__3
core1/core/cores_98/backward/currentState_reg[5]_bret
core1/core/cores_98/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_98/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_98/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_98/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_98/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_98/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_98/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_98/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_98/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_98/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_98/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_98/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_98/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_98/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_98/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_98/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_98/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_98/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_98/backward/currentState_reg[5]_bret__3
core1/core/cores_99/backward/currentState_reg[0]_bret__0
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core1/core/cores_99/backward/currentState_reg[0]_bret__4
core1/core/cores_99/backward/currentState_reg[0]_bret_bret
core1/core/cores_99/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_99/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_99/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_99/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_99/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_99/backward/currentState_reg[1]_bret
core1/core/cores_99/backward/currentState_reg[1]_bret__3
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core1/core/cores_99/backward/currentState_reg[2]_bret__3
core1/core/cores_99/backward/currentState_reg[3]_bret
core1/core/cores_99/backward/currentState_reg[3]_bret__3
core1/core/cores_99/backward/currentState_reg[4]_bret
core1/core/cores_99/backward/currentState_reg[4]_bret__3
core1/core/cores_99/backward/currentState_reg[5]_bret
core1/core/cores_99/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_99/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_99/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_99/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_99/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_99/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_99/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_99/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_99/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_99/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_99/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_99/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_99/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_99/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_99/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_99/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_99/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_99/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_99/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB14_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB15_tempName`
Numbers of forward move = 0, and backward move = 80
Retimed registers names:
core1/core/cores_86/backward/currentState_reg[0]_bret__0
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core1/core/cores_86/backward/currentState_reg[1]_bret__3
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core1/core/cores_86/backward/currentState_reg[2]_bret__3
core1/core/cores_86/backward/currentState_reg[3]_bret
core1/core/cores_86/backward/currentState_reg[3]_bret__3
core1/core/cores_86/backward/currentState_reg[4]_bret
core1/core/cores_86/backward/currentState_reg[4]_bret__3
core1/core/cores_86/backward/currentState_reg[5]_bret
core1/core/cores_86/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_86/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_86/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_86/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_86/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_86/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_86/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_86/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_86/backward/currentState_reg[5]_bret__1_bret__1
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core1/core/cores_86/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_86/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_86/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_86/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_86/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_86/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_86/backward/currentState_reg[5]_bret__3
core1/core/cores_87/backward/currentState_reg[0]_bret__0
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core1/core/cores_87/backward/currentState_reg[0]_bret_bret
core1/core/cores_87/backward/currentState_reg[0]_bret_bret__0
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core1/core/cores_87/backward/currentState_reg[0]_bret_bret__2
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core1/core/cores_87/backward/currentState_reg[1]_bret__3
core1/core/cores_87/backward/currentState_reg[2]_bret
core1/core/cores_87/backward/currentState_reg[2]_bret__3
core1/core/cores_87/backward/currentState_reg[3]_bret
core1/core/cores_87/backward/currentState_reg[3]_bret__3
core1/core/cores_87/backward/currentState_reg[4]_bret
core1/core/cores_87/backward/currentState_reg[4]_bret__3
core1/core/cores_87/backward/currentState_reg[5]_bret
core1/core/cores_87/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_87/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_87/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_87/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_87/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_87/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_87/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_87/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_87/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_87/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_87/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_87/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_87/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_87/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_87/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_87/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_87/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_87/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_87/backward/currentState_reg[5]_bret__3
core1/core/cores_88/backward/currentState_reg[0]_bret__0
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core1/core/cores_88/backward/currentState_reg[0]_bret_bret
core1/core/cores_88/backward/currentState_reg[0]_bret_bret__0
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core1/core/cores_88/backward/currentState_reg[4]_bret__3
core1/core/cores_88/backward/currentState_reg[5]_bret
core1/core/cores_88/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_88/backward/currentState_reg[5]_bret__0_bret__0
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core1/core/cores_88/backward/currentState_reg[5]_bret__1_bret__0
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core1/core/cores_88/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_88/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_88/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_88/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_88/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_88/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_88/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_88/backward/currentState_reg[5]_bret__2_bret__3
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core1/core/cores_88/backward/currentState_reg[5]_bret__3
core1/core/cores_89/backward/currentState_reg[0]_bret__0
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core1/core/cores_89/backward/currentState_reg[0]_bret_bret
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core1/core/cores_89/backward/currentState_reg[1]_bret
core1/core/cores_89/backward/currentState_reg[1]_bret__3
core1/core/cores_89/backward/currentState_reg[2]_bret
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core1/core/cores_89/backward/currentState_reg[3]_bret
core1/core/cores_89/backward/currentState_reg[3]_bret__3
core1/core/cores_89/backward/currentState_reg[4]_bret
core1/core/cores_89/backward/currentState_reg[4]_bret__3
core1/core/cores_89/backward/currentState_reg[5]_bret
core1/core/cores_89/backward/currentState_reg[5]_bret__0_bret
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core1/core/cores_89/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_89/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_89/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_89/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_89/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_89/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_89/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_89/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_89/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_89/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_89/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_89/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_89/backward/currentState_reg[5]_bret__3
core1/core/cores_90/backward/currentState_reg[0]_bret__0
core1/core/cores_90/backward/currentState_reg[0]_bret__1
core1/core/cores_90/backward/currentState_reg[0]_bret__4
core1/core/cores_90/backward/currentState_reg[0]_bret_bret
core1/core/cores_90/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_90/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_90/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_90/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_90/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_90/backward/currentState_reg[1]_bret
core1/core/cores_90/backward/currentState_reg[1]_bret__3
core1/core/cores_90/backward/currentState_reg[2]_bret
core1/core/cores_90/backward/currentState_reg[2]_bret__3
core1/core/cores_90/backward/currentState_reg[3]_bret
core1/core/cores_90/backward/currentState_reg[3]_bret__3
core1/core/cores_90/backward/currentState_reg[4]_bret
core1/core/cores_90/backward/currentState_reg[4]_bret__3
core1/core/cores_90/backward/currentState_reg[5]_bret
core1/core/cores_90/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_90/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_90/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_90/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_90/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_90/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_90/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_90/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_90/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_90/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_90/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_90/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_90/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_90/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_90/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_90/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_90/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_90/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_90/backward/currentState_reg[5]_bret__3
core1/core/cores_91/backward/currentState_reg[0]_bret__0
core1/core/cores_91/backward/currentState_reg[0]_bret__1
core1/core/cores_91/backward/currentState_reg[0]_bret__4
core1/core/cores_91/backward/currentState_reg[0]_bret_bret
core1/core/cores_91/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_91/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_91/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_91/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_91/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_91/backward/currentState_reg[1]_bret
core1/core/cores_91/backward/currentState_reg[1]_bret__3
core1/core/cores_91/backward/currentState_reg[2]_bret
core1/core/cores_91/backward/currentState_reg[2]_bret__3
core1/core/cores_91/backward/currentState_reg[3]_bret
core1/core/cores_91/backward/currentState_reg[3]_bret__3
core1/core/cores_91/backward/currentState_reg[4]_bret
core1/core/cores_91/backward/currentState_reg[4]_bret__3
core1/core/cores_91/backward/currentState_reg[5]_bret
core1/core/cores_91/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_91/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_91/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_91/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_91/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_91/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_91/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_91/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_91/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_91/backward/currentState_reg[5]_bret__1_bret__2
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core1/core/cores_91/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_91/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_91/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_91/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_91/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_91/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_91/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_91/backward/currentState_reg[5]_bret__3
core1/core/cores_92/backward/currentState_reg[0]_bret__0
core1/core/cores_92/backward/currentState_reg[0]_bret__1
core1/core/cores_92/backward/currentState_reg[0]_bret__4
core1/core/cores_92/backward/currentState_reg[0]_bret_bret
core1/core/cores_92/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_92/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_92/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_92/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_92/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_92/backward/currentState_reg[1]_bret
core1/core/cores_92/backward/currentState_reg[1]_bret__3
core1/core/cores_92/backward/currentState_reg[2]_bret
core1/core/cores_92/backward/currentState_reg[2]_bret__3
core1/core/cores_92/backward/currentState_reg[3]_bret
core1/core/cores_92/backward/currentState_reg[3]_bret__3
core1/core/cores_92/backward/currentState_reg[4]_bret
core1/core/cores_92/backward/currentState_reg[4]_bret__3
core1/core/cores_92/backward/currentState_reg[5]_bret
core1/core/cores_92/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_92/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_92/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_92/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_92/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_92/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_92/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_92/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_92/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_92/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_92/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_92/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_92/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_92/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_92/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_92/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_92/backward/currentState_reg[5]_bret__2_bret__3
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core1/core/cores_93/backward/currentState_reg[0]_bret__4
core1/core/cores_93/backward/currentState_reg[0]_bret_bret
core1/core/cores_93/backward/currentState_reg[0]_bret_bret__0
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core1/core/cores_93/backward/currentState_reg[0]_bret_bret__2
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core1/core/cores_93/backward/currentState_reg[2]_bret__3
core1/core/cores_93/backward/currentState_reg[3]_bret
core1/core/cores_93/backward/currentState_reg[3]_bret__3
core1/core/cores_93/backward/currentState_reg[4]_bret
core1/core/cores_93/backward/currentState_reg[4]_bret__3
core1/core/cores_93/backward/currentState_reg[5]_bret
core1/core/cores_93/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_93/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_93/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_93/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_93/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_93/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_93/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_93/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_93/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_93/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_93/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_93/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_93/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_93/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_93/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_93/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_93/backward/currentState_reg[5]_bret__2_bret__3
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core1/core/cores_93/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB15_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB16_tempName`
Numbers of forward move = 0, and backward move = 100
Retimed registers names:
core1/core/cores_104/backward/currentState_reg[0]_bret__0
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core1/core/cores_104/backward/currentState_reg[2]_bret__3
core1/core/cores_104/backward/currentState_reg[3]_bret
core1/core/cores_104/backward/currentState_reg[3]_bret__3
core1/core/cores_104/backward/currentState_reg[4]_bret
core1/core/cores_104/backward/currentState_reg[4]_bret__3
core1/core/cores_104/backward/currentState_reg[5]_bret
core1/core/cores_104/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_104/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_104/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_104/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_104/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_104/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_104/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_104/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_104/backward/currentState_reg[5]_bret__1_bret__1
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core1/core/cores_104/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_104/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_104/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_104/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_104/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_104/backward/currentState_reg[5]_bret__2_bret__4
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core1/core/cores_77/backward/currentState_reg[0]_bret__0
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core1/core/cores_77/backward/currentState_reg[0]_bret_bret
core1/core/cores_77/backward/currentState_reg[0]_bret_bret__0
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core1/core/cores_77/backward/currentState_reg[0]_bret_bret__2
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core1/core/cores_77/backward/currentState_reg[1]_bret__3
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core1/core/cores_77/backward/currentState_reg[2]_bret__3
core1/core/cores_77/backward/currentState_reg[3]_bret
core1/core/cores_77/backward/currentState_reg[3]_bret__3
core1/core/cores_77/backward/currentState_reg[4]_bret
core1/core/cores_77/backward/currentState_reg[4]_bret__3
core1/core/cores_77/backward/currentState_reg[5]_bret
core1/core/cores_77/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_77/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_77/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_77/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_77/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_77/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_77/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_77/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_77/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_77/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_77/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_77/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_77/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_77/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_77/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_77/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_77/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_77/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_77/backward/currentState_reg[5]_bret__3
core1/core/cores_78/backward/currentState_reg[0]_bret__0
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core1/core/cores_78/backward/currentState_reg[4]_bret__3
core1/core/cores_78/backward/currentState_reg[5]_bret
core1/core/cores_78/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_78/backward/currentState_reg[5]_bret__0_bret__0
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core1/core/cores_78/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_78/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_78/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_78/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_78/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_78/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_78/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_78/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_78/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_78/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_78/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_78/backward/currentState_reg[5]_bret__3
core1/core/cores_79/backward/currentState_reg[0]_bret__0
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core1/core/cores_79/backward/currentState_reg[0]_bret_bret
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core1/core/cores_79/backward/currentState_reg[1]_bret
core1/core/cores_79/backward/currentState_reg[1]_bret__3
core1/core/cores_79/backward/currentState_reg[2]_bret
core1/core/cores_79/backward/currentState_reg[2]_bret__3
core1/core/cores_79/backward/currentState_reg[3]_bret
core1/core/cores_79/backward/currentState_reg[3]_bret__3
core1/core/cores_79/backward/currentState_reg[4]_bret
core1/core/cores_79/backward/currentState_reg[4]_bret__3
core1/core/cores_79/backward/currentState_reg[5]_bret
core1/core/cores_79/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_79/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_79/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_79/backward/currentState_reg[5]_bret__0_bret__2
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core1/core/cores_80/backward/currentState_reg[1]_bret__3
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core1/core/cores_80/backward/currentState_reg[2]_bret__3
core1/core/cores_80/backward/currentState_reg[3]_bret
core1/core/cores_80/backward/currentState_reg[3]_bret__3
core1/core/cores_80/backward/currentState_reg[4]_bret
core1/core/cores_80/backward/currentState_reg[4]_bret__3
core1/core/cores_80/backward/currentState_reg[5]_bret
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core1/core/cores_80/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_80/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_80/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_80/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_80/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_80/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_80/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_80/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_80/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_80/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_80/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_80/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_80/backward/currentState_reg[5]_bret__3
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core1/core/cores_81/backward/currentState_reg[0]_bret_bret
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core1/core/cores_81/backward/currentState_reg[2]_bret__3
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core1/core/cores_81/backward/currentState_reg[3]_bret__3
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core1/core/cores_81/backward/currentState_reg[4]_bret__3
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core1/core/cores_81/backward/currentState_reg[5]_bret__1_bret__0
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core1/core/cores_81/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_81/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_81/backward/currentState_reg[5]_bret__1_bret__4
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core1/core/cores_81/backward/currentState_reg[5]_bret__2_bret__0
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core1/core/cores_81/backward/currentState_reg[5]_bret__2_bret__4
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core1/core/cores_82/backward/currentState_reg[0]_bret_bret
core1/core/cores_82/backward/currentState_reg[0]_bret_bret__0
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core1/core/cores_82/backward/currentState_reg[1]_bret__3
core1/core/cores_82/backward/currentState_reg[2]_bret
core1/core/cores_82/backward/currentState_reg[2]_bret__3
core1/core/cores_82/backward/currentState_reg[3]_bret
core1/core/cores_82/backward/currentState_reg[3]_bret__3
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core1/core/cores_82/backward/currentState_reg[4]_bret__3
core1/core/cores_82/backward/currentState_reg[5]_bret
core1/core/cores_82/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_82/backward/currentState_reg[5]_bret__0_bret__0
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core1/core/cores_82/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_82/backward/currentState_reg[5]_bret__2_bret__0
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core1/core/cores_82/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_82/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_82/backward/currentState_reg[5]_bret__2_bret__4
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core1/core/cores_83/backward/currentState_reg[0]_bret__0
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core1/core/cores_83/backward/currentState_reg[0]_bret_bret
core1/core/cores_83/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_83/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_83/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_83/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_83/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_83/backward/currentState_reg[1]_bret
core1/core/cores_83/backward/currentState_reg[1]_bret__3
core1/core/cores_83/backward/currentState_reg[2]_bret
core1/core/cores_83/backward/currentState_reg[2]_bret__3
core1/core/cores_83/backward/currentState_reg[3]_bret
core1/core/cores_83/backward/currentState_reg[3]_bret__3
core1/core/cores_83/backward/currentState_reg[4]_bret
core1/core/cores_83/backward/currentState_reg[4]_bret__3
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core1/core/cores_83/backward/currentState_reg[5]_bret__0_bret
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core1/core/cores_83/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_83/backward/currentState_reg[5]_bret__0_bret__3
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core1/core/cores_83/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_83/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_83/backward/currentState_reg[5]_bret__3
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core1/core/cores_84/backward/currentState_reg[0]_bret__4
core1/core/cores_84/backward/currentState_reg[0]_bret_bret
core1/core/cores_84/backward/currentState_reg[0]_bret_bret__0
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core1/core/cores_84/backward/currentState_reg[2]_bret__3
core1/core/cores_84/backward/currentState_reg[3]_bret
core1/core/cores_84/backward/currentState_reg[3]_bret__3
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core1/core/cores_84/backward/currentState_reg[4]_bret__3
core1/core/cores_84/backward/currentState_reg[5]_bret
core1/core/cores_84/backward/currentState_reg[5]_bret__0_bret
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core1/core/cores_84/backward/currentState_reg[5]_bret__0_bret__3
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core1/core/cores_84/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_84/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_84/backward/currentState_reg[5]_bret__1_bret__2
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core1/core/cores_84/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_84/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_84/backward/currentState_reg[5]_bret__2_bret__0
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core1/core/cores_84/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_84/backward/currentState_reg[5]_bret__2_bret__3
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core1/core/cores_85/backward/currentState_reg[0]_bret_bret__0
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core1/core/cores_85/backward/currentState_reg[2]_bret__3
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core1/core/cores_85/backward/currentState_reg[3]_bret__3
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core1/core/cores_85/backward/currentState_reg[4]_bret__3
core1/core/cores_85/backward/currentState_reg[5]_bret
core1/core/cores_85/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_85/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_85/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_85/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_85/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_85/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_85/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_85/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_85/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_85/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_85/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_85/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_85/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_85/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_85/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_85/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_85/backward/currentState_reg[5]_bret__2_bret__3
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INFO: [Synth 8-5816] Retiming module `anon_2__GB16_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Synth 8-5816] Retiming module `anon_2__GB17_tempName`
Numbers of forward move = 0, and backward move = 110
Retimed registers names:
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core1/core/cores_64/backward/currentState_reg[2]_bret__3
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core1/core/cores_64/backward/currentState_reg[4]_bret__3
core1/core/cores_64/backward/currentState_reg[5]_bret
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core1/core/cores_64/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_64/backward/currentState_reg[5]_bret__0_bret__3
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core1/core/cores_66/backward/currentState_reg[0]_bret_bret
core1/core/cores_66/backward/currentState_reg[0]_bret_bret__0
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core1/core/cores_66/backward/currentState_reg[1]_bret__3
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core1/core/cores_66/backward/currentState_reg[2]_bret__3
core1/core/cores_66/backward/currentState_reg[3]_bret
core1/core/cores_66/backward/currentState_reg[3]_bret__3
core1/core/cores_66/backward/currentState_reg[4]_bret
core1/core/cores_66/backward/currentState_reg[4]_bret__3
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core1/core/cores_75/backward/currentState_reg[5]_bret
core1/core/cores_75/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_75/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_75/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_75/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_75/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_75/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_75/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_75/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_75/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_75/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_75/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_75/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_75/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_75/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_75/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_75/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_75/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_75/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_75/backward/currentState_reg[5]_bret__3
core1/core/cores_76/backward/currentState_reg[0]_bret__0
core1/core/cores_76/backward/currentState_reg[0]_bret__1
core1/core/cores_76/backward/currentState_reg[0]_bret__4
core1/core/cores_76/backward/currentState_reg[0]_bret_bret
core1/core/cores_76/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_76/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_76/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_76/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_76/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_76/backward/currentState_reg[1]_bret
core1/core/cores_76/backward/currentState_reg[1]_bret__3
core1/core/cores_76/backward/currentState_reg[2]_bret
core1/core/cores_76/backward/currentState_reg[2]_bret__3
core1/core/cores_76/backward/currentState_reg[3]_bret
core1/core/cores_76/backward/currentState_reg[3]_bret__3
core1/core/cores_76/backward/currentState_reg[4]_bret
core1/core/cores_76/backward/currentState_reg[4]_bret__3
core1/core/cores_76/backward/currentState_reg[5]_bret
core1/core/cores_76/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_76/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_76/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_76/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_76/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_76/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_76/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_76/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_76/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_76/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_76/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_76/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_76/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_76/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_76/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_76/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_76/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_76/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_76/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB17_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5816] Retiming module `anon_2__GB18_tempName`
Numbers of forward move = 0, and backward move = 30
Retimed registers names:
core1/core/cores_124/backward/currentState_reg[0]_bret__0
core1/core/cores_124/backward/currentState_reg[0]_bret__1
core1/core/cores_124/backward/currentState_reg[0]_bret__4
core1/core/cores_124/backward/currentState_reg[0]_bret_bret
core1/core/cores_124/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_124/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_124/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_124/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_124/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_124/backward/currentState_reg[1]_bret
core1/core/cores_124/backward/currentState_reg[1]_bret__3
core1/core/cores_124/backward/currentState_reg[2]_bret
core1/core/cores_124/backward/currentState_reg[2]_bret__3
core1/core/cores_124/backward/currentState_reg[3]_bret
core1/core/cores_124/backward/currentState_reg[3]_bret__3
core1/core/cores_124/backward/currentState_reg[4]_bret
core1/core/cores_124/backward/currentState_reg[4]_bret__3
core1/core/cores_124/backward/currentState_reg[5]_bret
core1/core/cores_124/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_124/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_124/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_124/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_124/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_124/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_124/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_124/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_124/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_124/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_124/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_124/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_124/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_124/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_124/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_124/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_124/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_124/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_124/backward/currentState_reg[5]_bret__3
core1/core/cores_65/backward/currentState_reg[0]_bret__0
core1/core/cores_65/backward/currentState_reg[0]_bret__1
core1/core/cores_65/backward/currentState_reg[0]_bret__4
core1/core/cores_65/backward/currentState_reg[0]_bret_bret
core1/core/cores_65/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_65/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_65/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_65/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_65/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_65/backward/currentState_reg[1]_bret
core1/core/cores_65/backward/currentState_reg[1]_bret__3
core1/core/cores_65/backward/currentState_reg[2]_bret
core1/core/cores_65/backward/currentState_reg[2]_bret__3
core1/core/cores_65/backward/currentState_reg[3]_bret
core1/core/cores_65/backward/currentState_reg[3]_bret__3
core1/core/cores_65/backward/currentState_reg[4]_bret
core1/core/cores_65/backward/currentState_reg[4]_bret__3
core1/core/cores_65/backward/currentState_reg[5]_bret
core1/core/cores_65/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_65/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_65/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_65/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_65/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_65/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_65/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_65/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_65/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_65/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_65/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_65/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_65/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_65/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_65/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_65/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_65/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_65/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_65/backward/currentState_reg[5]_bret__3
core1/core/cores_69/backward/currentState_reg[0]_bret__0
core1/core/cores_69/backward/currentState_reg[0]_bret__1
core1/core/cores_69/backward/currentState_reg[0]_bret__4
core1/core/cores_69/backward/currentState_reg[0]_bret_bret
core1/core/cores_69/backward/currentState_reg[0]_bret_bret__0
core1/core/cores_69/backward/currentState_reg[0]_bret_bret__1
core1/core/cores_69/backward/currentState_reg[0]_bret_bret__2
core1/core/cores_69/backward/currentState_reg[0]_bret_bret__3
core1/core/cores_69/backward/currentState_reg[0]_bret_bret__4
core1/core/cores_69/backward/currentState_reg[1]_bret
core1/core/cores_69/backward/currentState_reg[1]_bret__3
core1/core/cores_69/backward/currentState_reg[2]_bret
core1/core/cores_69/backward/currentState_reg[2]_bret__3
core1/core/cores_69/backward/currentState_reg[3]_bret
core1/core/cores_69/backward/currentState_reg[3]_bret__3
core1/core/cores_69/backward/currentState_reg[4]_bret
core1/core/cores_69/backward/currentState_reg[4]_bret__3
core1/core/cores_69/backward/currentState_reg[5]_bret
core1/core/cores_69/backward/currentState_reg[5]_bret__0_bret
core1/core/cores_69/backward/currentState_reg[5]_bret__0_bret__0
core1/core/cores_69/backward/currentState_reg[5]_bret__0_bret__1
core1/core/cores_69/backward/currentState_reg[5]_bret__0_bret__2
core1/core/cores_69/backward/currentState_reg[5]_bret__0_bret__3
core1/core/cores_69/backward/currentState_reg[5]_bret__0_bret__4
core1/core/cores_69/backward/currentState_reg[5]_bret__1_bret
core1/core/cores_69/backward/currentState_reg[5]_bret__1_bret__0
core1/core/cores_69/backward/currentState_reg[5]_bret__1_bret__1
core1/core/cores_69/backward/currentState_reg[5]_bret__1_bret__2
core1/core/cores_69/backward/currentState_reg[5]_bret__1_bret__3
core1/core/cores_69/backward/currentState_reg[5]_bret__1_bret__4
core1/core/cores_69/backward/currentState_reg[5]_bret__2_bret
core1/core/cores_69/backward/currentState_reg[5]_bret__2_bret__0
core1/core/cores_69/backward/currentState_reg[5]_bret__2_bret__1
core1/core/cores_69/backward/currentState_reg[5]_bret__2_bret__2
core1/core/cores_69/backward/currentState_reg[5]_bret__2_bret__3
core1/core/cores_69/backward/currentState_reg[5]_bret__2_bret__4
core1/core/cores_69/backward/currentState_reg[5]_bret__3
INFO: [Synth 8-5816] Retiming module `anon_2__GB18_tempName' done
INFO: [Synth 8-5816] Retiming module `synthRx`
Numbers of forward move = 0, and backward move = 0
INFO: [Synth 8-5816] Retiming module `synthRx' done
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:06:00 ; elapsed = 00:07:28 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 21489 ; free virtual = 58627
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:06:24 ; elapsed = 00:07:52 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 21374 ; free virtual = 58624
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:06:24 ; elapsed = 00:07:53 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 21375 ; free virtual = 58625
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:06:50 ; elapsed = 00:08:19 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 21272 ; free virtual = 58522
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:06:53 ; elapsed = 00:08:22 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 21291 ; free virtual = 58541
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:06:57 ; elapsed = 00:08:25 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 21289 ; free virtual = 58539
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:06:58 ; elapsed = 00:08:26 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 21291 ; free virtual = 58541
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+------------+----------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+------------+----------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|synthRx | core1/core/cores_51/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_51/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_47/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_47/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_44/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_44/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_40/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_40/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_39/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_39/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_48/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_48/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_26/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_26/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_14/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_14/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_2/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_2/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_0/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_0/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_123/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_123/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_108/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_108/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_105/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_105/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_100/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_100/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_94/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_94/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_86/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_86/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_77/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_77/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_66/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_66/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_124/lastForRead_reg | 64 | 1 | YES | NO | YES | 0 | 2 |
|synthRx | core1/core/cores_124/reverse/lastForRead_reg | 63 | 1 | YES | NO | YES | 0 | 2 |
+------------+----------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
Retiming Report:
+--------------------+------+
|Retiming summary: | |
+--------------------+------+
|Forward Retiming | 2 |
|Backward Retiming | 1208 |
|New registers added | 4516 |
|Registers deleted | 732 |
+--------------------+------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------
Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+----------+------+
| |Cell |Count |
+------+----------+------+
|1 |CARRY8 | 1524|
|2 |LUT1 | 1042|
|3 |LUT2 | 13818|
|4 |LUT3 | 2660|
|5 |LUT4 | 41909|
|6 |LUT5 | 17226|
|7 |LUT6 | 59600|
|8 |MUXF7 | 4064|
|9 |MUXF8 | 244|
|10 |RAM128X1D | 127|
|11 |RAM64M8 | 370|
|12 |RAMB36E2 | 488|
|14 |SRLC32E | 76|
|15 |FDCE | 27713|
|16 |FDPE | 8270|
|17 |FDRE | 6919|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:06:58 ; elapsed = 00:08:27 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 21291 ; free virtual = 58541
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 128 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:06:34 ; elapsed = 00:08:09 . Memory (MB): peak = 7183.660 ; gain = 1656.980 ; free physical = 32719 ; free virtual = 69969
Synthesis Optimization Complete : Time (s): cpu = 00:07:02 ; elapsed = 00:08:31 . Memory (MB): peak = 7183.660 ; gain = 1907.105 ; free physical = 32742 ; free virtual = 69970
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 7183.660 ; gain = 0.000 ; free physical = 32554 ; free virtual = 69782
INFO: [Netlist 29-17] Analyzing 6329 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/doit.xdc]
Finished Parsing XDC File [/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/doit.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 7191.664 ; gain = 0.000 ; free physical = 32425 ; free virtual = 69652
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 497 instances were transformed.
RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 127 instances
RAM64M8 => RAM64M8 (RAMD64E(x8)): 370 instances
Synth Design complete, checksum: c54adb0c
INFO: [Common 17-83] Releasing license: Synthesis
1041 Infos, 202 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:07:43 ; elapsed = 00:09:13 . Memory (MB): peak = 7191.664 ; gain = 2023.867 ; free physical = 32850 ; free virtual = 70077
# write_checkpoint -force synthRx_after_synth.dcp
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-480] Writing timing data to binary archive.
INFO: [Common 17-1381] The checkpoint '/home/ltr/IdeaProjects/Chainsaw2/synthWorkspace/synthRx/synthRx_after_synth.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:40 ; elapsed = 00:00:23 . Memory (MB): peak = 7426.547 ; gain = 234.883 ; free physical = 32695 ; free virtual = 69923
# report_utilization
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 21:07:36 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_utilization
| Design : synthRx
| Device : xcvu9p-flga2104-2-i
| Speed File : -2
| Design State : Synthesized
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. BLOCKRAM
3. ARITHMETIC
4. I/O
5. CLOCK
6. ADVANCED
7. CONFIGURATION
8. Primitives
9. Black Boxes
10. Instantiated Netlists
11. SLR Connectivity
12. SLR Connectivity Matrix
13. SLR CLB Logic and Dedicated Block Utilization
14. SLR IO Utilization
1. CLB Logic
------------
+----------------------------+--------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+--------+-------+------------+-----------+-------+
| CLB LUTs* | 139037 | 0 | 0 | 1182240 | 11.76 |
| LUT as Logic | 135493 | 0 | 0 | 1182240 | 11.46 |
| LUT as Memory | 3544 | 0 | 0 | 591840 | 0.60 |
| LUT as Distributed RAM | 3468 | 0 | | | |
| LUT as Shift Register | 76 | 0 | | | |
| CLB Registers | 42902 | 0 | 0 | 2364480 | 1.81 |
| Register as Flip Flop | 42902 | 0 | 0 | 2364480 | 1.81 |
| Register as Latch | 0 | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 1524 | 0 | 0 | 147780 | 1.03 |
| F7 Muxes | 4318 | 0 | 0 | 591120 | 0.73 |
| F8 Muxes | 244 | 0 | 0 | 295560 | 0.08 |
| F9 Muxes | 0 | 0 | 0 | 147780 | 0.00 |
+----------------------------+--------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 8270 | Yes | - | Set |
| 27713 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 6919 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. BLOCKRAM
-----------
+-------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------+------+-------+------------+-----------+-------+
| Block RAM Tile | 488 | 0 | 0 | 2160 | 22.59 |
| RAMB36/FIFO* | 488 | 0 | 0 | 2160 | 22.59 |
| RAMB36E2 only | 488 | | | | |
| RAMB18 | 0 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 0 | 960 | 0.00 |
+-------------------+------+-------+------------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
3. ARITHMETIC
-------------
+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------+------+-------+------------+-----------+-------+
| DSPs | 0 | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+------------+-----------+-------+
4. I/O
------
+------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+------------+------+-------+------------+-----------+-------+
| Bonded IOB | 0 | 0 | 0 | 832 | 0.00 |
+------------+------+-------+------------+-----------+-------+
5. CLOCK
--------
+----------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------+------+-------+------------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 0 | 0 | 0 | 1800 | 0.00 |
| BUFGCE | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCE_DIV | 0 | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+------------+-----------+-------+
* Note: Each used BUFGCTRL counts as two GLOBAL CLOCK BUFFERs. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
6. ADVANCED
-----------
+-----------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-----------------+------+-------+------------+-----------+-------+
| CMACE4 | 0 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 0 | 52 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 0 | 13 | 0.00 |
| ILKNE4 | 0 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 0 | 26 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 0 | 26 | 0.00 |
| PCIE40E4 | 0 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 0 | 3 | 0.00 |
+-----------------+------+-------+------------+-----------+-------+
7. CONFIGURATION
----------------
+-------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------+------+-------+------------+-----------+-------+
| BSCANE2 | 0 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 0 | 3 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 0 | 3 | 0.00 |
| ICAPE3 | 0 | 0 | 0 | 6 | 0.00 |
| MASTER_JTAG | 0 | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 0 | 3 | 0.00 |
+-------------+------+-------+------------+-----------+-------+
8. Primitives
-------------
+----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+----------+-------+---------------------+
| LUT6 | 59600 | CLB |
| LUT4 | 41909 | CLB |
| FDCE | 27713 | Register |
| LUT5 | 17226 | CLB |
| LUT2 | 13818 | CLB |
| FDPE | 8270 | Register |
| FDRE | 6919 | Register |
| MUXF7 | 4318 | CLB |
| RAMD64E | 3468 | CLB |
| LUT3 | 2660 | CLB |
| CARRY8 | 1524 | CLB |
| LUT1 | 1042 | CLB |
| RAMB36E2 | 488 | BLOCKRAM |
| MUXF8 | 244 | CLB |
| SRLC32E | 76 | CLB |
+----------+-------+---------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. SLR Connectivity
--------------------
+----------------------------------+------+-------+-----------+-------+
| | Used | Fixed | Available | Util% |
+----------------------------------+------+-------+-----------+-------+
| SLR2 <-> SLR1 | 0 | | 17280 | 0.00 |
| SLR1 -> SLR2 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR2 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 <-> SLR0 | 0 | | 17280 | 0.00 |
| SLR0 -> SLR1 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
| SLR1 -> SLR0 | 0 | | | 0.00 |
| Using TX_REG only | 0 | 0 | | |
| Using RX_REG only | 0 | 0 | | |
| Using Both TX_REG and RX_REG | 0 | 0 | | |
+----------------------------------+------+-------+-----------+-------+
| Total SLLs Used | 0 | | | |
+----------------------------------+------+-------+-----------+-------+
12. SLR Connectivity Matrix
---------------------------
+-----------+------+------+------+
| FROM \ TO | SLR2 | SLR1 | SLR0 |
+-----------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+-----------+------+------+------+
13. SLR CLB Logic and Dedicated Block Utilization
-------------------------------------------------
+----------------------------+------+------+------+--------+--------+--------+
| Site Type | SLR0 | SLR1 | SLR2 | SLR0 % | SLR1 % | SLR2 % |
+----------------------------+------+------+------+--------+--------+--------+
| CLB | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBL | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLBM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB LUTs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Logic | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Memory | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| LUT as Shift Register | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CLB Registers | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| CARRY8 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| F9 Muxes | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Block RAM Tile | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB36/FIFO | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| RAMB18 | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| URAM | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| DSPs | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
| Unique Control Sets | 0 | 0 | 0 | 0.00 | 0.00 | 0.00 |
+----------------------------+------+------+------+--------+--------+--------+
* Note: Available Control Sets based on CLB Registers / 8
14. SLR IO Utilization
----------------------
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR Index | Used IOBs | (%)IOBs | Used IPADs | (%)IPADs | Used OPADs | (%)OPADs | GTs |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
| Total | 0 | | 0 | | 0 | | 0 |
+-----------+-----------+---------+------------+----------+------------+----------+-----+
# report_timing
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: I, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "clk" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Timing 38-78] ReportTimingParams: -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date : Tue Oct 25 21:08:02 2022
| Host : DarlingAlveo running 64-bit Ubuntu 18.04.2 LTS
| Command : report_timing
| Design : synthRx
| Device : xcvu9p-flga2104
| Speed File : -2 PRODUCTION 1.28 03-30-2022
| Temperature Grade : I
-----------------------------------------------------------------------------------------
Timing Report
Slack (VIOLATED) : -0.417ns (required time - arrival time)
Source: core1/core/cores_0/recordStack_reg_3/CLKARDCLK
(rising edge-triggered cell RAMB36E2 clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Destination: core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__0/D
(rising edge-triggered cell FDCE clocked by clk {rise@0.000ns fall@0.625ns period=1.250ns})
Path Group: clk
Path Type: Setup (Max at Slow Process Corner)
Requirement: 1.250ns (clk rise@1.250ns - clk rise@0.000ns)
Data Path Delay: 1.601ns (logic 1.171ns (73.142%) route 0.430ns (26.858%))
Logic Levels: 3 (LUT6=2 MUXF7=1)
Clock Path Skew: -0.056ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 0.020ns = ( 1.270 - 1.250 )
Source Clock Delay (SCD): 0.076ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk rise edge) 0.000 0.000 r
0.000 0.000 r clk (IN)
net (fo=47421, unset) 0.076 0.076 core1/core/cores_0/clk
RAMB36E2 r core1/core/cores_0/recordStack_reg_3/CLKARDCLK
------------------------------------------------------------------- -------------------
RAMB36E2 (Prop_RAMB36E2_CLKARDCLK_DOUTADOUT[18])
0.856 0.932 r core1/core/cores_0/recordStack_reg_3/DOUTADOUT[18]
net (fo=1, unplaced) 0.208 1.140 core1/core/cores_0/backward/_zz_recordStack_port1[234]
LUT6 (Prop_LUT6_I0_O) 0.150 1.290 r core1/core/cores_0/backward/currentState[5]_bret__0_bret__0_i_7__57/O
net (fo=1, unplaced) 0.018 1.308 core1/core/cores_0/backward/currentState[5]_bret__0_bret__0_i_7__57_n_0
MUXF7 (Prop_MUXF7_I1_O) 0.065 1.373 r core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__0_i_2__57/O
net (fo=1, unplaced) 0.156 1.529 core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__0_i_2__57_n_0
LUT6 (Prop_LUT6_I0_O) 0.100 1.629 r core1/core/cores_0/backward/currentState[5]_bret__0_bret__0_i_1__57/O
net (fo=1, unplaced) 0.048 1.677 core1/core/cores_0/backward/candidateDiscrepancies_0__123[2]
FDCE r core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__0/D
------------------------------------------------------------------- -------------------
(clock clk rise edge) 1.250 1.250 r
0.000 1.250 r clk (IN)
net (fo=47421, unset) 0.020 1.270 core1/core/cores_0/backward/clk
FDCE r core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__0/C
clock pessimism 0.000 1.270
clock uncertainty -0.035 1.235
FDCE (Setup_FDCE_C_D) 0.025 1.260 core1/core/cores_0/backward/currentState_reg[5]_bret__0_bret__0
-------------------------------------------------------------------
required time 1.260
arrival time -1.677
-------------------------------------------------------------------
slack -0.417
report_timing: Time (s): cpu = 00:00:43 ; elapsed = 00:00:26 . Memory (MB): peak = 7963.973 ; gain = 537.426 ; free physical = 32226 ; free virtual = 69454
INFO: [Common 17-206] Exiting Vivado at Tue Oct 25 21:08:03 2022...
-
[INFO ]
-
: binary adder cost = 70113
-
[INFO ]
-
: ternary adder cost = 9144
-
[INFO ]
-
: reg cost = 97939
-
[INFO ]
-
:
LUT: 139037
FF: 42902
DSP: 0
BRAM: 488
CARRY8: 1524
-
[INFO ]
-
:
fmax = 599.8800239952009 MHz